Changeset 0c47440 in rtems


Ignore:
Timestamp:
08/29/13 20:20:03 (9 years ago)
Author:
Karel Gardas <karel.gardas@…>
Branches:
4.11, 5, master
Children:
29f7d317
Parents:
47b6fad
git-author:
Karel Gardas <karel.gardas@…> (08/29/13 20:20:03)
git-committer:
Sebastian Huber <sebastian.huber@…> (09/02/13 07:06:20)
Message:

bsp/lm4f120: new BSP to support TI LM4F120 XL LaunchPad? board

Location:
c/src/lib/libbsp/arm/lm3s69xx
Files:
2 added
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lm3s69xx/configure.ac

    r47b6fad r0c47440  
    2626RTEMS_BSPOPTS_HELP([BSP_SMALL_MEMORY],[disable testsuite samples with high memory demands])
    2727
    28 RTEMS_BSPOPTS_SET([LM3S69XX_SYSTEM_CLOCK],[*],[50000000U])
     28RTEMS_BSPOPTS_SET([LM3S69XX_SYSTEM_CLOCK],[lm3s*],[50000000U])
     29RTEMS_BSPOPTS_SET([LM3S69XX_SYSTEM_CLOCK],[lm4f*],[80000000U])
    2930RTEMS_BSPOPTS_HELP([LM3S69XX_SYSTEM_CLOCK],[system clock in Hz])
    3031
    3132RTEMS_BSPOPTS_SET([LM3S69XX_XTAL_CONFIG],[lm3s6965*],[0xE]) dnl 8MHz XTAL
    3233RTEMS_BSPOPTS_SET([LM3S69XX_XTAL_CONFIG],[lm3s3749*],[0x10]) dnl 10MHz XTAL
     34RTEMS_BSPOPTS_SET([LM3S69XX_XTAL_CONFIG],[lm4f120*],[0x15]) dnl 16MHz XTAL
    3335RTEMS_BSPOPTS_HELP([LM3S69XX_XTAL_CONFIG],[crystal configuration for RCC register])
    3436
     
    5052RTEMS_BSPOPTS_SET([LM3S69XX_NUM_GPIO_BLOCKS],[lm3s3749*],[8])
    5153RTEMS_BSPOPTS_SET([LM3S69XX_NUM_GPIO_BLOCKS],[lm3s6965*],[7])
     54RTEMS_BSPOPTS_SET([LM3S69XX_NUM_GPIO_BLOCKS],[lm4f120*],[6])
    5255RTEMS_BSPOPTS_HELP([LM3S69XX_NUM_GPIO_BLOCKS],[number of GPIO blocks supported by MCU])
    5356
    5457RTEMS_BSPOPTS_SET([LM3S69XX_NUM_SSI_BLOCKS],[lm3s3749*],[2])
    5558RTEMS_BSPOPTS_SET([LM3S69XX_NUM_SSI_BLOCKS],[lm3s6965*],[1])
     59RTEMS_BSPOPTS_SET([LM3S69XX_NUM_SSI_BLOCKS],[lm4f120*],[4])
    5660RTEMS_BSPOPTS_HELP([LM3S69XX_NUM_SSI_BLOCKS],[number of SSI blocks supported by MCU])
    5761
    5862RTEMS_BSPOPTS_SET([LM3S69XX_HAS_UDMA],[lm3s3749*],[1])
     63RTEMS_BSPOPTS_SET([LM3S69XX_HAS_UDMA],[lm4f*],[1])
    5964RTEMS_BSPOPTS_SET([LM3S69XX_HAS_UDMA],[*],[0])
    6065RTEMS_BSPOPTS_HELP([LM3S69XX_HAS_UDMA],[defined if MCU supports UDMA])
    6166
    6267RTEMS_BSPOPTS_SET([LM3S69XX_USE_AHB_FOR_GPIO],[lm3s3749*],[1])
     68RTEMS_BSPOPTS_SET([LM3S69XX_USE_AHB_FOR_GPIO],[lm4f*],[1])
    6369RTEMS_BSPOPTS_SET([LM3S69XX_USE_AHB_FOR_GPIO],[*],[0])
    6470RTEMS_BSPOPTS_HELP([LM3S69XX_USE_AHB_FOR_GPIO],[use AHB apperture to access GPIO registers])
     
    7076RTEMS_BSPOPTS_HELP([LM3S69XX_MCU_LM3S6965],[board has LM3S6965 MCU])
    7177
     78RTEMS_BSPOPTS_SET([LM3S69XX_MCU_LM4F120],[lm4f120*],[1])
     79RTEMS_BSPOPTS_HELP([LM3S69XX_MCU_LM4F120],[board has LM4F120xxx MCU])
     80
    7281RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
    7382RTEMS_BSP_LINKCMDS
  • c/src/lib/libbsp/arm/lm3s69xx/include/lm3s69xx.h

    r47b6fad r0c47440  
    3333#define LM3S69XX_GPIO_E_BASE 0x4005c000
    3434#define LM3S69XX_GPIO_F_BASE 0x4005d000
     35#if LM3S69XX_NUM_GPIO_BLOCKS > 6
    3536#define LM3S69XX_GPIO_G_BASE 0x4005e000
    3637#if LM3S69XX_NUM_GPIO_BLOCKS > 7
    3738#define LM3S69XX_GPIO_H_BASE 0x4005f000
     39#endif
    3840#endif
    3941
     
    4648#define LM3S69XX_GPIO_E_BASE 0x40024000
    4749#define LM3S69XX_GPIO_F_BASE 0x40025000
     50#if LM3S69XX_NUM_GPIO_BLOCKS > 6
    4851#define LM3S69XX_GPIO_G_BASE 0x40026000
    4952#if LM3S69XX_NUM_GPIO_BLOCKS > 7
    5053#define LM3S69XX_GPIO_H_BASE 0x40027000
     54#endif
    5155#endif
    5256
     
    5963#if LM3S69XX_NUM_SSI_BLOCKS > 1
    6064#define LM3S69XX_SSI_1_BASE 0x40009000
     65#if LM3S69XX_NUM_SSI_BLOCKS > 2
     66#define LM3S69XX_SSI_2_BASE 0x4000A000
     67#if LM3S69XX_NUM_SSI_BLOCKS > 3
     68#define LM3S69XX_SSI_3_BASE 0x4000B000
     69#endif
     70#endif
    6171#endif
    6272
     
    195205
    196206#define SYSCONRCC2_USERCC2 BSP_BIT32(31)
     207#define SYSCONRCC2_DIV400 BSP_BIT32(30)
    197208#define SYSCONRCC2_SYSDIV2(val) BSP_FLD32(val, 23, 28)
    198 #define SYSCONRCC2_SYSDIV2_MSK(val) BSP_MSK32(23, 28)
     209#define SYSCONRCC2_SYSDIV2_MSK BSP_MSK32(23, 28)
     210#define SYSCONRCC2_SYSDIV2EXT(val) BSP_FLD32(val, 22, 28)
     211#define SYSCONRCC2_SYSDIV2EXT_MSK BSP_MSK32(22, 28)
    199212#define SYSCONRCC2_USBPWRDN BSP_BIT32(14)
    200213#define SYSCONRCC2_PWRDN2 BSP_BIT32(13)
  • c/src/lib/libbsp/arm/lm3s69xx/include/syscon.h

    r47b6fad r0c47440  
    1919void lm3s69xx_syscon_enable_pwm_clock(bool enable);
    2020void lm3s69xx_syscon_set_pwmdiv(unsigned int div);
     21void lm3s69xx_syscon_delay_3x_clocks(unsigned long x_count);
    2122
    2223#ifdef __cplusplus
  • c/src/lib/libbsp/arm/lm3s69xx/ssi/ssi.c

    r47b6fad r0c47440  
    135135  .idle_char = 0xffff,
    136136  .io_configs = {
    137 #if defined(LM3S69XX_MCU_LM3S3749) || defined(LM3S69XX_MCU_LM3S6965)
     137#if defined(LM3S69XX_MCU_LM3S3749) || defined(LM3S69XX_MCU_LM3S6965) || defined(LM3S69XX_MCU_LM4F120)
    138138    LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_A, 2), /* CLK */
    139139    LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_A, 5), /* TX */
     
    157157  .idle_char = 0xffff,
    158158  .io_configs = {
    159 #if defined(LM3S69XX_MCU_LM3S3749)
     159#if defined(LM3S69XX_MCU_LM3S3749) || defined(LM3S69XX_MCU_LM4F120)
    160160    LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_E, 0), /* CLK */
    161161    LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_E, 3), /* TX */
  • c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c

    r47b6fad r0c47440  
    2020
    2121  uint32_t sysdiv_val = LM3S69XX_PLL_FREQUENCY / LM3S69XX_SYSTEM_CLOCK;
     22#if defined(LM3S69XX_MCU_LM3S6965) || defined(LM3S69XX_MCU_LM3S3749)
    2223  assert(sysdiv_val * LM3S69XX_SYSTEM_CLOCK == LM3S69XX_PLL_FREQUENCY);
     24#endif
    2325  assert((sysdiv_val >= 4) && (sysdiv_val <= 16));
    2426
    2527  uint32_t rcc = syscon->rcc;
     28  uint32_t rcc2 = syscon->rcc2;
    2629
    2730  rcc = (rcc & ~SYSCONRCC_USESYSDIV) | SYSCONRCC_BYPASS;
     31  rcc2 |= SYSCONRCC2_BYPASS2;
     32
     33  syscon->rcc = rcc;
     34  syscon->rcc2 = rcc2;
     35
     36  /*
     37   As per a note in Stellaris® LM4F120H5QR Microcontroller Data
     38   Sheet on page 219: "When transitioning the system clock
     39   configuration to use the MOSC as the fundamental clock source, the
     40   MOSCDIS bit must be set prior to reselecting the MOSC or an
     41   undefined system clock configuration can sporadically occur."
     42  */
     43
     44  rcc |= SYSCONRCC_MOSCDIS;
    2845  syscon->rcc = rcc;
    2946
    30   rcc = (rcc & ~(SYSCONRCC_PWRDN | SYSCONRCC_XTAL_MSK | SYSCONRCC_OSCSRC_MSK))
    31       | SYSCONRCC_XTAL(LM3S69XX_XTAL_CONFIG) | SYSCONRCC_OSCSRC_MOSC;
     47  rcc = (rcc & ~(SYSCONRCC_XTAL_MSK))
     48      | SYSCONRCC_XTAL(LM3S69XX_XTAL_CONFIG);
     49  rcc2 = (rcc2 & ~(SYSCONRCC2_PWRDN2 | SYSCONRCC2_OSCSRC2_MSK))
     50      | SYSCONRCC2_USERCC2 | SYSCONRCC2_OSCSRC2(0x0);
     51
     52  /* clear PLL lock interrupt */
     53  syscon->misc &= (SYSCONMISC_PLLLMIS);
     54
    3255  syscon->rcc = rcc;
     56  syscon->rcc2 = rcc2;
     57  lm3s69xx_syscon_delay_3x_clocks(16);
    3358
    34   rcc = (rcc & ~SYSCONRCC_SYSDIV_MSK) | SYSCONRCC_SYSDIV(sysdiv_val / 2 - 1)
    35       | SYSCONRCC_USESYSDIV;
    36   syscon->rcc = rcc;
     59  /* since now, we'll use only RCC2 as SYSCONRCC2_USERCC2 and XTAL
     60     (only available in RCC) are already set */
     61
     62  if (sysdiv_val % 2 == 0) {
     63      rcc2 = (rcc2 & ~SYSCONRCC2_SYSDIV2_MSK) | SYSCONRCC2_SYSDIV2(sysdiv_val / 2 - 1);
     64
     65      rcc2 &= ~(SYSCONRCC2_DIV400);
     66  }
     67  else {
     68      /* need to use DIV400 */
     69      rcc2 = (rcc2 & ~SYSCONRCC2_SYSDIV2EXT_MSK) | SYSCONRCC2_SYSDIV2EXT(sysdiv_val - 1)
     70          | SYSCONRCC2_DIV400;
     71  }
     72  syscon->rcc2 = rcc2;
    3773
    3874  while ((syscon->ris & SYSCONRIS_PLLLRIS) == 0)
    3975      /* Wait for PLL lock */;
    4076
    41   rcc &= ~SYSCONRCC_BYPASS;
    42   syscon->rcc = rcc;
     77  rcc2 &= ~(SYSCONRCC2_BYPASS2);
     78
     79  syscon->rcc2 = rcc2;
     80  lm3s69xx_syscon_delay_3x_clocks(16);
    4381}
    4482
    4583static const lm3s69xx_gpio_config start_config_gpio[] = {
    4684#ifdef LM3S69XX_ENABLE_UART_0
    47 #if defined(LM3S69XX_MCU_LM3S3749) || defined(LM3S69XX_MCU_LM3S6965)
     85#if defined(LM3S69XX_MCU_LM3S3749) || defined(LM3S69XX_MCU_LM3S6965) || defined(LM3S69XX_MCU_LM4F120)
    4886  LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_A, 0),
    4987  LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_A, 1),
     
    6098  LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_D, 2),
    6199  LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_D, 3),
     100#elif defined(LM3S69XX_MCU_LM4F120)
     101  LM3S69XX_PIN_UART_RX(LM3S69XX_PORT_B, 0),
     102  LM3S69XX_PIN_UART_TX(LM3S69XX_PORT_B, 1),
     103  LM3S69XX_PIN_UART_RTS(LM3S69XX_PORT_C, 4),
     104  LM3S69XX_PIN_UART_CTS(LM3S69XX_PORT_C, 5),
    62105#else
    63106#error No GPIO pin configuration for UART 1
     
    86129      | SYSCONGPIOHBCTL_PORTC | SYSCONGPIOHBCTL_PORTD
    87130      | SYSCONGPIOHBCTL_PORTE | SYSCONGPIOHBCTL_PORTF
     131#if LM3S69XX_NUM_GPIO_BLOCKS > 6
    88132      | SYSCONGPIOHBCTL_PORTG
    89133#if LM3S69XX_NUM_GPIO_BLOCKS > 7
    90134      | SYSCONGPIOHBCTL_PORTH
     135#endif
    91136#endif
    92137      ;
  • c/src/lib/libbsp/arm/lm3s69xx/startup/syscon.c

    r47b6fad r0c47440  
    1717      "nop\n\t"
    1818      "nop");
     19}
     20
     21void __attribute__((naked)) lm3s69xx_syscon_delay_3x_clocks(unsigned long x_count)
     22{
     23    asm volatile(
     24                 "subs  r0, #1\n\t"
     25                 "bne   lm3s69xx_syscon_delay_3x_clocks\n\t"
     26                 "bx    lr"
     27                 );
    1928}
    2029
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