Ignore:
Timestamp:
Apr 4, 2012, 1:39:46 PM (8 years ago)
Author:
Jennifer Averett <jennifer.averett@…>
Branches:
4.11, 5, master
Children:
a36d1b4
Parents:
eb6362dc
git-author:
Jennifer Averett <jennifer.averett@…> (04/04/12 13:39:46)
git-committer:
Joel Sherrill <joel.sherrill@…> (04/04/12 13:43:08)
Message:

PR 1993 - Convert MIPS to PIC IRQ model

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/mips/au1x00/include/au1x00.h

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 *  AMD AU1X00 specific information
     5 */
     6
    17/*
    2  *  AMD AU1X00 specific information
    3  *
    4  * Copyright (c) 2005 by Cogent Computer Systems
    5  * Written by Jay Monkman <jtm@lopingdog.com>
     8 *  Copyright (c) 2005 by Cogent Computer Systems
     9 *  Written by Jay Monkman <jtm@lopingdog.com>
    610 *
    711 *  The license and distribution terms for this file may be
    812 *  found in the file LICENSE in this distribution or at
    9  *
    1013 *  http://www.rtems.com/license/LICENSE.
    11  *
     14 * 
    1215 *  $Id$
    13  *
    1416 */
    1517
     
    429431extern au1x00_uart_t *uart3;
    430432
    431 /*
    432  *  Interrupt Vector Numbers
    433  *
    434  */
    435 /* MIPS_INTERRUPT_BASE should be 32 (0x20) */
    436 #define AU1X00_IRQ_SW0                (MIPS_INTERRUPT_BASE + 0)
    437 #define AU1X00_IRQ_SW1                (MIPS_INTERRUPT_BASE + 1)
    438 #define AU1X00_IRQ_IC0_REQ0           (MIPS_INTERRUPT_BASE + 2)
    439 #define AU1X00_IRQ_IC0_REQ1           (MIPS_INTERRUPT_BASE + 3)
    440 #define AU1X00_IRQ_IC1_REQ0           (MIPS_INTERRUPT_BASE + 4)
    441 #define AU1X00_IRQ_IC1_REQ1           (MIPS_INTERRUPT_BASE + 5)
    442 #define AU1X00_IRQ_PERF               (MIPS_INTERRUPT_BASE + 6)
    443 #define AU1X00_IRQ_CNT                (MIPS_INTERRUPT_BASE + 7)
    444 
    445 #define AU1X00_IRQ_IC0_BASE           (MIPS_INTERRUPT_BASE + 8)
    446 #define AU1X00_IRQ_UART0              (MIPS_INTERRUPT_BASE + 8)
    447 #define AU1X00_IRQ_INTA               (MIPS_INTERRUPT_BASE + 9)
    448 #define AU1X00_IRQ_INTB               (MIPS_INTERRUPT_BASE + 10)
    449 #define AU1X00_IRQ_UART3              (MIPS_INTERRUPT_BASE + 11)
    450 #define AU1X00_IRQ_INTC               (MIPS_INTERRUPT_BASE + 12)
    451 #define AU1X00_IRQ_INTD               (MIPS_INTERRUPT_BASE + 13)
    452 #define AU1X00_IRQ_DMA0               (MIPS_INTERRUPT_BASE + 14)
    453 #define AU1X00_IRQ_DMA1               (MIPS_INTERRUPT_BASE + 15)
    454 #define AU1X00_IRQ_DMA2               (MIPS_INTERRUPT_BASE + 16)
    455 #define AU1X00_IRQ_DMA3               (MIPS_INTERRUPT_BASE + 17)
    456 #define AU1X00_IRQ_DMA4               (MIPS_INTERRUPT_BASE + 18)
    457 #define AU1X00_IRQ_DMA5               (MIPS_INTERRUPT_BASE + 19)
    458 #define AU1X00_IRQ_DMA6               (MIPS_INTERRUPT_BASE + 20)
    459 #define AU1X00_IRQ_DMA7               (MIPS_INTERRUPT_BASE + 21)
    460 #define AU1X00_IRQ_TOY_TICK           (MIPS_INTERRUPT_BASE + 22)
    461 #define AU1X00_IRQ_TOY_MATCH0         (MIPS_INTERRUPT_BASE + 23)
    462 #define AU1X00_IRQ_TOY_MATCH1         (MIPS_INTERRUPT_BASE + 24)
    463 #define AU1X00_IRQ_TOY_MATCH2         (MIPS_INTERRUPT_BASE + 25)
    464 #define AU1X00_IRQ_RTC_TICK           (MIPS_INTERRUPT_BASE + 26)
    465 #define AU1X00_IRQ_RTC_MATCH0         (MIPS_INTERRUPT_BASE + 27)
    466 #define AU1X00_IRQ_RTC_MATCH1         (MIPS_INTERRUPT_BASE + 28)
    467 #define AU1X00_IRQ_RTC_MATCH2         (MIPS_INTERRUPT_BASE + 29)
    468 #define AU1X00_IRQ_PCI_ERR            (MIPS_INTERRUPT_BASE + 30)
    469 #define AU1X00_IRQ_RSV0               (MIPS_INTERRUPT_BASE + 31)
    470 #define AU1X00_IRQ_USB_DEV            (MIPS_INTERRUPT_BASE + 32)
    471 #define AU1X00_IRQ_USB_SUSPEND        (MIPS_INTERRUPT_BASE + 33)
    472 #define AU1X00_IRQ_USB_HOST           (MIPS_INTERRUPT_BASE + 34)
    473 #define AU1X00_IRQ_AC97_ACSYNC        (MIPS_INTERRUPT_BASE + 35)
    474 #define AU1X00_IRQ_MAC0               (MIPS_INTERRUPT_BASE + 36)
    475 #define AU1X00_IRQ_MAC1               (MIPS_INTERRUPT_BASE + 37)
    476 #define AU1X00_IRQ_RSV1               (MIPS_INTERRUPT_BASE + 38)
    477 #define AU1X00_IRQ_AC97_CMD           (MIPS_INTERRUPT_BASE + 39)
    478 
    479 #define AU1X00_IRQ_IC1_BASE           (MIPS_INTERRUPT_BASE + 40)
    480 #define AU1X00_IRQ_GPIO0              (MIPS_INTERRUPT_BASE + 40)
    481 #define AU1X00_IRQ_GPIO1              (MIPS_INTERRUPT_BASE + 41)
    482 #define AU1X00_IRQ_GPIO2              (MIPS_INTERRUPT_BASE + 42)
    483 #define AU1X00_IRQ_GPIO3              (MIPS_INTERRUPT_BASE + 43)
    484 #define AU1X00_IRQ_GPIO4              (MIPS_INTERRUPT_BASE + 44)
    485 #define AU1X00_IRQ_GPIO5              (MIPS_INTERRUPT_BASE + 45)
    486 #define AU1X00_IRQ_GPIO6              (MIPS_INTERRUPT_BASE + 46)
    487 #define AU1X00_IRQ_GPIO7              (MIPS_INTERRUPT_BASE + 47)
    488 #define AU1X00_IRQ_GPIO8              (MIPS_INTERRUPT_BASE + 48)
    489 #define AU1X00_IRQ_GPIO9              (MIPS_INTERRUPT_BASE + 49)
    490 #define AU1X00_IRQ_GPIO10             (MIPS_INTERRUPT_BASE + 50)
    491 #define AU1X00_IRQ_GPIO11             (MIPS_INTERRUPT_BASE + 51)
    492 #define AU1X00_IRQ_GPIO12             (MIPS_INTERRUPT_BASE + 52)
    493 #define AU1X00_IRQ_GPIO13             (MIPS_INTERRUPT_BASE + 53)
    494 #define AU1X00_IRQ_GPIO14             (MIPS_INTERRUPT_BASE + 54)
    495 #define AU1X00_IRQ_GPIO15             (MIPS_INTERRUPT_BASE + 55)
    496 #define AU1X00_IRQ_GPIO200            (MIPS_INTERRUPT_BASE + 56)
    497 #define AU1X00_IRQ_GPIO201            (MIPS_INTERRUPT_BASE + 57)
    498 #define AU1X00_IRQ_GPIO202            (MIPS_INTERRUPT_BASE + 58)
    499 #define AU1X00_IRQ_GPIO203            (MIPS_INTERRUPT_BASE + 59)
    500 #define AU1X00_IRQ_GPIO20             (MIPS_INTERRUPT_BASE + 60)
    501 #define AU1X00_IRQ_GPIO204            (MIPS_INTERRUPT_BASE + 61)
    502 #define AU1X00_IRQ_GPIO205            (MIPS_INTERRUPT_BASE + 62)
    503 #define AU1X00_IRQ_GPIO23             (MIPS_INTERRUPT_BASE + 63)
    504 #define AU1X00_IRQ_GPIO24             (MIPS_INTERRUPT_BASE + 64)
    505 #define AU1X00_IRQ_GPIO25             (MIPS_INTERRUPT_BASE + 65)
    506 #define AU1X00_IRQ_GPIO26             (MIPS_INTERRUPT_BASE + 66)
    507 #define AU1X00_IRQ_GPIO27             (MIPS_INTERRUPT_BASE + 67)
    508 #define AU1X00_IRQ_GPIO28             (MIPS_INTERRUPT_BASE + 68)
    509 #define AU1X00_IRQ_GPIO206            (MIPS_INTERRUPT_BASE + 69)
    510 #define AU1X00_IRQ_GPIO207            (MIPS_INTERRUPT_BASE + 70)
    511 #define AU1X00_IRQ_GPIO208_215        (MIPS_INTERRUPT_BASE + 71)
    512 
    513 #define AU1X00_MAXIMUM_VECTORS        (MIPS_INTERRUPT_BASE + 72)
    514 
    515433void static inline au_sync(void)
    516434{
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