Changeset 0c0181d in rtems


Ignore:
Timestamp:
Apr 4, 2012, 1:39:46 PM (8 years ago)
Author:
Jennifer Averett <jennifer.averett@…>
Branches:
4.11, master
Children:
a36d1b4
Parents:
eb6362dc
git-author:
Jennifer Averett <jennifer.averett@…> (04/04/12 13:39:46)
git-committer:
Joel Sherrill <joel.sherrill@…> (04/04/12 13:43:08)
Message:

PR 1993 - Convert MIPS to PIC IRQ model

Files:
19 added
5 deleted
54 edited
2 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/mips/ChangeLog

    reb6362dc r0c0181d  
     12012-03-07      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        * shared/irq/irq.c: Fixed unhandled interrupts to print
     4        the registers and shutdown. This prevents a loop of
     5        unusable information from occuring.
     6
     72012-03-06      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     8
     9        PR 1993/bsps
     10        * shared/clock/clockdrv.c, shared/irq/vectorexceptions.c,
     11        ../shared/clockdrv_shell.h: Changed interrupt call, removed warnings
     12        and did cleanup.
     13
     142012-02-23      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     15
     16        PR 1993/bsps
     17        * shared/irq/interruptmask.c,
     18        shared/irq/interruptmask_TX49.c,
     19        shared/irq/irq.c, shared/irq/maxvectors.c,
     20        shared/irq/vectorexceptions.c:
     21        Mips conversion to PIC IRQ model.
     22        * shared/irq/interruptmask.c,
     23        shared/irq/interruptmask_TX49.c,
     24        shared/irq/irq.c: New files.
     25
    1262011-02-02      Ralf Corsépius <ralf.corsepius@rtems.org>
    227
  • c/src/lib/libbsp/mips/csb350/ChangeLog

    reb6362dc r0c0181d  
     12012-03-08      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        * include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
     4
     52012-03-06      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     6
     7        PR 1993/bsps
     8        * clock/clockdrv.c, include/bsp.h, include/irq.h,
     9        irq/vectorisrs.c, startup/bspstart.c:
     10        Changed interrupt call, removed warnings and did cleanup.
     11
     122012-02-23      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     13
     14        PR 1993/bsps
     15        * Makefile.am, clock/clockdrv.c, include/irq.h,
     16        irq/vectorisrs.c,network/network.c,
     17        preinstall.am, startup/bspstart.c:
     18        Mips conversion to PIC IRQ model.
     19        * include/irq.h, irq/vectorisrs.c: New files.
     20
    1212011-12-14      Joel Sherrill <joel.sherrilL@OARcorp.com>
    222
  • c/src/lib/libbsp/mips/csb350/Makefile.am

    reb6362dc r0c0181d  
    1414include_HEADERS += include/tm27.h
    1515include_bsp_HEADERS = ../shared/liblnk/regs.h
     16#isr
     17include_bsp_HEADERS += ../../shared/include/irq-generic.h
     18include_bsp_HEADERS += ../../shared/include/irq-info.h
     19include_bsp_HEADERS += include/irq.h
    1620
    1721nodist_include_HEADERS = include/bspopts.h
     
    4246libbsp_a_SOURCES += ../../shared/bootcard.c
    4347libbsp_a_SOURCES += ../../shared/sbrk.c
    44 libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
    45 libbsp_a_SOURCES += ../../shared/setvec.c
    4648# clock
    4749libbsp_a_SOURCES += clock/clockdrv.c
     
    5254# timer
    5355libbsp_a_SOURCES += timer/timer.c
     56#isr
     57libbsp_a_SOURCES += ../../shared/src/irq-generic.c
     58libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
     59libbsp_a_SOURCES += ../../shared/src/irq-info.c
     60libbsp_a_SOURCES += ../../shared/src/irq-shell.c
     61libbsp_a_SOURCES += ../../shared/src/irq-server.c
     62libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
     63libbsp_a_SOURCES += ../shared/irq/irq.c
     64libbsp_a_SOURCES += ../shared/irq/maxvectors.c
     65libbsp_a_SOURCES += irq/vectorisrs.c
     66libbsp_a_SOURCES += ../shared/irq/interruptmask.c
    5467
    5568if HAS_NETWORKING
     
    6376libbsp_a_LIBADD  = ../../../libcpu/mips/shared/cache.rel
    6477libbsp_a_LIBADD += ../../../libcpu/mips/shared/interrupts.rel
    65 libbsp_a_LIBADD += ../../../libcpu/mips/au1x00/vectorisrs.rel
     78
    6679if HAS_NETWORKING
    6780libbsp_a_LIBADD += network.rel
  • c/src/lib/libbsp/mips/csb350/bsp_specs

    reb6362dc r0c0181d  
    55*startfile:
    66%{!qrtems: %(old_startfile)} \
    7 %{!nostdlib: %{qrtems: start.o%s crtbegin.o%s -e _start}}
     7%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}}
    88
    99*link:
  • c/src/lib/libbsp/mips/csb350/clock/clockdrv.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  Instantiate the clock driver shell.
    35 *
    46 *  This uses the TOY (Time of Year) timer to implement the clock.
    5  *
     7 */
     8
     9/*
    610 *  Copyright (c) 2005 by Cogent Computer Systems
    711 *  Written by Jay Monkman <jtm@lopingdog.com>
     
    1014 *  found in the file LICENSE in this distribution or at
    1115 *  http://www.rtems.com/license/LICENSE.
    12  *
     16 * 
    1317 *  $Id$
    1418 */
     
    1620#include <rtems.h>
    1721#include <bsp.h>
    18 #include <libcpu/au1x00.h>
     22#include <bsp/irq.h>
    1923#include <rtems/bspIo.h>
    2024
    2125uint32_t tick_interval;
    2226uint32_t last_match;
     27
     28void au1x00_clock_init(void);
    2329
    2430#define CLOCK_VECTOR AU1X00_IRQ_TOY_MATCH2
     
    3541#define Clock_driver_support_install_isr( _new, _old )  \
    3642  do {                                                  \
    37         _old = set_vector( _new, AU1X00_IRQ_TOY_MATCH2, 1 );     \
    38         AU1X00_IC_MASKCLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
    39         AU1X00_IC_SRCSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
    40         AU1X00_IC_CFG0SET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
    41         AU1X00_IC_CFG1CLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
    42         AU1X00_IC_CFG2CLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
    43         AU1X00_IC_ASSIGNSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
     43    rtems_interrupt_handler_install( \
     44      CLOCK_VECTOR, \
     45      "clock", \
     46      0, \
     47      _new, \
     48      NULL \
     49    ); \
     50    AU1X00_IC_MASKCLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
     51    AU1X00_IC_SRCSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
     52    AU1X00_IC_CFG0SET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
     53    AU1X00_IC_CFG1CLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
     54    AU1X00_IC_CFG2CLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
     55    AU1X00_IC_ASSIGNSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
    4456  } while(0)
    4557
  • c/src/lib/libbsp/mips/csb350/include/bsp.h

    reb6362dc r0c0181d  
    1 /*  bsp.h
    2  *
     1/**
     2 *  @file
     3 * 
    34 *  This include file contains some definitions specific to the
    45 *  Cogent CSB350 Board.
    5  *
    6  *  COPYRIGHT (c) 1989-2000.
     6 */
     7
     8/*
     9 *  COPYRIGHT (c) 1989-2012.
    710 *  On-Line Applications Research Corporation (OAR).
    811 *
     
    2932#include <libcpu/au1x00.h>
    3033
     34#define BSP_FEATURE_IRQ_EXTENSION
     35#define BSP_SHARED_HANDLER_SUPPORT      1
    3136
    3237/*
  • c/src/lib/libbsp/mips/csb350/network/network.c

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 *  Au1x00 ethernet driver
     5 */
     6
    17/*
    2  *  Au1x00 ethernet driver
    3  *
    48 *  Copyright (c) 2005 by Cogent Computer Systems
    59 *  Written by Jay Monkman <jtm@lopingdog.com>
     
    812 *  found in the file LICENSE in this distribution or at
    913 *  http://www.rtems.com/license/LICENSE.
    10  *
     14 * 
    1115 *  $Id$
    1216 */
     
    1721#include <rtems/bspIo.h>
    1822#include <libcpu/au1x00.h>
     23#include <bsp/irq.h>
    1924
    2025#include <stdio.h>
  • c/src/lib/libbsp/mips/csb350/preinstall.am

    reb6362dc r0c0181d  
    5050PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
    5151
     52$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     53        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     54PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     55
     56$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     57        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
     58PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
     59
     60$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     61        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
     62PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
     63
    5264$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
    5365        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
  • c/src/lib/libbsp/mips/csb350/startup/bspstart.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  This routine starts the application.  It includes application,
    35 *  board, and monitor specific initialization and configuration.
    46 *  The generic CPU dependent initialization has been performed
    57 *  before this routine is invoked.
    6  *
    7  *  COPYRIGHT (c) 1989-2000.
     8 */
     9
     10/*
     11 *  COPYRIGHT (c) 1989-2012.
    812 *  On-Line Applications Research Corporation (OAR).
    913 *
     
    1115 *  found in the file LICENSE in this distribution or at
    1216 *  http://www.rtems.com/license/LICENSE.
    13  *
     17 * 
    1418 *  $Id$
    1519 */
     
    2024#include <libcpu/au1x00.h>
    2125#include <libcpu/isr_entries.h>
     26#include <bsp/irq-generic.h>
     27
     28void bsp_start( void );
    2229
    2330au1x00_uart_t *uart0 = (au1x00_uart_t *)AU1X00_UART0_ADDR;
     
    3643                          /* depend on the IRC to take care of things */
    3744  __asm__ volatile ("mtc0 %0, $11\n" :: "r" (compare));
    38   mips_install_isr_entries();
     45  bsp_interrupt_initialize();
    3946}
    40 
    41 
    42 /* These replace the ones in newlib. I'm not sure why the newlib ones
    43  * don't work.
    44  */
    45 void _init(void)
    46 {
    47 }
    48 
    49 void _fini(void)
    50 {
    51 }
  • c/src/lib/libbsp/mips/genmongoosev/ChangeLog

    reb6362dc r0c0181d  
     12012-03-08      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        * include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
     4
     52012-03-06      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     6
     7        PR 1993/bsps
     8        * clock/clockdrv.c, include/bsp.h,
     9        include/irq.h, irq/vectorisrs.c,
     10        startup/bspstart.c, clock/ckinit.c:
     11        Changed interrupt call, removed warnings and did cleanup.
     12
     132012-02-23      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     14
     15        PR 1993/bsps
     16        * Makefile.am, clock/clockdrv.c, console/conscfg.c,
     17        include/irq.h, irq/vectorisrs.c, preinstall.am,
     18        startup/bspstart.c:
     19        Mips conversion to PIC IRQ model.
     20        * include/irq.h, irq/vectorisrs.c: New files.
     21
    1222011-10-18      Jennifer Averett <Jennifer.Averett@OARcorp.com>
    223
  • c/src/lib/libbsp/mips/genmongoosev/Makefile.am

    reb6362dc r0c0181d  
    1414include_HEADERS += include/tm27.h
    1515include_bsp_HEADERS = start/regs.h
     16#isr
     17include_bsp_HEADERS += ../../shared/include/irq-generic.h
     18include_bsp_HEADERS += ../../shared/include/irq-info.h
     19include_bsp_HEADERS += include/irq.h
    1620
    1721nodist_include_HEADERS = include/bspopts.h
     
    2327
    2428noinst_LIBRARIES = libbspstart.a
    25 libbspstart_a_SOURCES = start/start.S start/regs.h start/mg5.h
     29libbspstart_a_SOURCES  = start/start.S
     30libbspstart_a_SOURCES += start/regs.h
     31libbspstart_a_SOURCES += start/mg5.h
    2632project_lib_DATA = start.$(OBJEXT)
    2733
     
    3238
    3339# startup
    34 libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsppretaskinghook.c \
    35     ../../shared/bsppredriverhook.c ../../shared/bsplibc.c \
    36     ../../shared/bsppost.c startup/bspstart.c ../../shared/bootcard.c \
    37     ../../shared/sbrk.c ../../shared/gnatinstallhandler.c \
    38     ../../shared/setvec.c ../../shared/bspgetworkarea.c
     40libbsp_a_SOURCES += ../../shared/bspclean.c
     41libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
     42libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
     43libbsp_a_SOURCES += ../../shared/bsplibc.c
     44libbsp_a_SOURCES += ../../shared/bsppost.c
     45libbsp_a_SOURCES += startup/bspstart.c
     46libbsp_a_SOURCES += ../../shared/bootcard.c
     47libbsp_a_SOURCES += ../../shared/sbrk.c
     48libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
    3949# clock
    4050libbsp_a_SOURCES += clock/clockdrv.c
    4151libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
    4252# console
    43 libbsp_a_SOURCES += console/conscfg.c ../../shared/console.c \
    44     ../../shared/console_select.c ../../shared/console_control.c \
    45     ../../shared/console_read.c ../../shared/console_write.c
     53libbsp_a_SOURCES += console/conscfg.c
     54libbsp_a_SOURCES += ../../shared/console.c
     55libbsp_a_SOURCES += ../../shared/console_select.c
     56libbsp_a_SOURCES += ../../shared/console_control.c
     57libbsp_a_SOURCES += ../../shared/console_read.c
     58libbsp_a_SOURCES += ../../shared/console_write.c
    4659# timer
    4760libbsp_a_SOURCES += timer/timer.c
     61#isr
     62libbsp_a_SOURCES += ../../shared/src/irq-generic.c
     63libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
     64libbsp_a_SOURCES += ../../shared/src/irq-info.c
     65libbsp_a_SOURCES += ../../shared/src/irq-shell.c
     66libbsp_a_SOURCES += ../../shared/src/irq-server.c
     67libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
     68libbsp_a_SOURCES += ../shared/irq/irq.c
     69libbsp_a_SOURCES += ../shared/irq/maxvectors.c
     70libbsp_a_SOURCES += irq/vectorisrs.c
     71libbsp_a_SOURCES += ../shared/irq/interruptmask.c
    4872
    4973gdbstub_CPPFLAGS = -I$(srcdir)/../../mips/shared/gdbstub
    5074noinst_PROGRAMS += gdbstub.rel
    51 gdbstub_rel_SOURCES = ../../mips/shared/gdbstub/mips-stub.c \
    52     startup/gdb-support.c ../../shared/gdbstub/rtems-stub-glue.c
     75gdbstub_rel_SOURCES  = ../../mips/shared/gdbstub/mips-stub.c
     76gdbstub_rel_SOURCES += startup/gdb-support.c
     77gdbstub_rel_SOURCES += ../../shared/gdbstub/rtems-stub-glue.c
    5378gdbstub_rel_CPPFLAGS = $(AM_CPPFLAGS) $(gdbstub_CPPFLAGS)
    5479gdbstub_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    5580
    56 libbsp_a_LIBADD = \
    57     ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    58     ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel \
    59     ../../../libcpu/@RTEMS_CPU@/mongoosev/duart.rel \
    60     ../../../libcpu/@RTEMS_CPU@/mongoosev/vectorisrs.rel
     81libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
     82libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
     83libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mongoosev/duart.rel
    6184
    6285include $(srcdir)/preinstall.am
  • c/src/lib/libbsp/mips/genmongoosev/clock/clockdrv.c

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 *  Instantiate the clock driver shell for the Mongoose-V's on-CPU timer.
     5 */
     6
    17/*
    2  *  Instantiate the clock driver shell for the Mongoose-V's on-CPU timer.
    3  *
    4  *  COPYRIGHT (c) 1989-2001.
     8 *  COPYRIGHT (c) 1989-2012.
    59 *  On-Line Applications Research Corporation (OAR).
    610 *
     
    812 *  found in the file LICENSE in this distribution or at
    913 *  http://www.rtems.com/license/LICENSE.
    10  *
     14 * 
    1115 *  $Id$
    1216 */
    1317
    1418#include <rtems.h>
    15 #include <libcpu/mongoose-v.h>
     19#include <bsp/irq.h>
    1620#include <bsp.h>
    1721
     
    3438#define Clock_driver_support_install_isr( _new, _old ) \
    3539  do { \
    36     _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
     40    rtems_interrupt_handler_install( \
     41      CLOCK_VECTOR, \
     42      "clock", \
     43      0, \
     44      _new, \
     45      NULL \
     46    ); \
    3747  } while(0)
    3848
  • c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  This file contains the libchip configuration information
    35 *  to instantiate the libchip driver for the on-CPU DUART
    46 *  and any other serial ports in the system.
    5  *
    6  *  COPYRIGHT (c) 1989-2001.
     7 */
     8
     9/*
     10 *  COPYRIGHT (c) 1989-2012.
    711 *  On-Line Applications Research Corporation (OAR).
    812 *
     
    1014 *  found in the file LICENSE in this distribution or at
    1115 *  http://www.rtems.com/license/LICENSE.
    12  *
     16 * 
    1317 *  $Id$
    1418 */
     
    1721
    1822#include <bsp.h>
     23#include <bsp/irq.h>
    1924
    2025#include <libchip/serial.h>
  • c/src/lib/libbsp/mips/genmongoosev/include/bsp.h

    reb6362dc r0c0181d  
    1 /*  bsp.h
    2  *
     1/**
     2 *  @file
     3 * 
    34 *  This include file contains some definitions specific to a board
    45 *  based upon the generic capabilities of a Mongoose-V.
    5  *
    6  *  COPYRIGHT (c) 1989-2001.
     6 */
     7
     8/*
     9 *  COPYRIGHT (c) 1989-2012.
    710 *  On-Line Applications Research Corporation (OAR).
    811 *
     
    2831#include <rtems/clockdrv.h>
    2932#include <libcpu/mongoose-v.h>
     33
     34#define BSP_FEATURE_IRQ_EXTENSION
     35#define BSP_SHARED_HANDLER_SUPPORT      1
    3036
    3137#ifndef CPU_CLOCK_RATE
  • c/src/lib/libbsp/mips/genmongoosev/preinstall.am

    reb6362dc r0c0181d  
    5050PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
    5151
     52$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     53        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     54PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     55
     56$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     57        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
     58PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
     59
     60$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     61        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
     62PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
     63
    5264$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
    5365        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
  • c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  This routine starts the application.  It includes application,
    35 *  board, and monitor specific initialization and configuration.
     
    57 *  before this routine is invoked.
    68 *
    7  *  COPYRIGHT (c) 1989-2001.
     9 *  Modification History:
     10 *        12/10/01  A.Ferrer, NASA/GSFC, Code 582
     11 *           Set interrupt mask to 0xAF00 (Line 139).
     12 */
     13
     14/*
     15 *  COPYRIGHT (c) 1989-2012.
    816 *  On-Line Applications Research Corporation (OAR).
    917 *
     
    1119 *  found in the file LICENSE in this distribution or at
    1220 *  http://www.rtems.com/license/LICENSE.
    13  *
     21 * 
    1422 *  $Id$
    15  *
    16  * Modification History:
    17  *        12/10/01  A.Ferrer, NASA/GSFC, Code 582
    18  *           Set interrupt mask to 0xAF00 (Line 139).
    1923 */
    20 
     24 
    2125#include <string.h>
    2226
     
    2428#include <libcpu/mongoose-v.h>
    2529#include <libcpu/isr_entries.h>
     30#include <bsp/irq-generic.h>
    2631
     32void bsp_start( void );
     33void clear_cache( void );
    2734extern void _sys_exit(int);
    2835extern void mips_gdb_stub_install(void);
     
    8390  mips_set_sr( (SR_CU0 | 0x400) );
    8491
    85   mips_install_isr_entries();
     92  bsp_interrupt_initialize();
    8693}
    8794
  • c/src/lib/libbsp/mips/hurricane/ChangeLog

    reb6362dc r0c0181d  
     12012-03-08      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        * include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
     4
     52012-03-06      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     6
     7        PR 1993/bsps
     8        * include/bsp.h, include/irq.h,
     9        irq/vectorisrs.c, startup/bspstart.c:
     10        Changed interrupt call, removed warnings and did cleanup.
     11
     122012-02-23      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     13
     14        PR 1993/bsps
     15        * Makefile.am, clock/ckinit.c, include/irq.h,
     16        irq/vectorisrs.c, preinstall.am, startup/bspstart.c:
     17        Mips conversion to PIC IRQ model.
     18        * include/irq.h, irq/vectorisrs.c: New files.
     19
    1202011-02-02      Ralf Corsépius <ralf.corsepius@rtems.org>
    221
  • c/src/lib/libbsp/mips/hurricane/Makefile.am

    reb6362dc r0c0181d  
    1515include_HEADERS += include/usc.h
    1616include_bsp_HEADERS = ../shared/liblnk/regs.h
     17#isr
     18include_bsp_HEADERS += ../../shared/include/irq-generic.h
     19include_bsp_HEADERS += ../../shared/include/irq-info.h
     20include_bsp_HEADERS += include/irq.h
    1721
    1822nodist_include_HEADERS = include/bspopts.h
     
    3236
    3337# startup
    34 libbsp_a_SOURCES += ../../shared/bspclean.c \
    35     ../../shared/bsplibc.c ../../shared/bsppost.c \
    36    ../../shared/bsppretaskinghook.c ../../shared/bspgetworkarea.c \
    37     ../../shared/bsppredriverhook.c startup/bspstart.c \
    38     ../../shared/bootcard.c ../../shared/sbrk.c \
    39     ../../shared/gnatinstallhandler.c ../../shared/setvec.c \
    40     startup/inittlb.c ../shared/startup/idtmem.S ../shared/startup/idttlb.S \
    41     ../shared/irq/exception.S startup/usc.S
     38libbsp_a_SOURCES += ../../shared/bspclean.c
     39libbsp_a_SOURCES += ../../shared/bsplibc.c
     40libbsp_a_SOURCES += ../../shared/bsppost.c
     41libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
     42libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
     43libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
     44libbsp_a_SOURCES += startup/bspstart.c
     45libbsp_a_SOURCES += ../../shared/bootcard.c
     46libbsp_a_SOURCES += ../../shared/sbrk.c
     47libbsp_a_SOURCES += startup/inittlb.c
     48libbsp_a_SOURCES += ../shared/startup/idtmem.S
     49libbsp_a_SOURCES += ../shared/startup/idttlb.S
     50libbsp_a_SOURCES += ../shared/irq/exception.S
     51libbsp_a_SOURCES += startup/usc.S
    4252# clock
    4353libbsp_a_SOURCES += clock/ckinit.c
     54libbsp_a_SOURCES += clock/clock.h
     55
    4456# console
    4557libbsp_a_SOURCES += console/console.c
    4658# liblnk
    47 libbsp_a_SOURCES += ../shared/liblnk/lnklib.S ../shared/liblnk/pmon.S \
    48     ../shared/liblnk/regs.h
     59libbsp_a_SOURCES += ../shared/liblnk/lnklib.S
     60libbsp_a_SOURCES += ../shared/liblnk/pmon.S
     61libbsp_a_SOURCES += ../shared/liblnk/regs.h
     62#isr
     63libbsp_a_SOURCES += ../../shared/src/irq-generic.c
     64libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
     65libbsp_a_SOURCES += ../../shared/src/irq-info.c
     66libbsp_a_SOURCES += ../../shared/src/irq-shell.c
     67libbsp_a_SOURCES += ../../shared/src/irq-server.c
     68libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
     69libbsp_a_SOURCES += ../shared/irq/irq.c
     70libbsp_a_SOURCES += ../shared/irq/maxvectors.c
     71libbsp_a_SOURCES += irq/vectorisrs.c
     72libbsp_a_SOURCES += ../shared/irq/interruptmask.c
    4973
    50 libbsp_a_LIBADD = \
    51     ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    52     ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel \
    53     ../../../libcpu/@RTEMS_CPU@/rm52xx/timer.rel \
    54     ../../../libcpu/@RTEMS_CPU@/rm52xx/vectorisrs.rel
     74libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
     75libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
     76libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rm52xx/timer.rel
    5577
    5678include $(srcdir)/preinstall.am
  • c/src/lib/libbsp/mips/hurricane/clock/ckinit.c

    reb6362dc r0c0181d  
    1 
    2 /*  ckinit.c
    3  *
     1/**
     2 *  @file
     3 * 
    44 *  This file contains the clock driver initialization for the Hurricane BSP.
    5  *
     5 */
     6
     7/*
    68 *  Author:     Craig Lebakken <craigl@transition.com>
    79 *
     
    1921 *      of this software for any purpose.
    2022 *
    21  *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c:
    22  *
    23  *  COPYRIGHT (c) 1989-1999.
     23 *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c
     24 *
     25 *  COPYRIGHT (c) 1989-2012.
    2426 *  On-Line Applications Research Corporation (OAR).
    2527 *
     
    2729 *  found in the file LICENSE in this distribution or at
    2830 *  http://www.rtems.com/license/LICENSE.
    29  *
     31 * 
    3032 *  $Id$
    3133 */
     
    4244
    4345#include <rtems.h>
     46#include <bsp.h>
     47#include <bsp/irq.h>
    4448
    4549extern uint32_t bsp_clicks_per_microsecond;
     
    4953#include "clock.h"
    5054
    51 /* to avoid including the bsp */
    52 mips_isr_entry set_vector( rtems_isr_entry, rtems_vector_number, int );
    53 
    54 void USC_isr( void );
     55rtems_isr USC_isr(void *unused);
     56
    5557void reset_wdt(void);
    5658void enable_wdi(void);
     
    5961void disable_hbi(void);
    6062
    61 void Clock_exit( void );
    62 rtems_isr Clock_isr( rtems_vector_number vector );
     63void Clock_exit(void);
     64rtems_isr Clock_isr(rtems_vector_number vector);
     65rtems_isr User_Clock_isr(rtems_vector_number vector);
     66void Install_clock(rtems_isr_entry clock_isr);
    6367
    6468
     
    8993
    9094/*
    91  * These are set by clock driver during its init
    92  */
    93 
    94 rtems_device_major_number rtems_clock_major = ~0;
    95 rtems_device_minor_number rtems_clock_minor;
    96 
    97 /*
    9895 *  The previous ISR on this clock tick interrupt vector.
    9996 */
     
    168165  disable_hbi();      /* Disable heartbeat interrupt in USC */
    169166
    170               /* Install interrupt handler */
    171   Old_ticker = (rtems_isr_entry) set_vector( USC_isr, CLOCK_VECTOR, 1 );
     167  /* Install interrupt handler */
     168  rtems_interrupt_handler_install(
     169    CLOCK_VECTOR,
     170    "clock",
     171    0,
     172    USC_isr,
     173    NULL
     174  );
    172175
    173176  init_hbt();        /* Initialize heartbeat timer */
     
    213216  Install_clock( Clock_isr );
    214217
    215   /*
    216    * make major/minor avail to others such as shared memory driver
    217    */
    218 
    219   rtems_clock_major = major;
    220   rtems_clock_minor = minor;
    221 
    222218  return RTEMS_SUCCESSFUL;
    223219}
  • c/src/lib/libbsp/mips/hurricane/include/bsp.h

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 */
     5
    16/*
    2  *  COPYRIGHT (c) 1989-2008.
     7 *  COPYRIGHT (c) 1989-2012.
    38 *  On-Line Applications Research Corporation (OAR).
    49 *
     
    2833
    2934extern uint32_t mips_get_timer( void );
     35
     36#define BSP_FEATURE_IRQ_EXTENSION
     37#define BSP_SHARED_HANDLER_SUPPORT      1
    3038
    3139#define CPU_CLOCK_RATE_MHZ     (200)
  • c/src/lib/libbsp/mips/hurricane/preinstall.am

    reb6362dc r0c0181d  
    5454PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
    5555
     56$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     57        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     58PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     59
     60$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     61        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
     62PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
     63
     64$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     65        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
     66PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
     67
    5668$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
    5769        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
  • c/src/lib/libbsp/mips/hurricane/startup/bspstart.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  This routine starts the application.  It includes application,
    35 *  board, and monitor specific initialization and configuration.
    46 *  The generic CPU dependent initialization has been performed
    57 *  before this routine is invoked.
    6  *
    7  *  COPYRIGHT (c) 1989-1999.
     8 */
     9
     10/*
     11 *  COPYRIGHT (c) 1989-2012.
    812 *  On-Line Applications Research Corporation (OAR).
    913 *
     
    1115 *  found in the file LICENSE in this distribution or at
    1216 *  http://www.rtems.com/license/LICENSE.
    13  *
     17 * 
    1418 *  $Id$
    1519 */
     
    1923#include <bsp.h>
    2024#include <libcpu/isr_entries.h>
     25#include <bsp/irq-generic.h>
    2126
     27void bsp_start( void );
    2228uint32_t bsp_clicks_per_microsecond;
    2329
     
    3238  bsp_clicks_per_microsecond = CPU_CLOCK_RATE_MHZ;
    3339
    34   mips_install_isr_entries(); /* Install generic MIPS exception handler */
     40  bsp_interrupt_initialize();
    3541}
  • c/src/lib/libbsp/mips/jmr3904/ChangeLog

    reb6362dc r0c0181d  
     12012-03-08      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        * include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
     4
     52012-03-06      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     6
     7        PR 1993/bsps
     8        * clock/clockdrv.c, include/bsp.h,
     9        include/irq.h, irq/vectorisrs.c, startup/bspstart.c:
     10        Changed interrupt call, removed warnings and did cleanup.
     11
     122012-02-23      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     13
     14        PR 1993/bsps
     15        * Makefile.am, clock/clockdrv.c, include/irq.h,
     16        irq/vectorisrs.c, preinstall.am, startup/bspstart.c:
     17        Mips conversion to PIC IRQ model.
     18        * include/irq.h, irq/vectorisrs.c: New files.
     19
    1202011-12-14      Joel Sherrill <joel.sherrilL@OARcorp.com>
    221
  • c/src/lib/libbsp/mips/jmr3904/Makefile.am

    reb6362dc r0c0181d  
    1414include_HEADERS += include/tm27.h
    1515include_bsp_HEADERS = ../shared/liblnk/regs.h
     16#isr
     17include_bsp_HEADERS += ../../shared/include/irq-generic.h
     18include_bsp_HEADERS += ../../shared/include/irq-info.h
     19include_bsp_HEADERS += include/irq.h
    1620
    1721nodist_include_HEADERS = include/bspopts.h
     
    4044libbsp_a_SOURCES += ../../shared/bootcard.c
    4145libbsp_a_SOURCES += ../../shared/sbrk.c
    42 libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
    43 libbsp_a_SOURCES += ../../shared/setvec.c
    4446libbsp_a_SOURCES += ../../shared/bspreset.c
    4547# clock
     
    5153# timer
    5254libbsp_a_SOURCES += timer/timer.c
     55#isr
     56libbsp_a_SOURCES += ../../shared/src/irq-generic.c
     57libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
     58libbsp_a_SOURCES += ../../shared/src/irq-info.c
     59libbsp_a_SOURCES += ../../shared/src/irq-shell.c
     60libbsp_a_SOURCES += ../../shared/src/irq-server.c
     61libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
     62libbsp_a_SOURCES += ../shared/irq/irq.c
     63libbsp_a_SOURCES += ../shared/irq/maxvectors.c
     64libbsp_a_SOURCES += irq/vectorisrs.c
     65libbsp_a_SOURCES += ../shared/irq/interruptmask.c
    5366
    5467libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
    5568libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
    56 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx39/vectorisrs.rel
    57 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
    5869
    5970include $(srcdir)/preinstall.am
  • c/src/lib/libbsp/mips/jmr3904/clock/clockdrv.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  Instantiate the clock driver shell.
    35 *
    46 *  The TX3904 simulator in gdb counts instructions.
    5  *
    6  *  COPYRIGHT (c) 1989-2009.
     7 */
     8
     9/*
     10 *  COPYRIGHT (c) 1989-2012.
    711 *  On-Line Applications Research Corporation (OAR).
    812 *
     
    1014 *  found in the file LICENSE in this distribution or at
    1115 *  http://www.rtems.com/license/LICENSE.
    12  *
     16 * 
    1317 *  $Id$
    1418 */
    1519
    1620#include <rtems.h>
    17 #include <libcpu/tx3904.h>
     21#include <bsp/irq.h>
    1822#include <bsp.h>
    1923
     
    2731
    2832#define CLICKS 5000
     33
    2934#define Clock_driver_support_install_isr( _new, _old ) \
    3035  do { \
    31     _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
    32   } while(0)
     36    rtems_interrupt_handler_install( \
     37      CLOCK_VECTOR, \
     38      "clock", \
     39      0, \
     40      _new, \
     41      NULL \
     42    ); \
     43 } while(0)
    3344
    3445#define Clock_driver_support_initialize_hardware() \
  • c/src/lib/libbsp/mips/jmr3904/include/bsp.h

    reb6362dc r0c0181d  
    1 /*  bsp.h
    2  *
     1/**
     2 *  @file
     3 * 
    34 *  This include file contains some definitions specific to the
    45 *  JMR3904 simulator in gdb.
    5  *
    6  *  COPYRIGHT (c) 1989-2000.
     6 */
     7
     8/*
     9 *  COPYRIGHT (c) 1989-2012.
    710 *  On-Line Applications Research Corporation (OAR).
    811 *
     
    2932#include <libcpu/tx3904.h>
    3033
     34#define BSP_FEATURE_IRQ_EXTENSION
     35#define BSP_SHARED_HANDLER_SUPPORT      1
     36
    3137/* functions */
    3238
  • c/src/lib/libbsp/mips/jmr3904/preinstall.am

    reb6362dc r0c0181d  
    5050PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
    5151
     52$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     53        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     54PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     55
     56$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     57        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
     58PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
     59
     60$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     61        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
     62PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
     63
    5264$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
    5365        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
  • c/src/lib/libbsp/mips/jmr3904/startup/bspstart.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  This routine starts the application.  It includes application,
    35 *  board, and monitor specific initialization and configuration.
    46 *  The generic CPU dependent initialization has been performed
    57 *  before this routine is invoked.
    6  *
    7  *  COPYRIGHT (c) 1989-2009.
     8 */
     9
     10/*
     11 *  COPYRIGHT (c) 1989-2012.
    812 *  On-Line Applications Research Corporation (OAR).
    913 *
     
    1115 *  found in the file LICENSE in this distribution or at
    1216 *  http://www.rtems.com/license/LICENSE.
    13  *
     17 * 
    1418 *  $Id$
    1519 */
     
    1822#include <libcpu/isr_entries.h>
    1923#include <bsp/bootcard.h>
    20 
    21 /*
    22  *  bsp_start
    23  *
    24  *  This routine does the bulk of the system initialization.
    25  */
    26 void bsp_start( void )
    27 {
    28   mips_set_sr( 0xff00 );  /* all interrupts unmasked but globally off */
    29                           /* depend on the IRC to take care of things */
    30   mips_install_isr_entries();
    31 }
    32 
    33 /*
    34  *  Required routine by some gcc run-times.
    35  */
    36 void clear_cache( void *address, size_t n )
    37 {
    38 }
     24#include <bsp/irq-generic.h>
     25#include <bsp/irq.h>
     26#include <bsp/irq-generic.h>
    3927
    4028/* Structure filled in by get_mem_info.  Only the size field is
     
    4836};
    4937
     38void bsp_start( void );
     39void clear_cache( void *address, size_t n );
     40void get_mem_info( struct s_mem *mem );
     41
     42/*
     43 *  bsp_start
     44 *
     45 *  This routine does the bulk of the system initialization.
     46 */
     47void bsp_start( void )
     48{
     49  mips_set_sr( 0xff00 );  /* all interrupts unmasked but globally off */
     50                          /* depend on the IRC to take care of things */
     51  bsp_interrupt_initialize();
     52}
     53
     54/*
     55 *  Required routine by some gcc run-times.
     56 */
     57void clear_cache( void *address, size_t n )
     58{
     59}
     60
     61
    5062void get_mem_info(
    5163  struct s_mem *mem
  • c/src/lib/libbsp/mips/rbtx4925/ChangeLog

    reb6362dc r0c0181d  
     12012-03-08      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        * include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
     4
     52012-03-06      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     6
     7        PR 1993/bsps
     8        * clock/clockdrv.c, include/bsp.h,
     9        include/irq.h, irq/vectorisrs.c, startup/bspstart.c:
     10        Changed interrupt call, removed warnings and did cleanup.
     11
     122012-02-23      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     13
     14        PR 1993/bsps
     15        * Makefile.am, clock/clockdrv.c, include/irq.h,
     16        irq/vectorisrs.c, preinstall.am, startup/bspstart.c:
     17        Mips conversion to PIC IRQ model.
     18        * include/irq.h, irq/vectorisrs.c: New files.
     19
    1202011-12-14      Joel Sherrill <joel.sherrilL@OARcorp.com>
    221
  • c/src/lib/libbsp/mips/rbtx4925/Makefile.am

    reb6362dc r0c0181d  
    1414include_HEADERS += ../../shared/include/tm27.h
    1515include_bsp_HEADERS = ../shared/liblnk/regs.h
     16#isr
     17include_bsp_HEADERS += ../../shared/include/irq-generic.h
     18include_bsp_HEADERS += ../../shared/include/irq-info.h
     19include_bsp_HEADERS += include/irq.h
    1620
    1721nodist_include_HEADERS = include/bspopts.h
     
    4246libbsp_a_SOURCES += ../../shared/bootcard.c
    4347libbsp_a_SOURCES += ../../shared/sbrk.c
    44 libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
    45 libbsp_a_SOURCES += ../../shared/setvec.c
    4648libbsp_a_SOURCES += startup/inittlb.c
    4749libbsp_a_SOURCES += ../shared/startup/idttlb.S
     
    5759libbsp_a_SOURCES += ../shared/liblnk/pmon.S
    5860libbsp_a_SOURCES += ../shared/liblnk/regs.h
     61#isr
     62libbsp_a_SOURCES += ../../shared/src/irq-generic.c
     63libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
     64libbsp_a_SOURCES += ../../shared/src/irq-info.c
     65libbsp_a_SOURCES += ../../shared/src/irq-shell.c
     66libbsp_a_SOURCES += ../../shared/src/irq-server.c
     67libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
     68libbsp_a_SOURCES += ../shared/irq/irq.c
     69libbsp_a_SOURCES += ../shared/irq/maxvectors.c
     70libbsp_a_SOURCES += irq/vectorisrs.c
     71libbsp_a_SOURCES += ../shared/irq/interruptmask_TX49.c
    5972
    6073libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
    6174libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
    6275libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/timer.rel
    63 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/vectorisrs.rel
    6476
    6577include $(srcdir)/preinstall.am
  • c/src/lib/libbsp/mips/rbtx4925/clock/clockdrv.c

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 *  Instantiate the clock driver shell.
     5 */
     6
    17/*
    2  *  Instantiate the clock driver shell.
     8 *  COPYRIGHT (c) 1989-2012.
     9 *  On-Line Applications Research Corporation (OAR).
    310 *
    4  *  clockdrv.c,v 1.5 2001/01/09 17:05:57 joel Exp
     11 *  The license and distribution terms for this file may be
     12 *  found in the file LICENSE in this distribution or at
     13 *  http://www.rtems.com/license/LICENSE.
     14 *
     15 *  $Id$
    516 */
    617
    718#include <rtems.h>
    8 #include <libcpu/tx4925.h>
     19#include <bsp/irq.h>
    920#include <bsp.h>
    1021
     
    3243#define Clock_driver_support_install_isr( _new, _old ) \
    3344  do { \
    34     _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
    35   } while(0)
     45    rtems_interrupt_handler_install( \
     46      CLOCK_VECTOR, \
     47      "clock", \
     48      0, \
     49      _new, \
     50      NULL \
     51    ); \
     52 } while(0)
    3653
    3754
  • c/src/lib/libbsp/mips/rbtx4925/include/bsp.h

    reb6362dc r0c0181d  
    1 /*  bsp.h
    2  *
     1/**
     2 *  @file
     3 * 
    34 *  This include file contains some definitions specific to the RBTX4925.
    4  *
    5  *  COPYRIGHT (c) 1989-2000.
     5 */
     6
     7/*
     8 *  COPYRIGHT (c) 1989-2012.
    69 *  On-Line Applications Research Corporation (OAR).
    710 *
     
    1013 *  http://www.rtems.com/license/LICENSE.
    1114 *
    12  *  bsp.h,v 1.7.6.1 2003/09/04 18:44:49 joel Exp
     15 *  $Id$
    1316 */
    1417
     
    2831#include <libcpu/tx4925.h>
    2932
     33#define BSP_FEATURE_IRQ_EXTENSION
     34#define BSP_SHARED_HANDLER_SUPPORT      1
     35
    3036/* functions */
    3137
  • c/src/lib/libbsp/mips/rbtx4925/preinstall.am

    reb6362dc r0c0181d  
    5050PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
    5151
     52$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     53        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     54PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     55
     56$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     57        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
     58PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
     59
     60$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     61        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
     62PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
     63
    5264$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
    5365        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
  • c/src/lib/libbsp/mips/rbtx4925/startup/bspstart.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  This routine starts the application.  It includes application,
    35 *  board, and monitor specific initialization and configuration.
    46 *  The generic CPU dependent initialization has been performed
    57 *  before this routine is invoked.
    6  *
    7  *  COPYRIGHT (c) 1989-2000.
     8 */
     9
     10/*
     11 *  COPYRIGHT (c) 1989-2012.
    812 *  On-Line Applications Research Corporation (OAR).
    913 *
     
    1115 *  found in the file LICENSE in this distribution or at
    1216 *  http://www.rtems.com/license/LICENSE.
    13  *
    14  *  bspstart.c,v 1.4.2.1 2003/09/04 18:44:49 joel Exp
     17 * 
     18 *  $Id$
    1519 */
    1620
    1721#include <bsp.h>
    1822#include <libcpu/isr_entries.h>
     23#include <bsp/irq-generic.h>
     24
     25void bsp_start( void );
    1926
    2027/*
     
    2532void bsp_start( void )
    2633{
    27   mips_install_isr_entries();  /* Install generic MIPS exception handler */
     34  bsp_interrupt_initialize();
    2835}
    2936
  • c/src/lib/libbsp/mips/rbtx4938/ChangeLog

    reb6362dc r0c0181d  
     12012-03-08      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        * include/bsp.h: Added define for BSP_SHARED_HANDLER_SUPPORT.
     4
     52012-03-06      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     6
     7        PR 1993/bsps
     8        * clock/clockdrv.c, include/bsp.h, include/irq.h,
     9        irq/vectorisrs.c, startup/bspstart.c:
     10        Changed interrupt call, removed warnings and did cleanup.
     11
     122012-02-23      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     13
     14        PR 1993/bsps
     15        * Makefile.am, clock/clockdrv.c, include/irq.h,
     16        irq/vectorisrs.c, preinstall.am, startup/bspstart.c,
     17        Mips conversion to PIC IRQ model.
     18        * include/irq.h, irq/vectorisrs.c: New files.
     19
    1202011-12-14      Joel Sherrill <joel.sherrilL@OARcorp.com>
    221
  • c/src/lib/libbsp/mips/rbtx4938/Makefile.am

    reb6362dc r0c0181d  
    1414include_HEADERS += ../../shared/include/tm27.h
    1515include_bsp_HEADERS = ../shared/liblnk/regs.h
     16#isr
     17include_bsp_HEADERS += ../../shared/include/irq-generic.h
     18include_bsp_HEADERS += ../../shared/include/irq-info.h
     19include_bsp_HEADERS += include/irq.h
    1620
    1721nodist_include_HEADERS = include/bspopts.h
     
    4246libbsp_a_SOURCES += ../../shared/bootcard.c
    4347libbsp_a_SOURCES += ../../shared/sbrk.c
    44 libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
    45 libbsp_a_SOURCES += ../../shared/setvec.c
    4648libbsp_a_SOURCES += startup/inittlb.c
    4749libbsp_a_SOURCES += ../shared/startup/idttlb.S
     
    5759libbsp_a_SOURCES += ../shared/liblnk/pmon.S
    5860libbsp_a_SOURCES += ../shared/liblnk/regs.h
     61#isr
     62libbsp_a_SOURCES += ../../shared/src/irq-generic.c
     63libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
     64libbsp_a_SOURCES += ../../shared/src/irq-info.c
     65libbsp_a_SOURCES += ../../shared/src/irq-shell.c
     66libbsp_a_SOURCES += ../../shared/src/irq-server.c
     67libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
     68libbsp_a_SOURCES += ../shared/irq/irq.c
     69libbsp_a_SOURCES += ../shared/irq/maxvectors.c
     70libbsp_a_SOURCES += irq/vectorisrs.c
     71libbsp_a_SOURCES += ../shared/irq/interruptmask_TX49.c
    5972
    6073libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
    6174libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
    6275libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/timer.rel
    63 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/vectorisrs.rel
    6476
    6577include $(srcdir)/preinstall.am
  • c/src/lib/libbsp/mips/rbtx4938/clock/clockdrv.c

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 *  Instantiate the clock driver shell.
     5 */
     6
    17/*
    2  *  Instantiate the clock driver shell.
     8 *  COPYRIGHT (c) 1989-2012.
     9 *  On-Line Applications Research Corporation (OAR).
    310 *
    4  *  clockdrv.c,v 1.5 2001/01/09 17:05:57 joel Exp
     11 *  The license and distribution terms for this file may be
     12 *  found in the file LICENSE in this distribution or at
     13 *  http://www.rtems.com/license/LICENSE.
     14 *
     15 *  $Id$
    516 */
    617
    718#include <rtems.h>
    8 #include <libcpu/tx4938.h>
     19#include <bsp/irq.h>
    920#include <bsp.h>
    1021
     
    3142#endif
    3243
     44void new_brk_esr(void);
    3345
    3446t_yamon_retfunc esr_retfunc = 0;
     
    5062#define Clock_driver_support_install_isr( _new, _old ) \
    5163  do { \
    52     _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
    53         YAMON_FUNC_REGISTER_IC_ISR(17,(t_yamon_isr)_new,0,&original_tmr0_isr); /* Call Yamon to enable interrupt */ \
     64    rtems_interrupt_handler_install( \
     65      CLOCK_VECTOR, \
     66      "clock", \
     67      0, \
     68      _new, \
     69      NULL \
     70    ); \
     71    YAMON_FUNC_REGISTER_IC_ISR(17,(t_yamon_isr)_new,0,&original_tmr0_isr); /* Call Yamon to enable interrupt */ \
    5472  } while(0)
    5573
  • c/src/lib/libbsp/mips/rbtx4938/include/bsp.h

    reb6362dc r0c0181d  
    1 /*  bsp.h
    2  *
     1/**
     2 *  @file
     3 * 
    34 *  This include file contains some definitions specific to the RBTX4938.
    4  *
    5  *  COPYRIGHT (c) 1989-2000.
     5 */
     6
     7/*
     8 *  COPYRIGHT (c) 1989-2012.
    69 *  On-Line Applications Research Corporation (OAR).
    710 *
     
    1013 *  http://www.rtems.com/license/LICENSE.
    1114 *
    12  *  bsp.h,v 1.7.6.1 2003/09/04 18:44:49 joel Exp
     15 *  $Id$
    1316 */
    1417
     
    2831#include <libcpu/tx4938.h>
    2932
     33#define BSP_FEATURE_IRQ_EXTENSION
     34#define BSP_SHARED_HANDLER_SUPPORT      1
     35
    3036/* functions */
    3137
  • c/src/lib/libbsp/mips/rbtx4938/preinstall.am

    reb6362dc r0c0181d  
    5050PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
    5151
     52$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     53        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     54PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     55
     56$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     57        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
     58PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
     59
     60$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     61        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
     62PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
     63
    5264$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
    5365        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
  • c/src/lib/libbsp/mips/rbtx4938/startup/bspstart.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  This routine starts the application.  It includes application,
    35 *  board, and monitor specific initialization and configuration.
    46 *  The generic CPU dependent initialization has been performed
    57 *  before this routine is invoked.
    6  *
    7  *  COPYRIGHT (c) 1989-2000.
     8 */
     9
     10/*
     11 *  COPYRIGHT (c) 1989-2012.
    812 *  On-Line Applications Research Corporation (OAR).
    913 *
     
    1115 *  found in the file LICENSE in this distribution or at
    1216 *  http://www.rtems.com/license/LICENSE.
    13  *
    14  *  bspstart.c,v 1.4.2.1 2003/09/04 18:44:49 joel Exp
     17 * 
     18 *  $Id$
    1519 */
    1620
    1721#include <bsp.h>
    1822#include <libcpu/isr_entries.h>
     23#include <bsp/irq-generic.h>
     24
     25void bsp_start( void );
    1926
    2027/*
     
    2532void bsp_start( void )
    2633{
    27   mips_install_isr_entries();  /* Install generic MIPS exception handler */
     34  bsp_interrupt_initialize();
    2835}
  • c/src/lib/libbsp/mips/shared/irq/maxvectors.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  This file contains the maximum number of vectors.  This can not
    35 *  be determined without knowing the RTEMS CPU model.
    4  *
    5  *  COPYRIGHT (c) 1989-2000.
     6 */
     7
     8/*
     9 *  COPYRIGHT (c) 1989-2012.
    610 *  On-Line Applications Research Corporation (OAR).
    711 *
     
    913 *  found in the file LICENSE in this distribution or at
    1014 *  http://www.rtems.com/license/LICENSE.
    11  *
     15 * 
    1216 *  $Id$
    1317 */
    1418
    15 /*
    16  *  Reserve first 32 for exceptions.
    17  */
     19#include <rtems.h>
     20#include <bsp/irq.h>
    1821
    19 unsigned int mips_interrupt_number_of_vectors = 32 + 8;
     22unsigned int mips_interrupt_number_of_vectors = BSP_INTERRUPT_VECTOR_MAX;
  • c/src/lib/libbsp/mips/shared/irq/vectorexceptions.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  Common Code for Vectoring MIPS Exceptions
    35 *
    46 *  The actual decoding of the cause register and vector number assignment
    57 *  is CPU model specific.
     8 */
     9
     10/*
     11 *  COPYRIGHT (c) 1989-2012.
     12 *  On-Line Applications Research Corporation (OAR).
    613 *
     14 *  The license and distribution terms for this file may be
     15 *  found in the file LICENSE in this distribution or at
     16 *  http://www.rtems.com/license/LICENSE.
     17 *
    718 *  $Id$
    819 */
     
    1425#include <rtems/mips/idtcpu.h>
    1526#include <rtems/bspIo.h>
     27#include <bsp/irq-generic.h>
     28
     29void mips_vector_exceptions( CPU_Interrupt_frame *frame );
    1630
    1731static const char *cause_strings[32] =
     
    88102}
    89103
    90 static void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame )
    91 {
    92   uint32_t sr;
    93   uint32_t cause;
    94 
    95   mips_get_sr( sr );
    96   mips_get_cause( cause );
    97 
    98   printk( "Unhandled exception %d\n", exc );
    99   printk( "sr: 0x%08x  cause: 0x%08x --> %s\n", sr, cause,
    100      cause_strings[(cause >> 2) &0x1f] );
    101   mips_dump_exception_frame( frame );
    102 
    103   rtems_fatal_error_occurred(1);
    104 }
    105 
    106 #define CALL_EXC(_vector,_frame) \
    107    do { \
    108         if ( _ISR_Vector_table[_vector] ) \
    109              (_ISR_Vector_table[_vector])(_vector,_frame); \
    110           else \
    111              mips_default_exception_code_handler( _vector, _frame ); \
    112    } while(0)
    113 
    114104/*
    115105 *  There are constants defined for these but they should basically
     
    125115  exc = (cause >> 2) & 0x1f;
    126116
    127   CALL_EXC( exc, frame );
     117  bsp_interrupt_handler_dispatch( exc );
    128118}
  • c/src/lib/libbsp/shared/clockdrv_shell.h

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 *  Clock Tick Device Driver Shell
     5 */
     6
    17/*
    2  *  Clock Tick Device Driver Shell
    3  *
    4  *  COPYRIGHT (c) 1989-2009.
     8 *  COPYRIGHT (c) 1989-2012.
    59 *  On-Line Applications Research Corporation (OAR).
    610 *
     
    5357 *  Return values:      NONE
    5458 */
     59#ifdef BSP_FEATURE_IRQ_EXTENSION
     60rtems_isr Clock_isr(void *arg);
     61rtems_isr Clock_isr(void *arg)
     62{
     63#else
     64rtems_isr Clock_isr(rtems_vector_number vector);
    5565rtems_isr Clock_isr(
    5666  rtems_vector_number vector
    5767)
    5868{
     69#endif
    5970  /*
    6071   *  Accurate count of ISRs
  • c/src/lib/libcpu/mips/ChangeLog

    reb6362dc r0c0181d  
     12012-02-23      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        PR 1993/bsps
     4        * Makefile.am, au1x00/include/au1x00.h,
     5        mongoosev/duart/mg5uart.c, mongoosev/include/mongoose-v.h,
     6        rm52xx/include/rm5231.h, shared/interrupts/isr_entries.h,
     7        tx39/include/tx3904.h, tx49/include/tx4925.h,
     8        tx49/include/tx4938.h:
     9        Mips conversion to PIC IRQ model.
     10        * au1x00/vectorisrs/maxvectors.c,mongoosev/vectorisrs/maxvectors.c
     11        rm52xx/vectorisrs/maxvectors.c, tx39/vectorisrs/maxvectors.c,
     12        tx49/vectorisrs/maxvectors.c: Removed.
     13
    1142011-12-10      Ralf Corsépius <ralf.corsepius@rtems.org>
    215
  • c/src/lib/libcpu/mips/Makefile.am

    reb6362dc r0c0181d  
    4242noinst_PROGRAMS += shared/interrupts.rel
    4343shared_interrupts_rel_SOURCES = shared/interrupts/installisrentries.c \
    44     shared/interrupts/vectorexceptions.c shared/interrupts/interruptmask.c \
    4544    shared/interrupts/isr_entries.S shared/interrupts/isr_entries.h
    4645shared_interrupts_rel_CPPFLAGS = $(AM_CPPFLAGS) $(interrupts_CPPFLAGS)
     
    6362mongoosev_duart_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    6463
    65 ## mongoosev/vectorisrs
    66 
    67 noinst_PROGRAMS += mongoosev/vectorisrs.rel
    68 mongoosev_vectorisrs_rel_SOURCES = mongoosev/vectorisrs/maxvectors.c \
    69    mongoosev/vectorisrs/vectorisrs.c
    70 mongoosev_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
    71 mongoosev_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    7264endif
    7365
    7466if tx39
    7567include_libcpu_HEADERS += tx39/include/tx3904.h
    76 
    77 noinst_PROGRAMS += tx39/vectorisrs.rel
    78 tx39_vectorisrs_rel_SOURCES = tx39/vectorisrs/maxvectors.c tx39/vectorisrs/vectorisrs.c
    79 tx39_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
    80 tx39_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    8168endif
    8269
    8370if tx49
    8471include_libcpu_HEADERS += tx49/include/tx4925.h tx49/include/tx4938.h
    85 
    86 noinst_PROGRAMS += tx49/vectorisrs.rel
    87 tx49_vectorisrs_rel_SOURCES = tx49/vectorisrs/maxvectors.c tx49/vectorisrs/vectorisrs.c
    88 tx49_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
    89 tx49_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    9072
    9173noinst_PROGRAMS += tx49/timer.rel
     
    9880include_libcpu_HEADERS += au1x00/include/au1x00.h
    9981
    100 noinst_PROGRAMS += au1x00/vectorisrs.rel
    101 au1x00_vectorisrs_rel_SOURCES = au1x00/vectorisrs/maxvectors.c \
    102   au1x00/vectorisrs/vectorisrs.c
    103 au1x00_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
    104 au1x00_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    10582endif
    10683
    10784if r46xx
    108 noinst_PROGRAMS += r46xx/vectorisrs.rel
    109 r46xx_vectorisrs_rel_SOURCES = r46xx/vectorisrs/maxvectors.c \
    110    r46xx/vectorisrs/vectorisrs.c
    111 r46xx_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
    112 r46xx_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    113 
    11485noinst_PROGRAMS += r46xx/timer.rel
    11586r46xx_timer_rel_SOURCES = timer/timer.c timer/gettime.S
     
    12697include_libcpu_HEADERS += rm52xx/include/rm5231.h
    12798
    128 noinst_PROGRAMS += rm52xx/vectorisrs.rel
    129 rm52xx_vectorisrs_rel_SOURCES = rm52xx/vectorisrs/maxvectors.c rm52xx/vectorisrs/vectorisrs.c
    130 rm52xx_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS)
    131 rm52xx_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    132 
    13399noinst_PROGRAMS += rm52xx/timer.rel
    134100rm52xx_timer_rel_SOURCES = timer/timer.c timer/gettime.S
  • c/src/lib/libcpu/mips/au1x00/include/au1x00.h

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 *  AMD AU1X00 specific information
     5 */
     6
    17/*
    2  *  AMD AU1X00 specific information
    3  *
    4  * Copyright (c) 2005 by Cogent Computer Systems
    5  * Written by Jay Monkman <jtm@lopingdog.com>
     8 *  Copyright (c) 2005 by Cogent Computer Systems
     9 *  Written by Jay Monkman <jtm@lopingdog.com>
    610 *
    711 *  The license and distribution terms for this file may be
    812 *  found in the file LICENSE in this distribution or at
    9  *
    1013 *  http://www.rtems.com/license/LICENSE.
    11  *
     14 * 
    1215 *  $Id$
    13  *
    1416 */
    1517
     
    429431extern au1x00_uart_t *uart3;
    430432
    431 /*
    432  *  Interrupt Vector Numbers
    433  *
    434  */
    435 /* MIPS_INTERRUPT_BASE should be 32 (0x20) */
    436 #define AU1X00_IRQ_SW0                (MIPS_INTERRUPT_BASE + 0)
    437 #define AU1X00_IRQ_SW1                (MIPS_INTERRUPT_BASE + 1)
    438 #define AU1X00_IRQ_IC0_REQ0           (MIPS_INTERRUPT_BASE + 2)
    439 #define AU1X00_IRQ_IC0_REQ1           (MIPS_INTERRUPT_BASE + 3)
    440 #define AU1X00_IRQ_IC1_REQ0           (MIPS_INTERRUPT_BASE + 4)
    441 #define AU1X00_IRQ_IC1_REQ1           (MIPS_INTERRUPT_BASE + 5)
    442 #define AU1X00_IRQ_PERF               (MIPS_INTERRUPT_BASE + 6)
    443 #define AU1X00_IRQ_CNT                (MIPS_INTERRUPT_BASE + 7)
    444 
    445 #define AU1X00_IRQ_IC0_BASE           (MIPS_INTERRUPT_BASE + 8)
    446 #define AU1X00_IRQ_UART0              (MIPS_INTERRUPT_BASE + 8)
    447 #define AU1X00_IRQ_INTA               (MIPS_INTERRUPT_BASE + 9)
    448 #define AU1X00_IRQ_INTB               (MIPS_INTERRUPT_BASE + 10)
    449 #define AU1X00_IRQ_UART3              (MIPS_INTERRUPT_BASE + 11)
    450 #define AU1X00_IRQ_INTC               (MIPS_INTERRUPT_BASE + 12)
    451 #define AU1X00_IRQ_INTD               (MIPS_INTERRUPT_BASE + 13)
    452 #define AU1X00_IRQ_DMA0               (MIPS_INTERRUPT_BASE + 14)
    453 #define AU1X00_IRQ_DMA1               (MIPS_INTERRUPT_BASE + 15)
    454 #define AU1X00_IRQ_DMA2               (MIPS_INTERRUPT_BASE + 16)
    455 #define AU1X00_IRQ_DMA3               (MIPS_INTERRUPT_BASE + 17)
    456 #define AU1X00_IRQ_DMA4               (MIPS_INTERRUPT_BASE + 18)
    457 #define AU1X00_IRQ_DMA5               (MIPS_INTERRUPT_BASE + 19)
    458 #define AU1X00_IRQ_DMA6               (MIPS_INTERRUPT_BASE + 20)
    459 #define AU1X00_IRQ_DMA7               (MIPS_INTERRUPT_BASE + 21)
    460 #define AU1X00_IRQ_TOY_TICK           (MIPS_INTERRUPT_BASE + 22)
    461 #define AU1X00_IRQ_TOY_MATCH0         (MIPS_INTERRUPT_BASE + 23)
    462 #define AU1X00_IRQ_TOY_MATCH1         (MIPS_INTERRUPT_BASE + 24)
    463 #define AU1X00_IRQ_TOY_MATCH2         (MIPS_INTERRUPT_BASE + 25)
    464 #define AU1X00_IRQ_RTC_TICK           (MIPS_INTERRUPT_BASE + 26)
    465 #define AU1X00_IRQ_RTC_MATCH0         (MIPS_INTERRUPT_BASE + 27)
    466 #define AU1X00_IRQ_RTC_MATCH1         (MIPS_INTERRUPT_BASE + 28)
    467 #define AU1X00_IRQ_RTC_MATCH2         (MIPS_INTERRUPT_BASE + 29)
    468 #define AU1X00_IRQ_PCI_ERR            (MIPS_INTERRUPT_BASE + 30)
    469 #define AU1X00_IRQ_RSV0               (MIPS_INTERRUPT_BASE + 31)
    470 #define AU1X00_IRQ_USB_DEV            (MIPS_INTERRUPT_BASE + 32)
    471 #define AU1X00_IRQ_USB_SUSPEND        (MIPS_INTERRUPT_BASE + 33)
    472 #define AU1X00_IRQ_USB_HOST           (MIPS_INTERRUPT_BASE + 34)
    473 #define AU1X00_IRQ_AC97_ACSYNC        (MIPS_INTERRUPT_BASE + 35)
    474 #define AU1X00_IRQ_MAC0               (MIPS_INTERRUPT_BASE + 36)
    475 #define AU1X00_IRQ_MAC1               (MIPS_INTERRUPT_BASE + 37)
    476 #define AU1X00_IRQ_RSV1               (MIPS_INTERRUPT_BASE + 38)
    477 #define AU1X00_IRQ_AC97_CMD           (MIPS_INTERRUPT_BASE + 39)
    478 
    479 #define AU1X00_IRQ_IC1_BASE           (MIPS_INTERRUPT_BASE + 40)
    480 #define AU1X00_IRQ_GPIO0              (MIPS_INTERRUPT_BASE + 40)
    481 #define AU1X00_IRQ_GPIO1              (MIPS_INTERRUPT_BASE + 41)
    482 #define AU1X00_IRQ_GPIO2              (MIPS_INTERRUPT_BASE + 42)
    483 #define AU1X00_IRQ_GPIO3              (MIPS_INTERRUPT_BASE + 43)
    484 #define AU1X00_IRQ_GPIO4              (MIPS_INTERRUPT_BASE + 44)
    485 #define AU1X00_IRQ_GPIO5              (MIPS_INTERRUPT_BASE + 45)
    486 #define AU1X00_IRQ_GPIO6              (MIPS_INTERRUPT_BASE + 46)
    487 #define AU1X00_IRQ_GPIO7              (MIPS_INTERRUPT_BASE + 47)
    488 #define AU1X00_IRQ_GPIO8              (MIPS_INTERRUPT_BASE + 48)
    489 #define AU1X00_IRQ_GPIO9              (MIPS_INTERRUPT_BASE + 49)
    490 #define AU1X00_IRQ_GPIO10             (MIPS_INTERRUPT_BASE + 50)
    491 #define AU1X00_IRQ_GPIO11             (MIPS_INTERRUPT_BASE + 51)
    492 #define AU1X00_IRQ_GPIO12             (MIPS_INTERRUPT_BASE + 52)
    493 #define AU1X00_IRQ_GPIO13             (MIPS_INTERRUPT_BASE + 53)
    494 #define AU1X00_IRQ_GPIO14             (MIPS_INTERRUPT_BASE + 54)
    495 #define AU1X00_IRQ_GPIO15             (MIPS_INTERRUPT_BASE + 55)
    496 #define AU1X00_IRQ_GPIO200            (MIPS_INTERRUPT_BASE + 56)
    497 #define AU1X00_IRQ_GPIO201            (MIPS_INTERRUPT_BASE + 57)
    498 #define AU1X00_IRQ_GPIO202            (MIPS_INTERRUPT_BASE + 58)
    499 #define AU1X00_IRQ_GPIO203            (MIPS_INTERRUPT_BASE + 59)
    500 #define AU1X00_IRQ_GPIO20             (MIPS_INTERRUPT_BASE + 60)
    501 #define AU1X00_IRQ_GPIO204            (MIPS_INTERRUPT_BASE + 61)
    502 #define AU1X00_IRQ_GPIO205            (MIPS_INTERRUPT_BASE + 62)
    503 #define AU1X00_IRQ_GPIO23             (MIPS_INTERRUPT_BASE + 63)
    504 #define AU1X00_IRQ_GPIO24             (MIPS_INTERRUPT_BASE + 64)
    505 #define AU1X00_IRQ_GPIO25             (MIPS_INTERRUPT_BASE + 65)
    506 #define AU1X00_IRQ_GPIO26             (MIPS_INTERRUPT_BASE + 66)
    507 #define AU1X00_IRQ_GPIO27             (MIPS_INTERRUPT_BASE + 67)
    508 #define AU1X00_IRQ_GPIO28             (MIPS_INTERRUPT_BASE + 68)
    509 #define AU1X00_IRQ_GPIO206            (MIPS_INTERRUPT_BASE + 69)
    510 #define AU1X00_IRQ_GPIO207            (MIPS_INTERRUPT_BASE + 70)
    511 #define AU1X00_IRQ_GPIO208_215        (MIPS_INTERRUPT_BASE + 71)
    512 
    513 #define AU1X00_MAXIMUM_VECTORS        (MIPS_INTERRUPT_BASE + 72)
    514 
    515433void static inline au_sync(void)
    516434{
  • c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  This file contains the termios TTY driver for the UART found
    35 *  on the Synova Mongoose-V.
    4  *
    5  *  COPYRIGHT (c) 1989-2001.
     6 */
     7
     8/*
     9 *  COPYRIGHT (c) 1989-2012.
    610 *  On-Line Applications Research Corporation (OAR).
    711 *
     
    913 *  found in the file LICENSE in this distribution or at
    1014 *  http://www.rtems.com/license/LICENSE.
    11  *
     15 * 
    1216 *  $Id$
    1317 */
     
    2226#include <libcpu/mongoose-v.h>
    2327
    24 extern void set_vector( rtems_isr_entry, rtems_vector_number, int );
     28#include <bsp/irq.h>
     29#include <bsp.h>
    2530
    2631/*
     
    6974  int mask
    7075);
    71 
    72 /*
    73  *  mg5uart_set_attributes
    74  *
    75  *  This function sets the UART channel to reflect the requested termios
    76  *  port settings.
    77  */
    78 
    79 MG5UART_STATIC int mg5uart_set_attributes(
    80   int minor,
    81   const struct termios *t
    82 )
    83 {
    84   uint32_t               pMG5UART_port;
    85   uint32_t               pMG5UART;
    86   uint32_t               cmd, cmdSave;
    87   uint32_t               baudcmd;
    88   uint32_t               shift;
    89   rtems_interrupt_level  Irql;
    90 
    91   pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
    92   pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
    93 
    94   /*
    95    *  Set the baud rate
    96    */
    97 
    98   if (mg5uart_baud_rate( minor, t->c_cflag, &baudcmd ) == -1)
    99     return -1;
    100 
    101   /*
    102    *  Base settings
    103    */
    104 
    105   /*
    106    *  Base settings
    107    */
    108 
    109   cmd = MONGOOSEV_UART_CMD_RX_ENABLE | MONGOOSEV_UART_CMD_TX_ENABLE;
    110 
    111   /*
    112    *  Parity
    113    */
    114 
    115   if (t->c_cflag & PARENB) {
    116     cmd |= MONGOOSEV_UART_CMD_PARITY_ENABLE;
    117     if (t->c_cflag & PARODD)
    118       cmd |= MONGOOSEV_UART_CMD_PARITY_ODD;
    119     else
    120       cmd |= MONGOOSEV_UART_CMD_PARITY_EVEN;
    121   } else {
    122     cmd |= MONGOOSEV_UART_CMD_PARITY_DISABLE;
    123   }
    124 
    125   /*
    126    *  Character Size
    127    */
    128 
    129   if (t->c_cflag & CSIZE) {
    130     switch (t->c_cflag & CSIZE) {
    131       case CS5:
    132       case CS6:
    133       case CS7:
    134         return -1;
    135         break;
    136       case CS8:
    137         /* Mongoose-V only supports CS8 */
    138         break;
    139 
    140     }
    141   } /* else default to CS8 */
    142 
    143   /*
    144    *  Stop Bits
    145    */
    146 
    147 #if 0
    148   if (t->c_cflag & CSTOPB) {
    149     /* 2 stop bits not supported by Mongoose-V uart */
    150     return -1;
    151   }
    152 #endif
    153 
    154   /*
    155    *  XXX what about CTS/RTS
    156    */
    157 
    158   /* XXX */
    159 
    160   /*
    161    *  Now write the registers
    162    */
    163 
    164   if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
    165     shift = MONGOOSEV_UART0_CMD_SHIFT;
    166   else
    167     shift = MONGOOSEV_UART1_CMD_SHIFT;
    168 
    169 
    170 
    171   rtems_interrupt_disable(Irql);
    172 
    173   cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
    174 
    175   MG5UART_SETREG( pMG5UART,
    176                   MG5UART_COMMAND_REGISTER,
    177                   (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
    178 
    179   MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
    180 
    181   rtems_interrupt_enable(Irql);
    182   return 0;
    183 }
    184 
    185 /*
    186  *  mg5uart_initialize_context
    187  *
    188  *  This function sets the default values of the per port context structure.
    189  */
    190 
    191 MG5UART_STATIC void mg5uart_initialize_context(
    192   int               minor,
    193   mg5uart_context  *pmg5uartContext
    194 )
    195 {
    196   int          port;
    197   unsigned int pMG5UART;
    198   unsigned int pMG5UART_port;
    199 
    200   pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
    201   pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
    202 
    203   pmg5uartContext->mate = -1;
    204 
    205   for (port=0 ; port<Console_Port_Count ; port++ ) {
    206     if ( Console_Port_Tbl[port]->ulCtrlPort1 == pMG5UART &&
    207          Console_Port_Tbl[port]->ulCtrlPort2 != pMG5UART_port ) {
    208       pmg5uartContext->mate = port;
    209       break;
    210     }
    211   }
    212 
    213 }
    214 
    215 /*
    216  *  mg5uart_init
    217  *
    218  *  This function initializes the DUART to a quiecsent state.
    219  */
    220 
    221 MG5UART_STATIC void mg5uart_init(int minor)
    222 {
    223   uint32_t              pMG5UART_port;
    224   uint32_t              pMG5UART;
    225   uint32_t              cmdSave;
    226   uint32_t              shift;
    227 
    228   mg5uart_context        *pmg5uartContext;
    229 
    230   pmg5uartContext = (mg5uart_context *) malloc(sizeof(mg5uart_context));
    231 
    232   Console_Port_Data[minor].pDeviceContext = (void *)pmg5uartContext;
    233 
    234   mg5uart_initialize_context( minor, pmg5uartContext );
    235 
    236   pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
    237   pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
    238 
    239   if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
    240      shift = MONGOOSEV_UART0_CMD_SHIFT;
    241   else
    242      shift = MONGOOSEV_UART1_CMD_SHIFT;
    243 
    244   /*
    245    *  Disable the uart and leave this port disabled.
    246    */
    247 
    248   cmdSave = MG5UART_GETREG(pMG5UART, MG5UART_COMMAND_REGISTER) & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift);
    249 
    250   MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmdSave );
    251 
    252   /*
    253    *  Disable interrupts on RX and TX for this port
    254    */
    255   mg5uart_enable_interrupts( minor, MG5UART_DISABLE_ALL );
    256 }
    257 
    258 /*
    259  *  mg5uart_open
    260  *
    261  *  This function opens a port for communication.
    262  *
    263  *  Default state is 9600 baud, 8 bits, No parity, and 1 stop bit.
    264  */
    265 
    266 MG5UART_STATIC int mg5uart_open(
    267   int      major,
    268   int      minor,
    269   void    *arg
    270 )
    271 {
    272   uint32_t      pMG5UART;
    273   uint32_t      pMG5UART_port;
    274   uint32_t      vector;
    275   uint32_t      cmd, cmdSave;
    276   uint32_t      baudcmd;
    277   uint32_t      shift;
    278 
    279   rtems_interrupt_level  Irql;
    280 
    281   pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
    282   pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
    283   vector        = Console_Port_Tbl[minor]->ulIntVector;
    284 
    285   if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
    286     shift = MONGOOSEV_UART0_CMD_SHIFT;
    287   else
    288     shift = MONGOOSEV_UART1_CMD_SHIFT;
    289 
    290 
    291   /* XXX default baud rate could be from configuration table */
    292 
    293   (void) mg5uart_baud_rate( minor, B19200, &baudcmd );
    294 
    295   /*
    296    *  Set the DUART channel to a default useable state
    297    *  B19200, 8Nx since there is no stop bit control.
    298    */
    299 
    300   cmd = MONGOOSEV_UART_CMD_TX_ENABLE | MONGOOSEV_UART_CMD_RX_ENABLE;
    301 
    302   rtems_interrupt_disable(Irql);
    303 
    304   cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
    305 
    306   MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
    307 
    308   MG5UART_SETREG( pMG5UART,
    309                   MG5UART_COMMAND_REGISTER,
    310                   cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
    311 
    312   rtems_interrupt_enable(Irql);
    313 
    314   return RTEMS_SUCCESSFUL;
    315 }
    316 
    317 /*
    318  *  mg5uart_close
    319  *
    320  *  This function shuts down the requested port.
    321  */
    322 
    323 MG5UART_STATIC int mg5uart_close(
    324   int      major,
    325   int      minor,
    326   void    *arg
    327 )
    328 {
    329   uint32_t      pMG5UART;
    330   uint32_t      pMG5UART_port;
    331   uint32_t      cmd, cmdSave;
    332   uint32_t      shift;
    333   rtems_interrupt_level  Irql;
    334 
    335   pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
    336   pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
    337 
    338   /*
    339    *  Disable interrupts from this channel and then disable it totally.
    340    */
    341 
    342   /* XXX interrupts */
    343 
    344   cmd = MONGOOSEV_UART_CMD_TX_DISABLE | MONGOOSEV_UART_CMD_RX_DISABLE;
    345 
    346   if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
    347     shift = MONGOOSEV_UART0_CMD_SHIFT;
    348   else
    349     shift = MONGOOSEV_UART1_CMD_SHIFT;
    350 
    351 
    352   rtems_interrupt_disable(Irql);
    353   cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
    354 
    355   MG5UART_SETREG( pMG5UART,
    356                   MG5UART_COMMAND_REGISTER,
    357                   (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
    358   rtems_interrupt_enable(Irql);
    359 
    360   return(RTEMS_SUCCESSFUL);
    361 }
    362 
    363 
    364 
    365 
    366 /*
    367  *  mg5uart_write_polled
    368  *
    369  *  This routine polls out the requested character.
    370  */
    371 
    372 MG5UART_STATIC void mg5uart_write_polled(
    373   int   minor,
    374   char  c
    375 )
    376 {
    377   uint32_t                pMG5UART;
    378   uint32_t                pMG5UART_port;
    379   uint32_t                status;
    380   int                     shift;
    381   int                     timeout;
    382 
    383   pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
    384   pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
    385 
    386   if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
    387     shift = MONGOOSEV_UART0_IRQ_SHIFT;
    388   else
    389     shift = MONGOOSEV_UART1_IRQ_SHIFT;
    390 
    391   /*
    392    * wait for transmitter holding register to be empty
    393    */
    394   timeout = 2000;
    395 
    396   while( --timeout )
    397   {
    398     status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
    399 
    400     /*
    401     if ( (status & (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY)) ==
    402             (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY) )
    403       break;
    404     */
    405 
    406     if( (status & (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY)) )
    407        break;
    408 
    409     /*
    410      * Yield while we wait
    411      */
    412 
    413 #if 0
    414      if(_System_state_Is_up(_System_state_Get()))
    415      {
    416        rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
    417      }
    418 #endif
    419   }
    420 
    421   /*
    422    * transmit character
    423    */
    424 
    425   MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, c);
    426 }
    427 
    428 
    429 
    43076
    43177/*
     
    44995  \
    45096  MG5UART_STATIC rtems_isr mg5uart_isr_ ## _TYPE ( \
    451     rtems_vector_number vector \
     97    void *arg \
    45298  ) \
    45399  { \
     100    rtems_vector_number vector = (rtems_vector_number) arg; \
    454101    int   minor; \
    455102    \
     
    470117__ISR(rx_ready, MG5UART_IRQ_RX_READY)
    471118
     119/*
     120 *  mg5uart_set_attributes
     121 *
     122 *  This function sets the UART channel to reflect the requested termios
     123 *  port settings.
     124 */
     125
     126MG5UART_STATIC int mg5uart_set_attributes(
     127  int minor,
     128  const struct termios *t
     129)
     130{
     131  uint32_t               pMG5UART_port;
     132  uint32_t               pMG5UART;
     133  uint32_t               cmd, cmdSave;
     134  uint32_t               baudcmd;
     135  uint32_t               shift;
     136  rtems_interrupt_level  Irql;
     137
     138  pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
     139  pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
     140
     141  /*
     142   *  Set the baud rate
     143   */
     144
     145  if (mg5uart_baud_rate( minor, t->c_cflag, &baudcmd ) == -1)
     146    return -1;
     147
     148  /*
     149   *  Base settings
     150   */
     151
     152  /*
     153   *  Base settings
     154   */
     155
     156  cmd = MONGOOSEV_UART_CMD_RX_ENABLE | MONGOOSEV_UART_CMD_TX_ENABLE;
     157
     158  /*
     159   *  Parity
     160   */
     161
     162  if (t->c_cflag & PARENB) {
     163    cmd |= MONGOOSEV_UART_CMD_PARITY_ENABLE;
     164    if (t->c_cflag & PARODD)
     165      cmd |= MONGOOSEV_UART_CMD_PARITY_ODD;
     166    else
     167      cmd |= MONGOOSEV_UART_CMD_PARITY_EVEN;
     168  } else {
     169    cmd |= MONGOOSEV_UART_CMD_PARITY_DISABLE;
     170  }
     171
     172  /*
     173   *  Character Size
     174   */
     175
     176  if (t->c_cflag & CSIZE) {
     177    switch (t->c_cflag & CSIZE) {
     178      case CS5:
     179      case CS6:
     180      case CS7:
     181        return -1;
     182        break;
     183      case CS8:
     184        /* Mongoose-V only supports CS8 */
     185        break;
     186
     187    }
     188  } /* else default to CS8 */
     189
     190  /*
     191   *  Stop Bits
     192   */
     193
     194#if 0
     195  if (t->c_cflag & CSTOPB) {
     196    /* 2 stop bits not supported by Mongoose-V uart */
     197    return -1;
     198  }
     199#endif
     200
     201  /*
     202   *  XXX what about CTS/RTS
     203   */
     204
     205  /* XXX */
     206
     207  /*
     208   *  Now write the registers
     209   */
     210
     211  if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
     212    shift = MONGOOSEV_UART0_CMD_SHIFT;
     213  else
     214    shift = MONGOOSEV_UART1_CMD_SHIFT;
     215
     216
     217
     218  rtems_interrupt_disable(Irql);
     219
     220  cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
     221
     222  MG5UART_SETREG( pMG5UART,
     223                  MG5UART_COMMAND_REGISTER,
     224                  (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
     225
     226  MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
     227
     228  rtems_interrupt_enable(Irql);
     229  return 0;
     230}
     231
     232/*
     233 *  mg5uart_initialize_context
     234 *
     235 *  This function sets the default values of the per port context structure.
     236 */
     237
     238MG5UART_STATIC void mg5uart_initialize_context(
     239  int               minor,
     240  mg5uart_context  *pmg5uartContext
     241)
     242{
     243  int          port;
     244  unsigned int pMG5UART;
     245  unsigned int pMG5UART_port;
     246
     247  pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
     248  pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
     249
     250  pmg5uartContext->mate = -1;
     251
     252  for (port=0 ; port<Console_Port_Count ; port++ ) {
     253    if ( Console_Port_Tbl[port]->ulCtrlPort1 == pMG5UART &&
     254         Console_Port_Tbl[port]->ulCtrlPort2 != pMG5UART_port ) {
     255      pmg5uartContext->mate = port;
     256      break;
     257    }
     258  }
     259
     260}
     261
     262/*
     263 *  mg5uart_init
     264 *
     265 *  This function initializes the DUART to a quiecsent state.
     266 */
     267
     268MG5UART_STATIC void mg5uart_init(int minor)
     269{
     270  uint32_t              pMG5UART_port;
     271  uint32_t              pMG5UART;
     272  uint32_t              cmdSave;
     273  uint32_t              shift;
     274
     275  mg5uart_context        *pmg5uartContext;
     276
     277  pmg5uartContext = (mg5uart_context *) malloc(sizeof(mg5uart_context));
     278
     279  Console_Port_Data[minor].pDeviceContext = (void *)pmg5uartContext;
     280
     281  mg5uart_initialize_context( minor, pmg5uartContext );
     282
     283  pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
     284  pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
     285
     286  if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
     287     shift = MONGOOSEV_UART0_CMD_SHIFT;
     288  else
     289     shift = MONGOOSEV_UART1_CMD_SHIFT;
     290
     291  /*
     292   *  Disable the uart and leave this port disabled.
     293   */
     294
     295  cmdSave = MG5UART_GETREG(pMG5UART, MG5UART_COMMAND_REGISTER) & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift);
     296
     297  MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmdSave );
     298
     299  /*
     300   *  Disable interrupts on RX and TX for this port
     301   */
     302  mg5uart_enable_interrupts( minor, MG5UART_DISABLE_ALL );
     303}
     304
     305/*
     306 *  mg5uart_open
     307 *
     308 *  This function opens a port for communication.
     309 *
     310 *  Default state is 9600 baud, 8 bits, No parity, and 1 stop bit.
     311 */
     312
     313MG5UART_STATIC int mg5uart_open(
     314  int      major,
     315  int      minor,
     316  void    *arg
     317)
     318{
     319  uint32_t      pMG5UART;
     320  uint32_t      pMG5UART_port;
     321  uint32_t      vector;
     322  uint32_t      cmd, cmdSave;
     323  uint32_t      baudcmd;
     324  uint32_t      shift;
     325
     326  rtems_interrupt_level  Irql;
     327
     328  pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
     329  pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
     330  vector        = Console_Port_Tbl[minor]->ulIntVector;
     331
     332  if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
     333    shift = MONGOOSEV_UART0_CMD_SHIFT;
     334  else
     335    shift = MONGOOSEV_UART1_CMD_SHIFT;
     336
     337
     338  /* XXX default baud rate could be from configuration table */
     339
     340  (void) mg5uart_baud_rate( minor, B19200, &baudcmd );
     341
     342  /*
     343   *  Set the DUART channel to a default useable state
     344   *  B19200, 8Nx since there is no stop bit control.
     345   */
     346
     347  cmd = MONGOOSEV_UART_CMD_TX_ENABLE | MONGOOSEV_UART_CMD_RX_ENABLE;
     348
     349  rtems_interrupt_disable(Irql);
     350
     351  cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
     352
     353  MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
     354
     355  MG5UART_SETREG( pMG5UART,
     356                  MG5UART_COMMAND_REGISTER,
     357                  cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
     358
     359  rtems_interrupt_enable(Irql);
     360
     361  return RTEMS_SUCCESSFUL;
     362}
     363
     364/*
     365 *  mg5uart_close
     366 *
     367 *  This function shuts down the requested port.
     368 */
     369
     370MG5UART_STATIC int mg5uart_close(
     371  int      major,
     372  int      minor,
     373  void    *arg
     374)
     375{
     376  uint32_t      pMG5UART;
     377  uint32_t      pMG5UART_port;
     378  uint32_t      cmd, cmdSave;
     379  uint32_t      shift;
     380  rtems_interrupt_level  Irql;
     381
     382  pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
     383  pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
     384
     385  /*
     386   *  Disable interrupts from this channel and then disable it totally.
     387   */
     388
     389  /* XXX interrupts */
     390
     391  cmd = MONGOOSEV_UART_CMD_TX_DISABLE | MONGOOSEV_UART_CMD_RX_DISABLE;
     392
     393  if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
     394    shift = MONGOOSEV_UART0_CMD_SHIFT;
     395  else
     396    shift = MONGOOSEV_UART1_CMD_SHIFT;
     397
     398
     399  rtems_interrupt_disable(Irql);
     400  cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
     401
     402  MG5UART_SETREG( pMG5UART,
     403                  MG5UART_COMMAND_REGISTER,
     404                  (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
     405  rtems_interrupt_enable(Irql);
     406
     407  return(RTEMS_SUCCESSFUL);
     408}
     409
     410
     411
     412
     413/*
     414 *  mg5uart_write_polled
     415 *
     416 *  This routine polls out the requested character.
     417 */
     418
     419MG5UART_STATIC void mg5uart_write_polled(
     420  int   minor,
     421  char  c
     422)
     423{
     424  uint32_t                pMG5UART;
     425  uint32_t                pMG5UART_port;
     426  uint32_t                status;
     427  int                     shift;
     428  int                     timeout;
     429
     430  pMG5UART      = Console_Port_Tbl[minor]->ulCtrlPort1;
     431  pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
     432
     433  if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
     434    shift = MONGOOSEV_UART0_IRQ_SHIFT;
     435  else
     436    shift = MONGOOSEV_UART1_IRQ_SHIFT;
     437
     438  /*
     439   * wait for transmitter holding register to be empty
     440   */
     441  timeout = 2000;
     442
     443  while( --timeout )
     444  {
     445    status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
     446
     447    /*
     448    if ( (status & (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY)) ==
     449            (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY) )
     450      break;
     451    */
     452
     453    if( (status & (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY)) )
     454       break;
     455
     456    /*
     457     * Yield while we wait
     458     */
     459
     460#if 0
     461     if(_System_state_Is_up(_System_state_Get()))
     462     {
     463       rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
     464     }
     465#endif
     466  }
     467
     468  /*
     469   * transmit character
     470   */
     471
     472  MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, c);
     473}
    472474
    473475MG5UART_STATIC void mg5uart_process_isr_rx_error(
     
    592594}
    593595
    594 
    595 
    596 
     596static rtems_irq_connect_data mg5uart_rx_frame_error_cd  = {  \
     597  0,                             /* filled in at initialization */
     598  mg5uart_isr_rx_frame_error,   /* filled in at initialization */
     599  NULL,   /* (void *) minor */
     600  NULL,
     601  NULL,
     602  NULL
     603};
     604
     605static rtems_irq_connect_data mg5uart_rx_overrun_error_cd  = {  \
     606  0,                             /* filled in at initialization */
     607  mg5uart_isr_rx_overrun_error,   /* filled in at initialization */
     608  NULL,   /* (void *) minor */
     609  NULL,
     610  NULL,
     611  NULL
     612};
     613
     614static rtems_irq_connect_data mg5uart_tx_empty_cd  = {  \
     615  0,                             /* filled in at initialization */
     616  mg5uart_isr_tx_empty,   /* filled in at initialization */
     617  NULL,   /* (void *) minor */
     618  NULL,
     619  NULL,
     620  NULL
     621};
     622
     623static rtems_irq_connect_data mg5uart_tx_ready_cd  = {  \
     624  0,                             /* filled in at initialization */
     625  mg5uart_isr_tx_ready,   /* filled in at initialization */
     626  NULL,   /* (void *) minor */
     627  NULL,
     628  NULL,
     629  NULL
     630};
     631
     632static rtems_irq_connect_data mg5uart_rx_ready_cd  = {  \
     633  0,                             /* filled in at initialization */
     634  mg5uart_isr_rx_ready,   /* filled in at initialization */
     635  NULL,   /* (void *) minor */
     636  NULL,
     637  NULL,
     638  NULL
     639};
    597640
    598641
     
    612655  v = Console_Port_Tbl[minor]->ulIntVector;
    613656
    614   set_vector(mg5uart_isr_rx_frame_error,   v + MG5UART_IRQ_RX_FRAME_ERROR, 1);
    615   set_vector(mg5uart_isr_rx_overrun_error, v + MG5UART_IRQ_RX_OVERRUN_ERROR, 1);
    616   set_vector(mg5uart_isr_tx_empty,         v + MG5UART_IRQ_TX_EMPTY, 1);
    617   set_vector(mg5uart_isr_tx_ready,         v + MG5UART_IRQ_TX_READY, 1);
    618   set_vector(mg5uart_isr_rx_ready,         v + MG5UART_IRQ_RX_READY, 1);
     657  mg5uart_rx_frame_error_cd.name    =  v + MG5UART_IRQ_RX_FRAME_ERROR;
     658  mg5uart_rx_overrun_error_cd.name  =  v + MG5UART_IRQ_RX_OVERRUN_ERROR;
     659  mg5uart_tx_empty_cd.name          =  v + MG5UART_IRQ_TX_EMPTY; 
     660  mg5uart_tx_ready_cd.name          =  v + MG5UART_IRQ_TX_READY;
     661  mg5uart_rx_ready_cd.name          =  v + MG5UART_IRQ_RX_READY;
     662
     663  mg5uart_rx_frame_error_cd.handle    =  (void *)mg5uart_rx_frame_error_cd.name;
     664  mg5uart_rx_overrun_error_cd.handle  =  (void *)mg5uart_rx_overrun_error_cd.name;
     665  mg5uart_tx_empty_cd.handle          =  (void *)mg5uart_tx_empty_cd.name; 
     666  mg5uart_tx_ready_cd.handle          =  (void *)mg5uart_tx_ready_cd.name;
     667  mg5uart_rx_ready_cd.handle          =  (void *)mg5uart_rx_ready_cd.name;
     668
     669 
     670  BSP_install_rtems_irq_handler( &mg5uart_rx_frame_error_cd );
     671  BSP_install_rtems_irq_handler( &mg5uart_rx_overrun_error_cd );
     672  BSP_install_rtems_irq_handler( &mg5uart_tx_empty_cd );
     673  BSP_install_rtems_irq_handler( &mg5uart_tx_ready_cd );
     674  BSP_install_rtems_irq_handler( &mg5uart_rx_ready_cd );
    619675
    620676  mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
    621677}
    622 
    623 
    624 
    625 
    626678
    627679/*
  • c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  MIPS Mongoose-V specific information
    3  *
    4  *  COPYRIGHT (c) 1989-2001.
     5 */
     6
     7/*
     8 *  COPYRIGHT (c) 1989-2012.
    59 *  On-Line Applications Research Corporation (OAR).
    610 *
     
    812 *  found in the file LICENSE in this distribution or at
    913 *  http://www.rtems.com/license/LICENSE.
    10  *
     14 * 
    1115 *  $Id$
    1216 */
     
    250254#define MONGOOSEV_BAUD_RATE    8
    251255
    252 /*
    253  *  Interrupt Vector Numbers
    254  *
    255  *  NOTE: IRQ INT5 is logical or of peripheral cause register
    256  *        per p. 5-22 of Mongoose-V manual.
    257  */
    258 
    259 #define MONGOOSEV_IRQ_INT0                    MIPS_INTERRUPT_BASE+0
    260 #define MONGOOSEV_IRQ_TIMER1                  MONGOOSEV_IRQ_INT0
    261 #define MONGOOSEV_IRQ_INT1                    MIPS_INTERRUPT_BASE+1
    262 #define MONGOOSEV_IRQ_TIMER2                  MONGOOSEV_IRQ_INT1
    263 #define MONGOOSEV_IRQ_INT2                    MIPS_INTERRUPT_BASE+2
    264 #define MONGOOSEV_IRQ_INT3                    MIPS_INTERRUPT_BASE+3
    265 #define MONGOOSEV_IRQ_FPU                     MONGOOSEV_IRQ_INT3
    266 
    267 #define MONGOOSEV_IRQ_INT4                    MIPS_INTERRUPT_BASE+4
    268 
    269 /* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */
    270 #define MONGOOSEV_IRQ_PERIPHERAL_BASE         MIPS_INTERRUPT_BASE+5
    271 #define MONGOOSEV_IRQ_XINT0                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 0
    272 #define MONGOOSEV_IRQ_XINT1                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 1
    273 #define MONGOOSEV_IRQ_XINT2                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 2
    274 #define MONGOOSEV_IRQ_XINT3                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 3
    275 #define MONGOOSEV_IRQ_XINT4                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 4
    276 #define MONGOOSEV_IRQ_XINT5                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 5
    277 #define MONGOOSEV_IRQ_XINT6                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 6
    278 #define MONGOOSEV_IRQ_XINT7                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 7
    279 #define MONGOOSEV_IRQ_XINT8                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 8
    280 #define MONGOOSEV_IRQ_XINT9                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 9
    281 #define MONGOOSEV_IRQ_RESERVED_BIT_10        MONGOOSEV_IRQ_PERIPHERAL_BASE + 10
    282 #define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR   MONGOOSEV_IRQ_PERIPHERAL_BASE + 11
    283 #define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12
    284 #define MONGOOSEV_IRQ_UART0_TX_EMPTY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 13
    285 #define MONGOOSEV_IRQ_UART0_TX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 14
    286 #define MONGOOSEV_IRQ_UART0_RX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 15
    287 #define MONGOOSEV_IRQ_RESERVED_BIT_16        MONGOOSEV_IRQ_PERIPHERAL_BASE + 16
    288 #define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR   MONGOOSEV_IRQ_PERIPHERAL_BASE + 17
    289 #define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18
    290 #define MONGOOSEV_IRQ_UART1_TX_EMPTY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 19
    291 #define MONGOOSEV_IRQ_UART1_TX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 20
    292 #define MONGOOSEV_IRQ_UART1_RX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 21
    293 #define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION  MONGOOSEV_IRQ_PERIPHERAL_BASE + 22
    294 #define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23
    295 #define MONGOOSEV_IRQ_RESERVED_24            MONGOOSEV_IRQ_PERIPHERAL_BASE + 24
    296 #define MONGOOSEV_IRQ_RESERVED_25            MONGOOSEV_IRQ_PERIPHERAL_BASE + 25
    297 #define MONGOOSEV_IRQ_RESERVED_26            MONGOOSEV_IRQ_PERIPHERAL_BASE + 26
    298 #define MONGOOSEV_IRQ_RESERVED_27            MONGOOSEV_IRQ_PERIPHERAL_BASE + 27
    299 #define MONGOOSEV_IRQ_RESERVED_28            MONGOOSEV_IRQ_PERIPHERAL_BASE + 28
    300 #define MONGOOSEV_IRQ_RESERVED_29            MONGOOSEV_IRQ_PERIPHERAL_BASE + 29
    301 #define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR    MONGOOSEV_IRQ_PERIPHERAL_BASE + 30
    302 #define MONGOOSEV_IRQ_CORRECTABLE_ERROR      MONGOOSEV_IRQ_PERIPHERAL_BASE + 31
    303 
    304 #define MONGOOSEV_IRQ_SOFTWARE_1             MIPS_INTERRUPT_BASE+37
    305 #define MONGOOSEV_IRQ_SOFTWARE_2             MIPS_INTERRUPT_BASE+38
    306 #define MONGOOSEV_MAXIMUM_VECTORS            MIPS_INTERRUPT_BASE+39
    307 
    308256
    309257/*
  • c/src/lib/libcpu/mips/rm52xx/include/rm5231.h

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 *  MIPS RM5231 specific information
     5 */
     6
    17/*
    2  *  MIPS RM5231 specific information
     8 *  COPYRIGHT (c) 1989-2012.
     9 *  On-Line Applications Research Corporation (OAR).
    310 *
    4  *  rm5231.h,v 1.0 2004/06/23 19:54:22
     11 *  The license and distribution terms for this file may be
     12 *  found in the file LICENSE in this distribution or at
     13 *  http://www.rtems.com/license/LICENSE.
     14 *
     15 *  $Id$
    516 */
    617
     
    819#define __RM5231_h
    920
    10 #define RM5231_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+8
    11 
    1221#endif
  • c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 */
     5
    16/*
     7 *  COPYRIGHT (c) 1989-2012.
     8 *  On-Line Applications Research Corporation (OAR).
     9 *
     10 *  The license and distribution terms for this file may be
     11 *  found in the file LICENSE in this distribution or at
     12 *  http://www.rtems.com/license/LICENSE.
     13 *
    214 *  $Id$
    315 */
     
    719
    820extern void mips_install_isr_entries( void );
     21extern void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
    922
    1023#if __mips == 1
  • c/src/lib/libcpu/mips/tx39/include/tx3904.h

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  MIPS Tx3904 specific information
    35 *
    46 *  NOTE: This is far from complete.  --joel (13 Dec 2000)
     7 */
     8
     9/*
     10 *  COPYRIGHT (c) 1989-2012.
     11 *  On-Line Applications Research Corporation (OAR).
    512 *
     13 *  The license and distribution terms for this file may be
     14 *  found in the file LICENSE in this distribution or at
     15 *  http://www.rtems.com/license/LICENSE.
     16 *
    617 *  $Id$
    718 */
     
    3445  *((volatile uint32_t*)((_base) + (_register))) = (_value)
    3546
    36 /*
    37  *  Interrupt Vector Numbers
    38  *
    39  *  NOTE: Numbers 0-15 directly map to levels on the IRC.
    40  *        Number 16 is "1xxxx" per p. 164 of the TX3904 manual.
    41  */
    42 
    43 #define TX3904_IRQ_INT1        MIPS_INTERRUPT_BASE+0
    44 #define TX3904_IRQ_INT2        MIPS_INTERRUPT_BASE+1
    45 #define TX3904_IRQ_INT3        MIPS_INTERRUPT_BASE+2
    46 #define TX3904_IRQ_INT4        MIPS_INTERRUPT_BASE+3
    47 #define TX3904_IRQ_INT5        MIPS_INTERRUPT_BASE+4
    48 #define TX3904_IRQ_INT6        MIPS_INTERRUPT_BASE+5
    49 #define TX3904_IRQ_INT7        MIPS_INTERRUPT_BASE+6
    50 #define TX3904_IRQ_DMAC3       MIPS_INTERRUPT_BASE+7
    51 #define TX3904_IRQ_DMAC2       MIPS_INTERRUPT_BASE+8
    52 #define TX3904_IRQ_DMAC1       MIPS_INTERRUPT_BASE+9
    53 #define TX3904_IRQ_DMAC0       MIPS_INTERRUPT_BASE+10
    54 #define TX3904_IRQ_SIO0        MIPS_INTERRUPT_BASE+11
    55 #define TX3904_IRQ_SIO1        MIPS_INTERRUPT_BASE+12
    56 #define TX3904_IRQ_TMR0        MIPS_INTERRUPT_BASE+13
    57 #define TX3904_IRQ_TMR1        MIPS_INTERRUPT_BASE+14
    58 #define TX3904_IRQ_TMR2        MIPS_INTERRUPT_BASE+15
    59 #define TX3904_IRQ_INT0        MIPS_INTERRUPT_BASE+16
    60 #define TX3904_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+17
    61 #define TX3904_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+18
    62 #define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19
    63 
    6447#endif
  • c/src/lib/libcpu/mips/tx49/include/tx4925.h

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 *  MIPS Tx4925 specific information
     5 */
     6
    17/*
    2  *  MIPS Tx4925 specific information
     8 *  COPYRIGHT (c) 1989-2012.
     9 *  On-Line Applications Research Corporation (OAR).
    310 *
    4  *  tx4925.h,v 1.0 2004/06/23 19:54:22
     11 *  The license and distribution terms for this file may be
     12 *  found in the file LICENSE in this distribution or at
     13 *  http://www.rtems.com/license/LICENSE.
     14 *
     15 *  $Id$
    516 */
    617
     
    96107  *((volatile uint32_t *)((_base) + (_register))) = (_value)
    97108
    98 /*
    99  *  Interrupt Vector Numbers
    100  *
    101  */
    102 #define TX4925_IRQ_RSV1        MIPS_INTERRUPT_BASE+0
    103 #define TX4925_IRQ_WTE         MIPS_INTERRUPT_BASE+1
    104 #define TX4925_IRQ_INT0        MIPS_INTERRUPT_BASE+2
    105 #define TX4925_IRQ_INT1        MIPS_INTERRUPT_BASE+3
    106 #define TX4925_IRQ_INT2        MIPS_INTERRUPT_BASE+4
    107 #define TX4925_IRQ_INT3        MIPS_INTERRUPT_BASE+5
    108 #define TX4925_IRQ_INT4        MIPS_INTERRUPT_BASE+6
    109 #define TX4925_IRQ_INT5        MIPS_INTERRUPT_BASE+7
    110 #define TX4925_IRQ_INT6        MIPS_INTERRUPT_BASE+8
    111 #define TX4925_IRQ_INT7        MIPS_INTERRUPT_BASE+9
    112 #define TX4925_IRQ_RSV2        MIPS_INTERRUPT_BASE+10
    113 #define TX4925_IRQ_NAND        MIPS_INTERRUPT_BASE+11
    114 #define TX4925_IRQ_SIO0        MIPS_INTERRUPT_BASE+12
    115 #define TX4925_IRQ_SIO1        MIPS_INTERRUPT_BASE+13
    116 #define TX4925_IRQ_DMAC0       MIPS_INTERRUPT_BASE+14
    117 #define TX4925_IRQ_DMAC1       MIPS_INTERRUPT_BASE+15
    118 #define TX4925_IRQ_DMAC2       MIPS_INTERRUPT_BASE+16
    119 #define TX4925_IRQ_DMAC3       MIPS_INTERRUPT_BASE+17
    120 #define TX4925_IRQ_IRC         MIPS_INTERRUPT_BASE+18
    121 #define TX4925_IRQ_PDMAC       MIPS_INTERRUPT_BASE+19
    122 #define TX4925_IRQ_PCIC        MIPS_INTERRUPT_BASE+20
    123 #define TX4925_IRQ_TMR0        MIPS_INTERRUPT_BASE+21
    124 #define TX4925_IRQ_TMR1        MIPS_INTERRUPT_BASE+22
    125 #define TX4925_IRQ_TMR2        MIPS_INTERRUPT_BASE+23
    126 #define TX4925_IRQ_SPI         MIPS_INTERRUPT_BASE+24
    127 #define TX4925_IRQ_RTC         MIPS_INTERRUPT_BASE+25
    128 #define TX4925_IRQ_ACLC        MIPS_INTERRUPT_BASE+26
    129 #define TX4925_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27
    130 #define TX4925_IRQ_CHI         MIPS_INTERRUPT_BASE+28
    131 #define TX4925_IRQ_PCIERR      MIPS_INTERRUPT_BASE+29
    132 #define TX4925_IRQ_PCIPME      MIPS_INTERRUPT_BASE+30
    133 #define TX4925_IRQ_RSV3        MIPS_INTERRUPT_BASE+31
    134 
    135 #define TX4925_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32
    136 #define TX4925_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33
    137 #define TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
    138 
    139109#endif
  • c/src/lib/libcpu/mips/tx49/include/tx4938.h

    reb6362dc r0c0181d  
     1/**
     2 *  @file
     3 * 
     4 *  MIPS Tx4938 specific information
     5 */
     6
    17/*
    2  *  MIPS Tx4938 specific information
     8 *  COPYRIGHT (c) 1989-2012.
     9 *  On-Line Applications Research Corporation (OAR).
    310 *
    4  *  tx4938.h,v 1.0 2004/06/23 19:54:22
     11 *  The license and distribution terms for this file may be
     12 *  found in the file LICENSE in this distribution or at
     13 *  http://www.rtems.com/license/LICENSE.
     14 *
     15 *  $Id$
    516 */
    617
     
    111122  *((volatile uint32_t *)((_base) + (_register))) = (_value)
    112123
    113 /*
    114  *  Interrupt Vector Numbers
    115  *
    116  */
    117 #define TX4938_IRQ_ECC         MIPS_INTERRUPT_BASE+0
    118 #define TX4938_IRQ_WTE         MIPS_INTERRUPT_BASE+1
    119 #define TX4938_IRQ_INT0        MIPS_INTERRUPT_BASE+2
    120 #define TX4938_IRQ_INT1        MIPS_INTERRUPT_BASE+3
    121 #define TX4938_IRQ_INT2        MIPS_INTERRUPT_BASE+4
    122 #define TX4938_IRQ_INT3        MIPS_INTERRUPT_BASE+5
    123 #define TX4938_IRQ_INT4        MIPS_INTERRUPT_BASE+6
    124 #define TX4938_IRQ_INT5        MIPS_INTERRUPT_BASE+7
    125 #define TX4938_IRQ_SIO0        MIPS_INTERRUPT_BASE+8
    126 #define TX4938_IRQ_SIO1        MIPS_INTERRUPT_BASE+9
    127 #define TX4938_IRQ_DMAC00      MIPS_INTERRUPT_BASE+10
    128 #define TX4938_IRQ_DMAC01      MIPS_INTERRUPT_BASE+11
    129 #define TX4938_IRQ_DMAC02      MIPS_INTERRUPT_BASE+12
    130 #define TX4938_IRQ_DMAC03      MIPS_INTERRUPT_BASE+13
    131 #define TX4938_IRQ_IRC         MIPS_INTERRUPT_BASE+14
    132 #define TX4938_IRQ_PDMAC       MIPS_INTERRUPT_BASE+15
    133 #define TX4938_IRQ_PCIC        MIPS_INTERRUPT_BASE+16
    134 #define TX4938_IRQ_TMR0        MIPS_INTERRUPT_BASE+17
    135 #define TX4938_IRQ_TMR1        MIPS_INTERRUPT_BASE+18
    136 #define TX4938_IRQ_TMR2        MIPS_INTERRUPT_BASE+19
    137 #define TX4938_IRQ_RSV1        MIPS_INTERRUPT_BASE+20
    138 #define TX4938_IRQ_NDFMC       MIPS_INTERRUPT_BASE+21
    139 #define TX4938_IRQ_PCIERR      MIPS_INTERRUPT_BASE+22
    140 #define TX4938_IRQ_PCIPMC      MIPS_INTERRUPT_BASE+23
    141 #define TX4938_IRQ_ACLC        MIPS_INTERRUPT_BASE+24
    142 #define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+25
    143 #define TX4938_IRQ_PCIC1NT     MIPS_INTERRUPT_BASE+26
    144 #define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27
    145 #define TX4938_IRQ_DMAC10      MIPS_INTERRUPT_BASE+28
    146 #define TX4938_IRQ_DMAC11      MIPS_INTERRUPT_BASE+29
    147 #define TX4938_IRQ_DMAC12      MIPS_INTERRUPT_BASE+30
    148 #define TX4938_IRQ_DMAC13      MIPS_INTERRUPT_BASE+31
    149 
    150 #define TX4938_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32
    151 #define TX4938_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33
    152 #define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
    153 
    154124/************************************************************************
    155125 *      TX49 Register field encodings
  • cpukit/score/cpu/mips/ChangeLog

    reb6362dc r0c0181d  
     12012-03-07      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        * rtems/score/cpu.h: In order to handle a issue in the
     4        compilation of printk all tasks should be defined as
     5        floating point for the MIPS processor.
     6
     72012-02-23      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     8
     9        PR 1993/bsps
     10        * cpu.c, rtems/score/cpu.h:
     11        Mips conversion to PIC IRQ model.
     12
    1132011-12-09      Jennifer Averett
    214
  • cpukit/score/cpu/mips/cpu.c

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  Mips CPU Dependent Source
    35 *
     
    1820 *    added the new interrupt vectoring support in libcpu and
    1921 *    tried to better support the various interrupt controllers.
    20  *
     22 */
     23
     24/*
    2125 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
    2226 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
     
    3337 *             suitability of this software for any purpose.
    3438 *
    35  *  COPYRIGHT (c) 1989-2001.
     39 *  COPYRIGHT (c) 1989-2012.
    3640 *  On-Line Applications Research Corporation (OAR).
    3741 *
     
    3943 *  found in the file LICENSE in this distribution or at
    4044 *  http://www.rtems.com/license/LICENSE.
    41  *
     45 * 
    4246 *  $Id$
    4347 */
     
    171175}
    172176
    173 
    174 
    175 /*
    176  *  _CPU_ISR_install_raw_handler
    177  *
    178  *  Input parameters:
    179  *    vector      - interrupt vector number
    180  *    old_handler - former ISR for this vector number
    181  *    new_handler - replacement ISR for this vector number
    182  *
    183  *  Output parameters:  NONE
    184  *
    185  */
    186 
    187 void _CPU_ISR_install_raw_handler(
    188   uint32_t    vector,
    189   proc_ptr    new_handler,
    190   proc_ptr   *old_handler
    191 )
    192 {
    193   /*
    194    *  This is where we install the interrupt handler into the "raw" interrupt
    195    *  table used by the CPU to dispatch interrupt handlers.
    196    *
    197    *  Because all interrupts are vectored through the same exception handler
    198    *  this is not necessary on this port.
    199    */
    200 }
    201 
    202 /*
    203  *  _CPU_ISR_install_vector
    204  *
    205  *  This kernel routine installs the RTEMS handler for the
    206  *  specified vector.
    207  *
    208  *  Input parameters:
    209  *    vector      - interrupt vector number
    210  *    old_handler - former ISR for this vector number
    211  *    new_handler - replacement ISR for this vector number
    212  *
    213  *  Output parameters:  NONE
    214  *
    215  */
    216 
    217 void _CPU_ISR_install_vector(
    218   uint32_t    vector,
    219   proc_ptr    new_handler,
    220   proc_ptr   *old_handler
    221 )
    222 {
    223    *old_handler = _ISR_Vector_table[ vector ];
    224 
    225    /*
    226     *  If the interrupt vector table is a table of pointer to isr entry
    227     *  points, then we need to install the appropriate RTEMS interrupt
    228     *  handler for this vector number.
    229     */
    230 
    231    _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
    232 
    233    /*
    234     *  We put the actual user ISR address in '_ISR_vector_table'.  This will
    235     *  be used by the _ISR_Handler so the user gets control.
    236     */
    237 
    238     _ISR_Vector_table[ vector ] = new_handler;
    239 }
    240 
    241177/*
    242178 *  _CPU_Install_interrupt_stack
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    reb6362dc r0c0181d  
    1 /*
     1/**
     2 *  @file
     3 * 
    24 *  Mips CPU Dependent Header File
    35 *
     
    1315 *    tried to better support the various interrupt controllers.
    1416 *
     17 */
     18
     19/*
    1520 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
    1621 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
     
    2732 *      of this software for any purpose.
    2833 *
    29  *  COPYRIGHT (c) 1989-2006.
     34 *  COPYRIGHT (c) 1989-2012.
    3035 *  On-Line Applications Research Corporation (OAR).
    3136 *
     
    3338 *  found in the file LICENSE in this distribution or at
    3439 *  http://www.rtems.com/license/LICENSE.
    35  *
     40 * 
    3641 *  $Id$
    3742 */
     
    125130 *  XXX document implementation including references if appropriate
    126131 */
    127 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
     132#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
    128133
    129134/*
     
    202207 *
    203208 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
    204  */
    205 
    206 #define CPU_ALL_TASKS_ARE_FP    FALSE
     209 *
     210 *  Mips Note: It appears the GCC can implicitly generate FPU
     211 *  and Altivec instructions when you least expect them.  So make
     212 *  all tasks floating point.
     213 */
     214
     215#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
    207216
    208217/*
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