Changeset 0bd3f7e in rtems


Ignore:
Timestamp:
Jul 28, 2011, 5:33:07 PM (9 years ago)
Author:
Jennifer Averett <Jennifer.Averett@…>
Branches:
4.11, 5, master
Children:
b4fdfc6
Parents:
38ccd6fa
Message:

2011-07-28 Jennifer Averett <Jennifer.Averett@…>

PR 1801

  • shared/irq_asm.S: Modifications to synch the sparc with the smp working tree.
Location:
c/src/lib/libbsp/sparc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/ChangeLog

    r38ccd6fa r0bd3f7e  
     12011-07-28      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        PR 1801
     4        * shared/irq_asm.S: Modifications to synch the sparc with the smp
     5        working tree.
     6
    172011-06-28      Joel Sherrill <joel.sherrill@oarcorp.com>
    28                Jennifer Averett <jennifer.averett@OARcorp.com>
  • c/src/lib/libbsp/sparc/shared/irq_asm.S

    r38ccd6fa r0bd3f7e  
    163163
    164164        mov     %sp, %o1                       ! 2nd arg to ISR Handler
    165 
    166         /*
    167          *  Increment ISR nest level and Thread dispatch disable level.
    168          *
    169          *  Register usage for this section:
    170          *
    171          *    l4 = _Thread_Dispatch_disable_level pointer
    172          *    l5 = _ISR_Nest_level pointer
    173          *    l6 = _Thread_Dispatch_disable_level value
    174          *    l7 = _ISR_Nest_level value
    175          *
    176          *  NOTE: It is assumed that l4 - l7 will be preserved until the ISR
    177          *        nest and thread dispatch disable levels are unnested.
    178          */
    179 
    180         sethi    %hi(SYM(_Thread_Dispatch_disable_level)), %l4
    181         ld       [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
    182 
    183         PUBLIC(_ISR_PER_CPU)
    184 SYM(_ISR_PER_CPU):
    185 #if defined(RTEMS_SMP)
    186         sethi    %hi(_Per_CPU_Information_p), %l5
    187         add      %l5, %lo(_Per_CPU_Information_p), %l5
    188     #if BSP_LEON3_SMP
    189         /* LEON3 SMP support */
    190         rd      %asr17, %l7
    191         srl     %l7, 28, %l7    /* CPU number is upper 4 bits so shift */
    192         sll     %l7, 2, %l7     /* l7 = offset */
    193         add     %l5, %l7, %l5
    194     #endif
    195         ld       [%l5], %l5     /* l5 = pointer to per CPU */
    196         nop
    197         nop
    198 #else
    199         sethi    %hi(_Per_CPU_Information), %l5
    200         add      %l5, %lo(_Per_CPU_Information), %l5
    201 #endif
    202         ld       [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
    203 
    204         add      %l6, 1, %l6
    205         st       %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
    206 
    207         add      %l7, 1, %l7
    208         st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
    209 
    210         /*
    211          *  If ISR nest level was zero (now 1), then switch stack.
    212          */
    213 
    214         mov      %sp, %fp
    215         subcc    %l7, 1, %l7             ! outermost interrupt handler?
    216         bnz      dont_switch_stacks      ! No, then do not switch stacks
    217 
    218         ld       [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
    219 
    220 dont_switch_stacks:
    221         /*
    222          *  Make sure we have a place on the stack for the window overflow
    223          *  trap handler to write into.  At this point it is safe to
    224          *  enable traps again.
    225          */
    226 
    227         sub      %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
    228165
    229166        /*
     
    317254dont_fix_pil2:
    318255
     256        PUBLIC(_ISR_PER_CPU)
     257SYM(_ISR_PER_CPU):
     258
     259#if defined(RTEMS_SMP)
     260        sethi    %hi(_Per_CPU_Information_p), %l5
     261        add      %l5, %lo(_Per_CPU_Information_p), %l5
     262    #if BSP_LEON3_SMP
     263        /* LEON3 SMP support */
     264        rd      %asr17, %l7
     265        srl     %l7, 28, %l7    /* CPU number is upper 4 bits so shift */
     266        sll     %l7, 2, %l7     /* l7 = offset */
     267        add     %l5, %l7, %l5
     268    #endif
     269        ld       [%l5], %l5     /* l5 = pointer to per CPU */
     270        nop
     271        nop
     272
     273        /*
     274         *  On multi-core system, we need to use SMP safe versions
     275         *  of ISR and Thread Dispatch critical sections.
     276         *
     277         *  _ISR_SMP_Enter returns the interrupt nest level.  If we are
     278         *  outermost interrupt, then we need to switch stacks.
     279         */
     280        mov      %sp, %fp
     281        call    SYM(_ISR_SMP_Enter), 0
     282        nop                             ! delay slot
     283        cmp     %o0, 0
     284#else
     285        /*
     286         *  On single core system, we can directly use variables.
     287         *
     288         *  Increment ISR nest level and Thread dispatch disable level.
     289         *
     290         *  Register usage for this section:
     291         *
     292         *    l4 = _Thread_Dispatch_disable_level pointer
     293         *    l5 = _ISR_Nest_level pointer
     294         *    l6 = _Thread_Dispatch_disable_level value
     295         *    l7 = _ISR_Nest_level value
     296         *
     297         *  NOTE: It is assumed that l4 - l7 will be preserved until the ISR
     298         *        nest and thread dispatch disable levels are unnested.
     299         */
     300        sethi    %hi(SYM(_Thread_Dispatch_disable_level)), %l4
     301        ld       [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
     302
     303        sethi    %hi(_Per_CPU_Information), %l5
     304        add      %l5, %lo(_Per_CPU_Information), %l5
     305
     306        ld       [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
     307
     308        add      %l6, 1, %l6
     309        st       %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
     310
     311        add      %l7, 1, %l7
     312        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
     313
     314        /*
     315         *  If ISR nest level was zero (now 1), then switch stack.
     316         */
     317        mov      %sp, %fp
     318        subcc    %l7, 1, %l7             ! outermost interrupt handler?
     319#endif
     320
     321        /*
     322         *  Do we need to switch to the interrupt stack?
     323         */
     324        bnz      dont_switch_stacks      ! No, then do not switch stacks
     325        ld       [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
     326
     327dont_switch_stacks:
     328        /*
     329         *  Make sure we have a place on the stack for the window overflow
     330         *  trap handler to write into.  At this point it is safe to
     331         *  enable traps again.
     332         */
     333
     334        sub      %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
     335
    319336        /*
    320337         *  Vector to user's handler.
     
    337354        nop                             ! delay slot
    338355
     356#if defined(RTEMS_SMP)
     357        call    SYM(_ISR_SMP_Exit), 0
     358        nop                             ! delay slot
     359        cmp     %o0, 0
     360        bz      simple_return
     361#else
     362        !sethi    %hi(SYM(_Thread_Dispatch_disable_level)), %l4
     363        !ld       [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
     364        !ld       [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
     365#endif
     366
    339367        /*
    340368         *  Redisable traps so we can finish up the interrupt processing.
     
    347375        nop; nop; nop
    348376
     377#if !defined(RTEMS_SMP)
    349378        /*
    350379         *  Decrement ISR nest level and Thread dispatch disable level.
     
    390419        orcc     %l5, %g0, %g0   ! Is thread switch necessary?
    391420        bz       simple_return   ! No, then return
    392 
     421#endif
    393422        /*
    394423         *  Invoke interrupt dispatcher.
Note: See TracChangeset for help on using the changeset viewer.