Index: doc/supplements/mips64orion/ChangeLog
===================================================================
--- doc/supplements/mips64orion/ChangeLog	(revision 52c5689ecd46a4601aea1104c1c860f8ca48ec05)
+++ doc/supplements/mips64orion/ChangeLog	(revision 0b93b9785601ef8da6b7ae501c55033230d6589c)
@@ -1,2 +1,6 @@
+2002-07-30	Joel Sherrill <joel@OARcorp.com>
+
+	* intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
+
 2002-03-27	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
 
Index: doc/supplements/mips64orion/intr_NOTIMES.t
===================================================================
--- doc/supplements/mips64orion/intr_NOTIMES.t	(revision 52c5689ecd46a4601aea1104c1c860f8ca48ec05)
+++ doc/supplements/mips64orion/intr_NOTIMES.t	(revision 0b93b9785601ef8da6b7ae501c55033230d6589c)
@@ -168,5 +168,5 @@
 to insure that interrupts are disabled for less than 
 RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a 
-RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz XXX with 
+RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz processor with 
 zero wait states.  These numbers will vary based the 
 number of wait states and processor speed present on the target board.
@@ -190,5 +190,5 @@
 process, RTEMS will install its interrupt stack.
 
-The XXX port of RTEMS supports a software managed
+The mips64orion port of RTEMS supports a software managed
 dedicated interrupt stack on those CPU models which do not
 support a separate interrupt stack in hardware.
Index: doc/supplements/mips64orion/timeBSP.t
===================================================================
--- doc/supplements/mips64orion/timeBSP.t	(revision 52c5689ecd46a4601aea1104c1c860f8ca48ec05)
+++ doc/supplements/mips64orion/timeBSP.t	(revision 0b93b9785601ef8da6b7ae501c55033230d6589c)
@@ -28,5 +28,6 @@
 All times reported except for the maximum period
 interrupts are disabled by RTEMS were measured using a Motorola
-BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a 20Mhz board with one wait
+BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz board with one wait
 state dynamic memory and a XXX numeric coprocessor.  The
 Zilog 8036 countdown timer on this board was used to measure
@@ -42,5 +43,6 @@
 assumed.  The total CPU cycles executed with interrupts
 disabled, including the instructions to disable and enable
-interrupts, was divided by 20 to simulate a 20Mhz XXX.  It
+interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz processor.  It
 should be noted that the worst case instruction times for the
 XXX assume that the internal cache is disabled and that no
@@ -53,5 +55,5 @@
 microseconds including the instructions
 which disable and re-enable interrupts.  The time required for
-the XXX to vector an interrupt and for the RTEMS entry
+the mips64orion to vector an interrupt and for the RTEMS entry
 overhead before invoking the user's interrupt handler are a
 total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK 
@@ -59,5 +61,6 @@
 interrupt latency of less than 
 RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK 
-microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
+microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz.  [NOTE:  The maximum period with interrupts
 disabled was last determined for Release 
 RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
@@ -66,5 +69,6 @@
 interrupts disabled within RTEMS is hand-timed and based upon
 worst case (i.e. CPU cache disabled and no instruction overlap)
-times for a 20Mhz XXX.  The interrupt vector and entry
+times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz processor.  The interrupt vector and entry
 overhead time was generated on an BSP_FOR_TIMES benchmark platform
 using the Multiprocessing Communications registers to generate
Index: doc/supplements/sh/ChangeLog
===================================================================
--- doc/supplements/sh/ChangeLog	(revision 52c5689ecd46a4601aea1104c1c860f8ca48ec05)
+++ doc/supplements/sh/ChangeLog	(revision 0b93b9785601ef8da6b7ae501c55033230d6589c)
@@ -1,2 +1,6 @@
+2002-07-30	Joel Sherrill <joel@OARcorp.com>
+
+	* intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
+
 2002-03-27	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
 
Index: doc/supplements/sh/intr_NOTIMES.t
===================================================================
--- doc/supplements/sh/intr_NOTIMES.t	(revision 52c5689ecd46a4601aea1104c1c860f8ca48ec05)
+++ doc/supplements/sh/intr_NOTIMES.t	(revision 0b93b9785601ef8da6b7ae501c55033230d6589c)
@@ -24,5 +24,5 @@
 details of interrupt processing, it is important to understand
 how the RTEMS interrupt manager is mapped onto the processor's
-unique architecture. Discussed in this chapter are the XXX's
+unique architecture. Discussed in this chapter are the SH's
 interrupt response and control mechanisms as they pertain to
 RTEMS.
@@ -31,10 +31,10 @@
 
 Depending on whether or not the particular CPU
-supports a separate interrupt stack, the XXX family has two
+supports a separate interrupt stack, the SH family has two
 different interrupt handling models.
 
 @subsection Models Without Separate Interrupt Stacks
 
-Upon receipt of an interrupt the XXX family
+Upon receipt of an interrupt the SH family
 members without separate interrupt stacks automatically perform
 the following actions:
@@ -46,5 +46,5 @@
 @subsection Models With Separate Interrupt Stacks
 
-Upon receipt of an interrupt the XXX family
+Upon receipt of an interrupt the SH family
 members with separate interrupt stacks automatically perform the
 following actions:
Index: doc/supplements/sh/timeBSP.t
===================================================================
--- doc/supplements/sh/timeBSP.t	(revision 52c5689ecd46a4601aea1104c1c860f8ca48ec05)
+++ doc/supplements/sh/timeBSP.t	(revision 0b93b9785601ef8da6b7ae501c55033230d6589c)
@@ -16,5 +16,5 @@
 @section Introduction
 
-The timing data for the XXX version of RTEMS is
+The timing data for the SH version of RTEMS is
 provided along with the target dependent aspects concerning the
 gathering of the timing data.  The hardware platform used to
@@ -22,5 +22,5 @@
 understanding of each directive time provided.  Also, provided
 is a description of the interrupt latency and the context switch
-times as they pertain to the XXX version of RTEMS.
+times as they pertain to the SH version of RTEMS.
 
 @section Hardware Platform
@@ -28,5 +28,6 @@
 All times reported except for the maximum period
 interrupts are disabled by RTEMS were measured using a Motorola
-BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a 20Mhz board with one wait
+BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz board with one wait
 state dynamic memory and a XXX numeric coprocessor.  The
 Zilog 8036 countdown timer on this board was used to measure
@@ -42,7 +43,8 @@
 assumed.  The total CPU cycles executed with interrupts
 disabled, including the instructions to disable and enable
-interrupts, was divided by 20 to simulate a 20Mhz XXX.  It
+interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz processor.  It
 should be noted that the worst case instruction times for the
-XXX assume that the internal cache is disabled and that no
+processor assume that the internal cache is disabled and that no
 instructions overlap.
 
@@ -53,5 +55,5 @@
 microseconds including the instructions
 which disable and re-enable interrupts.  The time required for
-the XXX to vector an interrupt and for the RTEMS entry
+the processor to vector an interrupt and for the RTEMS entry
 overhead before invoking the user's interrupt handler are a
 total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK 
@@ -59,5 +61,6 @@
 interrupt latency of less than 
 RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK 
-microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
+microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz.  [NOTE:  The maximum period with interrupts
 disabled was last determined for Release 
 RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
@@ -66,5 +69,6 @@
 interrupts disabled within RTEMS is hand-timed and based upon
 worst case (i.e. CPU cache disabled and no instruction overlap)
-times for a 20Mhz XXX.  The interrupt vector and entry
+times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz processor.  The interrupt vector and entry
 overhead time was generated on an BSP_FOR_TIMES benchmark platform
 using the Multiprocessing Communications registers to generate
Index: doc/supplements/template/ChangeLog
===================================================================
--- doc/supplements/template/ChangeLog	(revision 52c5689ecd46a4601aea1104c1c860f8ca48ec05)
+++ doc/supplements/template/ChangeLog	(revision 0b93b9785601ef8da6b7ae501c55033230d6589c)
@@ -1,2 +1,6 @@
+2002-07-30	Joel Sherrill <joel@OARcorp.com>
+
+	* intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
+
 2002-03-27	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
 
Index: doc/supplements/template/intr_NOTIMES.t
===================================================================
--- doc/supplements/template/intr_NOTIMES.t	(revision 52c5689ecd46a4601aea1104c1c860f8ca48ec05)
+++ doc/supplements/template/intr_NOTIMES.t	(revision 0b93b9785601ef8da6b7ae501c55033230d6589c)
@@ -24,5 +24,5 @@
 details of interrupt processing, it is important to understand
 how the RTEMS interrupt manager is mapped onto the processor's
-unique architecture. Discussed in this chapter are the XXX's
+unique architecture. Discussed in this chapter are the processor's
 interrupt response and control mechanisms as they pertain to
 RTEMS.
Index: doc/supplements/template/timeBSP.t
===================================================================
--- doc/supplements/template/timeBSP.t	(revision 52c5689ecd46a4601aea1104c1c860f8ca48ec05)
+++ doc/supplements/template/timeBSP.t	(revision 0b93b9785601ef8da6b7ae501c55033230d6589c)
@@ -28,10 +28,11 @@
 All times reported except for the maximum period
 interrupts are disabled by RTEMS were measured using a Motorola
-MYBSP CPU board.  The MYBSP is a 20Mhz board with one wait
+MYBSP CPU board.  The MYBSP is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz board with one wait
 state dynamic memory and a XXX numeric coprocessor.  The
 Zilog 8036 countdown timer on this board was used to measure
 elapsed time with a one-half microsecond resolution.  All
 sources of hardware interrupts were disabled, although the
-interrupt level of the XXX allows all interrupts.
+interrupt level of the processor allows all interrupts.
 
 The maximum period interrupts are disabled was
@@ -42,7 +43,8 @@
 assumed.  The total CPU cycles executed with interrupts
 disabled, including the instructions to disable and enable
-interrupts, was divided by 20 to simulate a 20Mhz XXX.  It
+interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz processor.  It
 should be noted that the worst case instruction times for the
-XXX assume that the internal cache is disabled and that no
+processor assume that the internal cache is disabled and that no
 instructions overlap.
 
@@ -53,5 +55,5 @@
 microseconds including the instructions
 which disable and re-enable interrupts.  The time required for
-the XXX to vector an interrupt and for the RTEMS entry
+the processor to vector an interrupt and for the RTEMS entry
 overhead before invoking the user's interrupt handler are a
 total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK 
@@ -59,5 +61,6 @@
 interrupt latency of less than 
 RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK 
-microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
+microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz.  [NOTE:  The maximum period with interrupts
 disabled was last determined for Release 
 RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
@@ -66,5 +69,6 @@
 interrupts disabled within RTEMS is hand-timed and based upon
 worst case (i.e. CPU cache disabled and no instruction overlap)
-times for a 20Mhz XXX.  The interrupt vector and entry
+times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz processor.  The interrupt vector and entry
 overhead time was generated on an MYBSP benchmark platform
 using the Multiprocessing Communications registers to generate
