Changeset 0b93b978 in rtems


Ignore:
Timestamp:
Jul 31, 2002, 12:17:12 AM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
bf2f674
Parents:
52c5689e
Message:

2002-07-30 Joel Sherrill <joel@…>

  • intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
Location:
doc/supplements
Files:
9 edited

Legend:

Unmodified
Added
Removed
  • doc/supplements/mips64orion/ChangeLog

    r52c5689e r0b93b978  
     12002-07-30      Joel Sherrill <joel@OARcorp.com>
     2
     3        * intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
     4
    152002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    26
  • doc/supplements/mips64orion/intr_NOTIMES.t

    r52c5689e r0b93b978  
    168168to insure that interrupts are disabled for less than
    169169RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a
    170 RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz XXX with
     170RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz processor with
    171171zero wait states.  These numbers will vary based the
    172172number of wait states and processor speed present on the target board.
     
    190190process, RTEMS will install its interrupt stack.
    191191
    192 The XXX port of RTEMS supports a software managed
     192The mips64orion port of RTEMS supports a software managed
    193193dedicated interrupt stack on those CPU models which do not
    194194support a separate interrupt stack in hardware.
  • doc/supplements/mips64orion/timeBSP.t

    r52c5689e r0b93b978  
    2828All times reported except for the maximum period
    2929interrupts are disabled by RTEMS were measured using a Motorola
    30 BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a 20Mhz board with one wait
     30BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     31Mhz board with one wait
    3132state dynamic memory and a XXX numeric coprocessor.  The
    3233Zilog 8036 countdown timer on this board was used to measure
     
    4243assumed.  The total CPU cycles executed with interrupts
    4344disabled, including the instructions to disable and enable
    44 interrupts, was divided by 20 to simulate a 20Mhz XXX.  It
     45interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     46Mhz processor.  It
    4547should be noted that the worst case instruction times for the
    4648XXX assume that the internal cache is disabled and that no
     
    5355microseconds including the instructions
    5456which disable and re-enable interrupts.  The time required for
    55 the XXX to vector an interrupt and for the RTEMS entry
     57the mips64orion to vector an interrupt and for the RTEMS entry
    5658overhead before invoking the user's interrupt handler are a
    5759total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
     
    5961interrupt latency of less than
    6062RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
    61 microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
     63microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     64Mhz.  [NOTE:  The maximum period with interrupts
    6265disabled was last determined for Release
    6366RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
     
    6669interrupts disabled within RTEMS is hand-timed and based upon
    6770worst case (i.e. CPU cache disabled and no instruction overlap)
    68 times for a 20Mhz XXX.  The interrupt vector and entry
     71times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     72Mhz processor.  The interrupt vector and entry
    6973overhead time was generated on an BSP_FOR_TIMES benchmark platform
    7074using the Multiprocessing Communications registers to generate
  • doc/supplements/sh/ChangeLog

    r52c5689e r0b93b978  
     12002-07-30      Joel Sherrill <joel@OARcorp.com>
     2
     3        * intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
     4
    152002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    26
  • doc/supplements/sh/intr_NOTIMES.t

    r52c5689e r0b93b978  
    2424details of interrupt processing, it is important to understand
    2525how the RTEMS interrupt manager is mapped onto the processor's
    26 unique architecture. Discussed in this chapter are the XXX's
     26unique architecture. Discussed in this chapter are the SH's
    2727interrupt response and control mechanisms as they pertain to
    2828RTEMS.
     
    3131
    3232Depending on whether or not the particular CPU
    33 supports a separate interrupt stack, the XXX family has two
     33supports a separate interrupt stack, the SH family has two
    3434different interrupt handling models.
    3535
    3636@subsection Models Without Separate Interrupt Stacks
    3737
    38 Upon receipt of an interrupt the XXX family
     38Upon receipt of an interrupt the SH family
    3939members without separate interrupt stacks automatically perform
    4040the following actions:
     
    4646@subsection Models With Separate Interrupt Stacks
    4747
    48 Upon receipt of an interrupt the XXX family
     48Upon receipt of an interrupt the SH family
    4949members with separate interrupt stacks automatically perform the
    5050following actions:
  • doc/supplements/sh/timeBSP.t

    r52c5689e r0b93b978  
    1616@section Introduction
    1717
    18 The timing data for the XXX version of RTEMS is
     18The timing data for the SH version of RTEMS is
    1919provided along with the target dependent aspects concerning the
    2020gathering of the timing data.  The hardware platform used to
     
    2222understanding of each directive time provided.  Also, provided
    2323is a description of the interrupt latency and the context switch
    24 times as they pertain to the XXX version of RTEMS.
     24times as they pertain to the SH version of RTEMS.
    2525
    2626@section Hardware Platform
     
    2828All times reported except for the maximum period
    2929interrupts are disabled by RTEMS were measured using a Motorola
    30 BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a 20Mhz board with one wait
     30BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     31Mhz board with one wait
    3132state dynamic memory and a XXX numeric coprocessor.  The
    3233Zilog 8036 countdown timer on this board was used to measure
     
    4243assumed.  The total CPU cycles executed with interrupts
    4344disabled, including the instructions to disable and enable
    44 interrupts, was divided by 20 to simulate a 20Mhz XXX.  It
     45interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     46Mhz processor.  It
    4547should be noted that the worst case instruction times for the
    46 XXX assume that the internal cache is disabled and that no
     48processor assume that the internal cache is disabled and that no
    4749instructions overlap.
    4850
     
    5355microseconds including the instructions
    5456which disable and re-enable interrupts.  The time required for
    55 the XXX to vector an interrupt and for the RTEMS entry
     57the processor to vector an interrupt and for the RTEMS entry
    5658overhead before invoking the user's interrupt handler are a
    5759total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
     
    5961interrupt latency of less than
    6062RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
    61 microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
     63microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     64Mhz.  [NOTE:  The maximum period with interrupts
    6265disabled was last determined for Release
    6366RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
     
    6669interrupts disabled within RTEMS is hand-timed and based upon
    6770worst case (i.e. CPU cache disabled and no instruction overlap)
    68 times for a 20Mhz XXX.  The interrupt vector and entry
     71times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     72Mhz processor.  The interrupt vector and entry
    6973overhead time was generated on an BSP_FOR_TIMES benchmark platform
    7074using the Multiprocessing Communications registers to generate
  • doc/supplements/template/ChangeLog

    r52c5689e r0b93b978  
     12002-07-30      Joel Sherrill <joel@OARcorp.com>
     2
     3        * intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
     4
    152002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    26
  • doc/supplements/template/intr_NOTIMES.t

    r52c5689e r0b93b978  
    2424details of interrupt processing, it is important to understand
    2525how the RTEMS interrupt manager is mapped onto the processor's
    26 unique architecture. Discussed in this chapter are the XXX's
     26unique architecture. Discussed in this chapter are the processor's
    2727interrupt response and control mechanisms as they pertain to
    2828RTEMS.
  • doc/supplements/template/timeBSP.t

    r52c5689e r0b93b978  
    2828All times reported except for the maximum period
    2929interrupts are disabled by RTEMS were measured using a Motorola
    30 MYBSP CPU board.  The MYBSP is a 20Mhz board with one wait
     30MYBSP CPU board.  The MYBSP is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     31Mhz board with one wait
    3132state dynamic memory and a XXX numeric coprocessor.  The
    3233Zilog 8036 countdown timer on this board was used to measure
    3334elapsed time with a one-half microsecond resolution.  All
    3435sources of hardware interrupts were disabled, although the
    35 interrupt level of the XXX allows all interrupts.
     36interrupt level of the processor allows all interrupts.
    3637
    3738The maximum period interrupts are disabled was
     
    4243assumed.  The total CPU cycles executed with interrupts
    4344disabled, including the instructions to disable and enable
    44 interrupts, was divided by 20 to simulate a 20Mhz XXX.  It
     45interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     46Mhz processor.  It
    4547should be noted that the worst case instruction times for the
    46 XXX assume that the internal cache is disabled and that no
     48processor assume that the internal cache is disabled and that no
    4749instructions overlap.
    4850
     
    5355microseconds including the instructions
    5456which disable and re-enable interrupts.  The time required for
    55 the XXX to vector an interrupt and for the RTEMS entry
     57the processor to vector an interrupt and for the RTEMS entry
    5658overhead before invoking the user's interrupt handler are a
    5759total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
     
    5961interrupt latency of less than
    6062RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
    61 microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
     63microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     64Mhz.  [NOTE:  The maximum period with interrupts
    6265disabled was last determined for Release
    6366RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
     
    6669interrupts disabled within RTEMS is hand-timed and based upon
    6770worst case (i.e. CPU cache disabled and no instruction overlap)
    68 times for a 20Mhz XXX.  The interrupt vector and entry
     71times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     72Mhz processor.  The interrupt vector and entry
    6973overhead time was generated on an MYBSP benchmark platform
    7074using the Multiprocessing Communications registers to generate
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