Changeset 0b74e10f in rtems


Ignore:
Timestamp:
Feb 17, 2014, 10:57:19 AM (6 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
9fcd1b35
Parents:
b0553f47
git-author:
Ralf Kirchner <ralf.kirchner@…> (02/17/14 10:57:19)
git-committer:
Sebastian Huber <sebastian.huber@…> (03/13/14 15:10:54)
Message:

bsp/arm: Add SCU errata handling for L2C-310 cache

Location:
c/src/lib/libbsp/arm/shared/include
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h

    rb0553f47 r0b74e10f  
    5959#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */
    6060#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
    61   uint32_t reserved_10[12];
     61  uint32_t reserved_09[8];
     62  uint32_t diagn_ctrl;
     63#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0)
     64  uint32_t reserved_10[3];
    6265  uint32_t fltstart;
    6366  uint32_t fltend;
  • c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h

    rb0553f47 r0b74e10f  
    3131#include <bsp/start.h>
    3232#include <bsp/arm-a9mpcore-regs.h>
     33#include <bsp/arm-errata.h>
    3334
    3435#ifdef __cplusplus
     
    8081}
    8182
     83BSP_START_TEXT_SECTION static void inline
     84arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu)
     85{
     86#ifdef RTEMS_SMP
     87  if (arm_errata_is_applicable_processor_errata_764369()) {
     88    scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE;
     89  }
     90#endif
     91}
     92
     93BSP_START_TEXT_SECTION static inline
     94arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu)
     95{
     96  arm_a9mpcore_start_errata_764369_handler(scu);
     97  scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
     98}
     99
    82100BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void)
    83101{
     102  volatile a9mpcore_scu *scu =
     103    (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
     104  uint32_t cpu_id;
     105
     106  arm_a9mpcore_start_scu_enable(scu);
     107
    84108#ifdef RTEMS_SMP
    85   volatile a9mpcore_scu *scu = (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
    86   uint32_t cpu_id;
    87   uint32_t actlr;
    88 
    89   /* Enable Snoop Control Unit (SCU) */
    90   scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
    91 
    92109  /* Enable cache coherency support for this processor */
    93   actlr = arm_cp15_get_auxiliary_control();
    94   actlr |= ARM_CORTEX_A9_ACTL_SMP;
    95   arm_cp15_set_auxiliary_control(actlr);
     110  {
     111    uint32_t actlr = arm_cp15_get_auxiliary_control();
     112    actlr |= ARM_CORTEX_A9_ACTL_SMP;
     113    arm_cp15_set_auxiliary_control(actlr);
     114  }
     115#endif
    96116
    97117  cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
     
    99119  arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf);
    100120
     121#ifdef RTEMS_SMP
    101122  if (cpu_id != 0) {
    102123    arm_a9mpcore_start_set_vector_base();
     
    117138
    118139      /* FIXME: Sharing the translation table between processors is brittle */
    119       arm_cp15_set_translation_table_base((uint32_t *) bsp_translation_table_base);
     140      arm_cp15_set_translation_table_base(
     141        (uint32_t *) bsp_translation_table_base
     142      );
    120143
    121144      ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
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