Changeset 0b1cb769 in rtems


Ignore:
Timestamp:
Sep 11, 2006, 9:43:36 PM (13 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
1883c87
Parents:
c6fda81
Message:

2006-09-11 Joel Sherrill <joel@…>

  • startup/init5282.c: Convert C++ style comments to C style.
Location:
c/src/lib/libbsp/m68k/av5282
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/av5282/ChangeLog

    rc6fda81 r0b1cb769  
     12006-09-11      Joel Sherrill <joel@OARcorp.com>
     2
     3        * startup/init5282.c: Convert C++ style comments to C style.
     4
    152006-02-08      Joel Sherrill <joel@OARcorp.com>
    26
  • c/src/lib/libbsp/m68k/av5282/startup/init5282.c

    rc6fda81 r0b1cb769  
    2121    int temp = 0;
    2222   
    23     //Setup the GPIO Registers
     23    /*Setup the GPIO Registers */
    2424    MCF5282_GPIO_PBCDPAR = 0x80;
    2525    MCF5282_GPIO_PEPAR = 0x5100;
     
    3232    MCF5282_GPTA_GPTPORT = 0x4;
    3333   
    34     //Setup the Chip Selects so CS0 is flash
     34    /*Setup the Chip Selects so CS0 is flash */
    3535    MCF5282_CS0_CSAR =(0xff800000 & 0xffff0000)>>16;
    3636    MCF5282_CS0_CSMR = 0x007f0001;
    3737    MCF5282_CS0_CSCR =(((0xf)&0x0F)<<10)|(1<<8)|(0x80);
    3838
    39         //Setup the SDRAM
     39        /*Setup the SDRAM  */
    4040        for(x=0; x<20000; x++)
    4141        {
     
    4949                temp +=1;
    5050        }
    51         // set ip ( bit 3 ) in dacr
     51        /* set ip ( bit 3 ) in dacr */
    5252        MCF5282_SDRAMC_DACR0 |= (0x00000008) ;
    53         // init precharge
     53        /* init precharge */
    5454        *((short *)MM_SDRAM_BASE) = 0;
    55         // set RE in dacr
     55        /* set RE in dacr */
    5656        MCF5282_SDRAMC_DACR0 |= (0x00008000); 
    57         // wait
     57        /* wait */
    5858        for(x=0; x<20000; x++)
    5959        {
    6060                temp +=1;
    6161        }
    62         // issue IMRS
     62        /* issue IMRS */
    6363        MCF5282_SDRAMC_DACR0 |= (0x00000040);
    6464        *((short *)MM_SDRAM_BASE) = 0x0000;
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