Changeset 0a7a30d in rtems


Ignore:
Timestamp:
Mar 12, 2018, 7:53:09 PM (14 months ago)
Author:
Joel Sherrill <joel@…>
Branches:
master
Children:
478dc89
Parents:
c0443b4
git-author:
Joel Sherrill <joel@…> (03/12/18 19:53:09)
git-committer:
Joel Sherrill <joel@…> (03/13/18 14:55:23)
Message:

Add PowerPC paravirtualization support

Cannot read or write MSR when executing in user mode. This
is used when RTEMS_PARAVIRT is defined.

Provide alternate methods to disable/enable interrupts

Closes #3306.

Files:
1 added
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/new-exceptions/cpu.c

    rc0443b4 r0a7a30d  
    6565{
    6666  ppc_context *the_ppc_context;
    67   uint32_t   msr_value;
     67  uint32_t   msr_value = 0;
    6868  uintptr_t  sp;
    6969  uintptr_t  stack_alignment;
     
    7676  sp = (uintptr_t) memset((void *) sp, 0, PPC_MINIMUM_STACK_FRAME_SIZE);
    7777
     78  the_ppc_context = ppc_get_context( the_context );
     79
     80#if !defined(PPC_DISABLE_MSR_ACCESS)
    7881  _CPU_MSR_GET( msr_value );
    79 
    80   the_ppc_context = ppc_get_context( the_context );
    8182
    8283  /*
     
    114115#ifdef PPC_MULTILIB_ALTIVEC
    115116  msr_value |= MSR_VE;
     117#endif
     118#endif  /* END PPC_DISABLE_MSR_ACCESS */
    116119
     120#ifdef PPC_MULTILIB_ALTIVEC
    117121  the_ppc_context->vrsave = 0;
    118122#endif
  • c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S

    rc0443b4 r0a7a30d  
    129129 * available. Therefore, we must explicitely enable it here!
    130130 */
     131#if !defined(PPC_DISABLE_MSR_ACCESS)
    131132        mfmsr   r4
    132133        andi.   r5,r4,MSR_FP
     
    135136        mtmsr   r5
    136137        isync
     138#endif  /* END PPC_DISABLE_MSR_ACCESS */
     139
    1371401:
    138141        lwz     r3, 0(r3)
     
    171174        mffs    f2
    172175        STF     f2, FP_FPSCR(r3)
     176#if !defined(PPC_DISABLE_MSR_ACCESS)
    173177        bne     1f
    174178        mtmsr   r4
    175179        isync
     180#endif  /* END PPC_DISABLE_MSR_ACCESS */
     181
    1761821:
    177183        blr
     
    197203 * available. Therefore, we must explicitely enable it here!
    198204 */
     205#if !defined(PPC_DISABLE_MSR_ACCESS)
    199206        mfmsr   r4
    200207        andi.   r5,r4,MSR_FP
     
    203210        mtmsr   r5
    204211        isync
     212#endif  /* END PPC_DISABLE_MSR_ACCESS */
     213
    2052141:
    206215        LDF     f2, FP_FPSCR(r3)
     
    239248        LDF     f31, FP_31(r3)
    240249        bne     1f
     250#if !defined(PPC_DISABLE_MSR_ACCESS)
    241251        mtmsr   r4
    242252        isync
     253#endif  /* END PPC_DISABLE_MSR_ACCESS */
     254
    2432551:
    244256        blr
     
    267279
    268280        GET_SELF_CPU_CONTROL    r12
     281#if !defined(PPC_DISABLE_MSR_ACCESS)
    269282        mfmsr   r6
     283#endif  /* END PPC_DISABLE_MSR_ACCESS */
    270284        mfcr    r7
    271285        mflr    r8
     
    530544        mtlr    r8
    531545        mtcr    r7
     546#if !defined(PPC_DISABLE_MSR_ACCESS)
    532547        mtmsr   r6
     548#endif  /* END PPC_DISABLE_MSR_ACCESS */
    533549        stw     r11, PER_CPU_ISR_DISPATCH_DISABLE(r12)
    534550
  • cpukit/score/cpu/powerpc/headers.am

    rc0443b4 r0a7a30d  
    1818include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h
    1919include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h
     20include_rtems_score_HEADERS += include/rtems/score/paravirt.h
    2021include_rtems_score_HEADERS += include/rtems/score/powerpc.h
  • cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h

    rc0443b4 r0a7a30d  
    673673 * A one bit means that this bit should be cleared.
    674674 */
     675#if !defined(PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE)
    675676extern char _PPC_INTERRUPT_DISABLE_MASK[];
    676677
     
    735736  );
    736737}
     738#else
     739uint32_t ppc_interrupt_get_disable_mask( void );
     740uint32_t ppc_interrupt_disable( void );
     741void ppc_interrupt_enable( uint32_t level );
     742void ppc_interrupt_flash( uint32_t level );
     743#endif /* PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE */
    737744
    738745#define _CPU_ISR_Disable( _isr_cookie ) \
  • cpukit/score/cpu/powerpc/include/rtems/score/cpu.h

    rc0443b4 r0a7a30d  
    3737
    3838#include <rtems/score/basedefs.h>
     39#if defined(RTEMS_PARAVIRT)
     40#include <rtems/score/paravirt.h>
     41#endif
    3942#include <rtems/score/powerpc.h>
    4043#include <rtems/powerpc/registers.h>
     
    655658}
    656659
     660#if !defined(PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE)
     661
    657662static inline uint32_t   _CPU_ISR_Get_level( void )
    658663{
     
    675680  _CPU_MSR_SET(msr);
    676681}
     682#else
     683/* disable, enable, etc. are in registers.h */
     684uint32_t ppc_get_interrupt_level( void );
     685void ppc_set_interrupt_level( uint32_t level );
     686#define _CPU_ISR_Get_level( _new_level ) ppc_get_interrupt_level()
     687#define _CPU_ISR_Set_level( _new_level ) ppc_set_interrupt_level(_new_level)
     688#endif
    677689
    678690#endif /* ASM */
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