Changeset 0a75a4aa in rtems


Ignore:
Timestamp:
Nov 26, 2018, 1:04:59 PM (5 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
c1864a0a
Parents:
6378978
git-author:
Sebastian Huber <sebastian.huber@…> (11/26/18 13:04:59)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/26/18 13:09:43)
Message:

Remove rtems_cache_*_processor_set() functions

The following rtems_cache_*_processor_set() cache manager API functions
are exotic, complex, very hard to use correctly, not used in the RTEMS
code base, and apparently unused by applications.

Close #3622.

Files:
3 edited

Legend:

Unmodified
Added
Removed
  • bsps/shared/cache/cacheimpl.h

    r6378978 r0a75a4aa  
    5050#endif
    5151
    52 #if defined(RTEMS_SMP)
    53 
    54 #include <rtems/score/smpimpl.h>
    55 
    56 typedef struct {
    57   const void *addr;
    58   size_t size;
    59 } smp_cache_area;
    60 
    61 #if defined(CPU_DATA_CACHE_ALIGNMENT)
    62 
    63 static void smp_cache_data_flush(void *arg)
    64 {
    65   smp_cache_area *area = arg;
    66 
    67   rtems_cache_flush_multiple_data_lines(area->addr, area->size);
    68 }
    69 
    70 static void smp_cache_data_inv(void *arg)
    71 {
    72   smp_cache_area *area = arg;
    73 
    74   rtems_cache_invalidate_multiple_data_lines(area->addr, area->size);
    75 }
    76 
    77 static void smp_cache_data_flush_all(void *arg)
    78 {
    79   rtems_cache_flush_entire_data();
    80 }
    81 
    82 static void smp_cache_data_inv_all(void *arg)
    83 {
    84   rtems_cache_invalidate_entire_data();
    85 }
    86 
    87 #endif /* defined(CPU_DATA_CACHE_ALIGNMENT) */
    88 
    89 void
    90 rtems_cache_flush_multiple_data_lines_processor_set(
    91   const void *addr,
    92   size_t size,
    93   const size_t setsize,
    94   const cpu_set_t *set
    95 )
    96 {
    97 #if defined(CPU_DATA_CACHE_ALIGNMENT)
    98   smp_cache_area area = { addr, size };
    99 
    100   _SMP_Multicast_action( setsize, set, smp_cache_data_flush, &area );
    101 #endif
    102 }
    103 
    104 void
    105 rtems_cache_invalidate_multiple_data_lines_processor_set(
    106   const void *addr,
    107   size_t size,
    108   const size_t setsize,
    109   const cpu_set_t *set
    110 )
    111 {
    112 #if defined(CPU_DATA_CACHE_ALIGNMENT)
    113   smp_cache_area area = { addr, size };
    114 
    115   _SMP_Multicast_action( setsize, set, smp_cache_data_inv, &area );
    116 #endif
    117 }
    118 
    119 void
    120 rtems_cache_flush_entire_data_processor_set(
    121   const size_t setsize,
    122   const cpu_set_t *set
    123 )
    124 {
    125 #if defined(CPU_DATA_CACHE_ALIGNMENT)
    126   _SMP_Multicast_action( setsize, set, smp_cache_data_flush_all, NULL );
    127 #endif
    128 }
    129 
    130 void
    131 rtems_cache_invalidate_entire_data_processor_set(
    132   const size_t setsize,
    133   const cpu_set_t *set
    134 )
    135 {
    136 #if defined(CPU_DATA_CACHE_ALIGNMENT)
    137   _SMP_Multicast_action( setsize, set, smp_cache_data_inv_all, NULL );
    138 #endif
    139 }
    140 
    141 #endif /* defined(RTEMS_SMP) */
    142 
    14352/*
    14453 * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE
  • cpukit/include/rtems/rtems/cache.h

    r6378978 r0a75a4aa  
    285285);
    286286
    287 #if defined( RTEMS_SMP )
    288 
    289 /**
    290  * @brief Flushes multiple data cache lines for a set of processors
    291  *
    292  * Dirty cache lines covering the area are transferred to memory.
    293  * Depending on the cache implementation this may mark the lines as invalid.
    294  *
    295  * This operation should not be called from interrupt context.
    296  *
    297  * @param[in] addr The start address of the area to flush.
    298  * @param[in] size The size in bytes of the area to flush.
    299  * @param[in] setsize The size of the processor set.
    300  * @param[in] set The target processor set.
    301  */
    302 void rtems_cache_flush_multiple_data_lines_processor_set(
    303   const void *addr,
    304   size_t size,
    305   const size_t setsize,
    306   const cpu_set_t *set
    307 );
    308 
    309 /**
    310  * @brief Invalidates multiple data cache lines for a set of processors
    311  *
    312  * The cache lines covering the area are marked as invalid.  A later read
    313  * access in the area will load the data from memory.
    314  *
    315  * In case the area is not aligned on cache line boundaries, then this
    316  * operation may destroy unrelated data.
    317  *
    318  * This operation should not be called from interrupt context.
    319  *
    320  * @param[in] addr The start address of the area to invalidate.
    321  * @param[in] size The size in bytes of the area to invalidate.
    322  * @param[in] setsize The size of the processor set.
    323  * @param[in] set The target processor set.
    324  */
    325 void rtems_cache_invalidate_multiple_data_lines_processor_set(
    326   const void *addr,
    327   size_t size,
    328   const size_t setsize,
    329   const cpu_set_t *set
    330 );
    331 
    332 /**
    333  * @brief Flushes the entire data cache for a set of processors
    334  *
    335  * This operation should not be called from interrupt context.
    336  *
    337  * @see rtems_cache_flush_multiple_data_lines().
    338  *
    339  * @param[in] setsize The size of the processor set.
    340  * @param[in] set The target processor set.
    341  */
    342 void rtems_cache_flush_entire_data_processor_set(
    343   const size_t setsize,
    344   const cpu_set_t *set
    345 );
    346 
    347 /**
    348  * @brief Invalidates the entire cache for a set of processors
    349  *
    350  * This function is responsible for performing a data cache
    351  * invalidate. It invalidates the entire cache for a set of
    352  * processors.
    353  *
    354  * This operation should not be called from interrupt context.
    355  *
    356  * @param[in] setsize The size of the processor set.
    357  * @param[in] set The target processor set.
    358  */
    359 void rtems_cache_invalidate_entire_data_processor_set(
    360   const size_t setsize,
    361   const cpu_set_t *set
    362 );
    363 
    364 #endif
    365 
    366287/**@}*/
    367288
  • testsuites/smptests/smpcache01/init.c

    r6378978 r0a75a4aa  
    2424const char rtems_test_name[] = "SMPCACHE 1";
    2525
    26 CPU_STRUCTURE_ALIGNMENT static int data_to_flush[1024];
    27 
    2826#define CPU_COUNT 32
    2927
     
    5553typedef void ( *test_case )(
    5654  size_t set_size,
    57   const cpu_set_t *cpu_set,
    58   SMP_barrier_State *bs
     55  const cpu_set_t *cpu_set
    5956);
    6057
    61 static void test_cache_flush_multiple_data_lines(
    62   size_t set_size,
    63   const cpu_set_t *cpu_set,
    64   SMP_barrier_State *bs
    65 )
    66 {
    67   rtems_cache_flush_multiple_data_lines_processor_set( &data_to_flush,
    68       sizeof(data_to_flush), set_size, cpu_set );
    69 }
    70 
    71 static void test_cache_invalidate_multiple_data_lines(
    72   size_t set_size,
    73   const cpu_set_t *cpu_set,
    74   SMP_barrier_State *bs
    75 )
    76 {
    77   rtems_cache_invalidate_multiple_data_lines_processor_set( &data_to_flush,
    78       sizeof(data_to_flush), set_size, cpu_set );
    79 }
    80 
    81 static void test_cache_flush_entire_data(
    82   size_t set_size,
    83   const cpu_set_t *cpu_set,
    84   SMP_barrier_State *bs
    85 )
    86 {
    87   rtems_cache_flush_entire_data_processor_set( set_size, cpu_set );
    88 }
    89 
    9058static void test_cache_invalidate_entire_instruction(
    9159  size_t set_size,
    92   const cpu_set_t *cpu_set,
    93   SMP_barrier_State *bs
     60  const cpu_set_t *cpu_set
    9461)
    9562{
     
    9966static void test_cache_invalidate_multiple_instruction_lines(
    10067  size_t set_size,
    101   const cpu_set_t *cpu_set,
    102   SMP_barrier_State *bs
     68  const cpu_set_t *cpu_set
    10369)
    10470{
     
    12793static void broadcast_test_body(
    12894  size_t set_size,
    129   const cpu_set_t *cpu_set,
    130   SMP_barrier_State *bs
     95  const cpu_set_t *cpu_set
    13196)
    13297{
     
    142107
    143108static test_case test_cases[] = {
    144   test_cache_flush_multiple_data_lines,
    145   test_cache_invalidate_multiple_data_lines,
    146   test_cache_flush_entire_data,
    147109  test_cache_invalidate_entire_instruction,
    148110  test_cache_invalidate_multiple_instruction_lines,
     
    159121  for (i = 0; i < RTEMS_ARRAY_SIZE( test_cases ); ++i) {
    160122    barrier( bs );
    161     ( *test_cases[ i ] )( set_size, cpu_set, bs );
     123    ( *test_cases[ i ] )( set_size, cpu_set );
    162124    barrier( bs );
    163125  }
     
    178140    _ISR_Local_disable( isr_level );
    179141    barrier( bs );
    180     ( *test_cases[ i ] )( set_size, cpu_set, bs );
     142    ( *test_cases[ i ] )( set_size, cpu_set );
    181143    _ISR_Local_enable( isr_level );
    182144    barrier( bs );
     
    198160    cpu_self = _Thread_Dispatch_disable();
    199161    barrier( bs );
    200     ( *test_cases[ i ] )( set_size, cpu_set, bs );
     162    ( *test_cases[ i ] )( set_size, cpu_set );
    201163    barrier( bs );
    202164    _Thread_Dispatch_enable( cpu_self );
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