Changeset 098755b3 in rtems


Ignore:
Timestamp:
Aug 5, 2002, 7:19:45 PM (17 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
8b58477
Parents:
bf1f6531
Message:

2002-08-05 Chris Ziomkowski <chris@…>

  • asm.h, cpu.c, cpu_asm.c, rtems/score/cpu.h, rtems/score/or32.h, rtems/score/types.h: Merged from OpenCores? CVS repository.
Location:
cpukit/score/cpu/or32
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/or32/ChangeLog

    rbf1f6531 r098755b3  
     12002-08-05      Chris Ziomkowski <chris@asics.ws>
     2
     3        * asm.h, cpu.c, cpu_asm.c, rtems/score/cpu.h, rtems/score/or32.h,
     4        rtems/score/types.h: Merged from OpenCores CVS repository.
     5
    162002-07-26      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    27
  • cpukit/score/cpu/or32/asm.h

    rbf1f6531 r098755b3  
    2424 */
    2525
    26 #ifndef __OR32_ASM_h
    27 #define __OR32_ASM_h
     26#ifndef __OR1K_ASM_h
     27#define __OR1K_ASM_h
    2828
    2929/*
     
    3434#define ASM
    3535#endif
    36 #include <rtems/score/cpuopts.h>
    37 #include <rtems/score/or32.h>
     36#include <rtems/score/targopts.h>
     37#include <rtems/score/or1k.h>
    3838
    3939/*
     
    9393 */
    9494
    95 #define PUBLIC(sym) .globl SYM (sym)
    96 #define EXTERN(sym) .globl SYM (sym)
     95#define PUBLIC(sym) .global SYM (sym)
     96#define EXTERN(sym) .global SYM (sym)
    9797
    9898#endif
  • cpukit/score/cpu/or32/cpu.c

    rbf1f6531 r098755b3  
    11/*
    2  *  XXX CPU Dependent Source
     2 *  Opencore Or1k CPU Dependent Source
    33 *
    44 *
     
    1010 *  http://www.OARcorp.com/rtems/license.html.
    1111 *
    12  *  $Id$
     12 *  This file adapted from no_bsp board library of the RTEMS distribution.
     13 *  The body has been modified for the Bender Or1k implementation by
     14 *  Chris Ziomkowski. <chris@asics.ws>
    1315 */
    1416
     
    2527 *    thread_dispatch - address of disptaching routine
    2628 *
    27  *  OR32 Specific Information:
    28  *
    29  *  XXX document implementation including references if appropriate
    3029 */
    3130
     
    3332void _CPU_Initialize(
    3433  rtems_cpu_table  *cpu_table,
    35   void      (*thread_dispatch)      /* ignored on this CPU */
     34  void      (*thread_dispatch) 
    3635)
    3736{
     
    6564 *  _CPU_ISR_Get_level
    6665 *
    67  *  OR32 Specific Information:
     66 *  or1k Specific Information:
    6867 *
    69  *  XXX document implementation including references if appropriate
     68 *  There are only 2 interrupt levels for the or1k architecture.
     69 *  Either interrupts are enabled or disabled. They are considered
     70 *  enabled if both exceptions are enabled (SR_EXR) and interrupts
     71 *  are enabled (SR_EIR). If either of these conditions are not
     72 *  met, interrupts are disabled, and a level of 1 is returned.
    7073 */
    71  
    72 unsigned32 _CPU_ISR_Get_level( void )
     74
     75inline unsigned32 _CPU_ISR_Get_level( void )
    7376{
    74   /*
    75    *  This routine returns the current interrupt level.
    76    */
    77 
    78   return 0;
     77  register unsigned32 sr;
     78  asm("l.mfspr %0,r0,0x17" : "=r" (sr));
     79  return !((sr & SR_EXR) && (sr & SR_EIR));
    7980}
    8081
     
    8384 *  _CPU_ISR_install_raw_handler
    8485 *
    85  *  OR32 Specific Information:
     86 *  or1k Specific Information:
    8687 *
    87  *  XXX document implementation including references if appropriate
     88 *  As a general rule the following is done for interrupts:
     89 * 
     90 *  For normal exceptions, exceptions are immediately reenabled
     91 *  by setting the SR_EXR bit. For interrupt exceptions, the
     92 *  SR_EIR bit is first cleared, and then exceptions are reenabled.
    8893 */
    8994 
     
    9499)
    95100{
    96   /*
    97    *  This is where we install the interrupt handler into the "raw" interrupt
    98    *  table used by the CPU to dispatch interrupt handlers.
    99    */
     101  register unsigned32 sr;
     102  register unsigned32 tmp;
     103  extern unsigned32 Or1k_Interrupt_Vectors[];
     104
     105  asm volatile ("l.mfspr %0,r0,0x11\n\t"
     106               "l.addi  %1,r0,-5\n\t"
     107               "l.and   %1,%1,%0\n\t": "=r" (sr) : "r" (tmp));
     108  *old_handler = *((proc_ptr*)&Or1k_Interrupt_Vectors[vector]);
     109  *((proc_ptr*)&Or1k_Interrupt_Vectors[vector]) = new_handler;
     110  asm volatile ("l.mtspr r0,%0,0x11\n\t":: "r" (sr));
    100111}
    101112
     
    115126 *
    116127 *
    117  *  OR32 Specific Information:
     128 *  NO_CPU Specific Information:
    118129 *
    119130 *  XXX document implementation including references if appropriate
     
    147158 *
    148159 *  _CPU_Install_interrupt_stack
     160 * 
     161 *  We don't use a separate interrupt stack.
    149162 *
    150  *  OR32 Specific Information:
    151  *
    152  *  XXX document implementation including references if appropriate
    153163 */
    154164
     
    173183 *     hook with caution.
    174184 *
    175  *  OR32 Specific Information:
    176  *
    177  *  XXX document implementation including references if appropriate
    178185 */
    179186
  • cpukit/score/cpu/or32/cpu_asm.c

    rbf1f6531 r098755b3  
    1414 *  http://www.OARcorp.com/rtems/license.html.
    1515 *
    16  *  $Id$
     16 *  This file adapted from no_bsp board library of the RTEMS distribution.
     17 *  The body has been modified for the Bender Or1k implementation by
     18 *  Chris Ziomkowski. <chris@asics.ws>
    1719 */
    1820
     
    3941 *  is to avoid writing assembly language.
    4042 *
    41  *  OR32 Specific Information:
    42  *
    43  *  XXX document implementation including references if appropriate
     43 *  or1k specific Information:
     44 *
     45 *  This implementation of RTEMS considers the concept of
     46 *  "fast context switching", as defined in the or1k architecture
     47 *  specification. Whether or not this makes a significant
     48 *  impact on speed is dubious, however it is not a significant
     49 *  impediment to include it. It probably wastes a few cycles on
     50 *  every floating point context switch.
     51 *
     52 *  This implementation will currently not work on a processor where
     53 *  the integer unit and floating point unit are not the same size. I
     54 *  am waiting on an architecture change to make this feasible. It
     55 *  should work fine on 64 bit architectures, except for the fact that
     56 *  the variables are declared as 32 bits. This shouldn't really make
     57 *  a difference, as the fact that they must be registers should force
     58 *  them into a 64 bit word anyway.
     59 *
     60 *  The decision as to whether to do 32 or 64 bit saves is performed
     61 *  at run time based on the configuration of the CPUCFGR register. This
     62 *  takes a performance hit of a few cycles, but this should be a very
     63 *  small percentage of the total number of cycles necessary to do the
     64 *  save, and doesn't require special code for 32 or 64 bit versions.
     65 *
     66 *  ADDITIONAL INFORMATION:
     67 *
     68 *  It has been unanimously agreed that floating point will not be
     69 *  included in the initial releases of the Or1k chips, and that
     70 *  significant changes to the floating point architecture may
     71 *  occur before any such release will ever be implemented. The code
     72 *  below is therefore never called and never used.
    4473 */
    4574
     
    4877)
    4978{
     79  register unsigned32 temp;
     80  register unsigned32 address = (unsigned32)(*fp_context_ptr);
     81  register unsigned32 xfer;
     82  register unsigned32 loop;
     83
     84  /* %0 is a temporary register which is used for several
     85     values throughout the code. %3 contains the address
     86     to save the context, and is modified during the course
     87     of the context save. %1 is a second dummy register
     88     which is used during transfer of the floating point
     89     value to memory. %2 is an end of loop marker which
     90     is compared against the pointer %3. */
     91
     92  asm volatile ("l.mfspr  %0,r0,0x02    \n\t"  /* CPUCFGR */
     93               "l.andi   %0,%0,0x380   \n\t"  /* OF32S or OV64S or OF64S */
     94               "l.sfnei  %0,0x0        \n\t"
     95               "l.bf     _L_nofps      \n\t"  /* exit if no floating point  */
     96               "l.sfeqi  %0,0x080      \n\t"  /* (DELAY) single precision?  */
     97               "l.mfspr  %0,r0,0x11    \n\t"  /* Load Status Register       */
     98               "l.srli   %0,%0,58      \n\t"  /* Move CID into low byte*32  */
     99               "l.bnf    _L_spfp_loops \n\t"  /* Branch on single precision */
     100               "l.addi   %2,%0,0x20    \n"    /* Terminating condition      */
     101               /**** Double Precision Floating Point Section ****/
     102               "_L_dpfp_loops:         \n\t"
     103               "l.mfspr  %1,%0,0x600   \n\t"  /* Load VFRx                  */
     104               "l.sd     0(%3),%1      \n\t"  /* Save VFRx                  */
     105               "l.addi   %0,%0,0x01    \n\t"  /* Increment counter          */
     106               "l.sfeq   %0,%2         \n\t"  /* Branch if incomplete       */
     107               "l.bf     _L_dpfp_loops \n\t"
     108               "l.addi   %3,%3,0x08    \n\t"  /* (DELAY) update pointer     */
     109               "l.bnf    _L_nofps      \n\t"  /* exit                       */
     110               "l.nop                  \n"
     111               /**** Single Precision Floating Point Section ****/
     112               "_L_spfp_loops:         \n\t"
     113               "l.mfspr  %1,%0,0x600   \n\t"  /* Load VFRx                  */
     114               "l.sw     0(%3),%1      \n\t"  /* Save VFRx                  */
     115               "l.addi   %0,%0,0x01    \n\t"  /* Increment counter          */
     116               "l.sfeq   %0,%2         \n\t"  /* Branch if incomplete       */
     117               "l.bf     _L_spfp_loops \n\t"
     118               "l.addi   %3,%3,0x04    \n"    /* (DELAY) update pointer     */
     119               "_L_nofps:              \n\t"  /* End of context save        */
     120                : "=&r" (temp), "=r" (xfer), "=&r" (loop), "+r" (address));
    50121}
    51122
     
    57128 *  from is changed then the pointer is modified by this routine.
    58129 *
    59  *  Sometimes a macro implementation of this is in cpu.h which dereferences
    60  *  the ** and a similarly named routine in this file is passed something
    61  *  like a (Context_Control_fp *).  The general rule on making this decision
    62  *  is to avoid writing assembly language.
    63  *
    64  *  OR32 Specific Information:
    65  *
    66  *  XXX document implementation including references if appropriate
     130 * 
    67131 */
    68132
     
    71135)
    72136{
     137  register unsigned32 temp;
     138  register unsigned32 address = (unsigned32)(*fp_context_ptr);
     139  register unsigned32 xfer;
     140  register unsigned32 loop;
     141
     142  /* The reverse of Context_save_fp */
     143  /* %0 is a temporary register which is used for several
     144     values throughout the code. %1 contains the address
     145     to save the context, and is modified during the course
     146     of the context save. %2 is a second dummy register
     147     which is used during transfer of the floating point
     148     value to memory. %3 is an end of loop marker which
     149     is compared against the pointer %1. */
     150
     151  asm volatile ("l.mfspr  %0,r0,0x02    \n\t"  /* CPUCFGR */
     152               "l.andi   %0,%0,0x380   \n\t"  /* OF32S or OV64S or OF64S */
     153               "l.sfnei  %0,0x0        \n\t"
     154               "l.bf     _L_nofpr      \n\t"  /* exit if no floating point  */
     155               "l.sfeqi  %0,0x080      \n\t"  /* (DELAY) single precision?  */
     156               "l.mfspr  %0,r0,0x11    \n\t"  /* Load Status Register       */
     157               "l.srli   %0,%0,58      \n\t"  /* Move CID into low byte*32  */
     158               "l.bnf    _L_spfp_loopr \n\t"  /* Branch on single precision */
     159               "l.addi   %3,%0,0x20    \n"    /* Terminating condition      */
     160               /**** Double Precision Floating Point Section ****/
     161               "_L_dpfp_loopr:          \n\t"
     162               "l.mfspr  %2,%0,0x600   \n\t"  /* Load VFRx                  */
     163               "l.sd     0(%1),%2      \n\t"  /* Save VFRx                  */
     164               "l.addi   %0,%0,0x01    \n\t"  /* Increment counter          */
     165               "l.sfeq   %0,%3         \n\t"  /* Branch if incomplete       */
     166               "l.bf     _L_dpfp_loopr \n\t"
     167               "l.addi   %1,%1,0x08    \n\t"  /* (DELAY) update pointer     */
     168               "l.bnf    _L_nofpr      \n\t"  /* exit                       */
     169               "l.nop                  \n"
     170               /**** Single Precision Floating Point Section ****/
     171               "_L_spfp_loopr:         \n\t"
     172               "l.mfspr  %2,%0,0x600   \n\t"  /* Load VFRx                  */
     173               "l.sw     0(%1),%2      \n\t"  /* Save VFRx                  */
     174               "l.addi   %0,%0,0x01    \n\t"  /* Increment counter          */
     175               "l.sfeq   %0,%3         \n\t"  /* Branch if incomplete       */
     176               "l.bf     _L_spfp_loopr \n\t"
     177               "l.addi   %1,%1,0x04    \n"    /* (DELAY) update pointer     */
     178               "_L_nofpr:              \n\t"  /* End of context save        */
     179               : "=&r" (temp), "+r" (address), "=r" (xfer), "=&r" (loop));
    73180}
    74181
     
    77184 *  This routine performs a normal non-FP context switch.
    78185 *
    79  *  OR32 Specific Information:
     186 *  NO_CPU Specific Information:
    80187 *
    81188 *  XXX document implementation including references if appropriate
     
    87194)
    88195{
     196  register unsigned32 temp1 = 0;
     197  register unsigned32 temp2 = 0;
     198
     199  /* This function is really tricky. When this function is called,
     200     we should save our state as we need it, and then grab the
     201     new state from the pointer. We then do a longjump to this
     202     code, replacing the current stack pointer with the new
     203     environment. This function never returns. Instead, at some
     204     later time, another person will call context switch with
     205     our pointer in the heir variable, and they will longjump
     206     to us. We will then continue. Let's see how this works... */
     207
     208  /* Technically, we could probably not worry about saving r3
     209     and r4, since these are parameters guaranteed to be saved
     210     by the calling function. We could also probably get away
     211     without saving r11, as that is filled in by the return
     212     statement. But as a first cut I'm in favor of just saving
     213     everything.... */
     214
     215  /* We could be more efficient and use compile time directives
     216     for 32 or 64 bit, but this will allow the code to run on
     217     everything without modification. Feel free to comment the
     218     relevant sections out if you don't need it. */
     219
     220  /* We should probably write this whole routine in assembly
     221     so that we can have seperate entry points for self restore
     222     or context switch. You can't jump to local labels from
     223     inline assembly across function calls, and I don't feel
     224     like embedding all the .global directives here...it really
     225     screws up the debugger. Oh well, what's 2 more instructions
     226     and a branch really cost... */
     227
     228  /* One thing which we should do is check for 32 or 64 bit models
     229     first, and then do one branch to the appropriate code section.
     230     Currently, we check the architecture bit in CPUCFGR twice. Once
     231     during the load section and again during restore. That is inefficient,
     232     and considering this code is huge anyway, saving the few bytes
     233     simply doesn't make any practical sense. FIX THIS LATER. */
     234
     235  /* Note that this routine assumes software context switches are
     236     done with the same CID. In other words, it will not manage
     237     the CIDs and assign a new one as necessary. If you tell it
     238     to restore a context at CID 2, and the current one is at CID
     239     4, it will do what it is told. It will overwrite the registers
     240     for context ID 2, meaning they are irretrievably lost. I hope
     241     you saved them earlier.... */
     242 
     243  /* Note that you can have a context jump anywhere you want, although
     244     by default we will jump to the L_restore label. If you then modify
     245     the location in the Context_Control structure, it will continue
     246     whereever you told it to go. Note however that you had better
     247     also have cleaned up the stack and frame pointers though, because
     248     they are probably still set with the values obtained from
     249     entering this function... */
     250
     251  asm volatile ("l.sfeqi   %3,0x0        \n\t"  /* Is this a self restore? */
     252               "l.bf     _L_restore    \n\t"  /* Yes it is...go there */
     253               "l.nop                  \n\t"
     254
     255               "l.lwz    %0,0(%3)      \n\t"  /* Prefetch new context */
     256               "l.mfspr  %2,r0,0x11    \n\t"  /* Status Register */
     257               "l.sw     0(%1),%2      \n\t"  /* Save it */
     258               "l.srli   %2,%2,28      \n\t"  /* Move CID into low byte */
     259               "l.mfspr  %0,%2,0x20    \n\t"  /* Offset from EPCR */
     260               "l.sw     4(%1),%0      \n\t"  /* Store it */
     261               "l.mfspr  %0,%2,0x30    \n\t"  /* Offset from EEAR */
     262               "l.sw     8(%1),%0      \n\t"  /* Store it */
     263               "l.mfspr  %0,%2,0x40    \n\t"  /* Offset from ESR */
     264               "l.sw     12(%1),%0     \n\t"  /* Store it */
     265               "l.mfspr  %0,r0,0x02    \n\t"  /* CPUCFGR */
     266               "l.andi   %0,%0,0x40    \n\t"  /* OB64S */
     267               "l.sfnei  %0,0x0        \n\t"
     268               "l.bf     _L_64bit      \n\t"  /* 64 bit architecture */
     269               "l.movhi  %0,hi(_L_restore)\n\t"
     270
     271               /****  32 bit implementation  ****/
     272               "l.ori    %0,%0,lo(_L_restore)\n\t"
     273               "l.sw     140(%1),%0    \n\t"   /* Save the PC */
     274               "l.lwz    %0,140(%3)    \n\t"   /* New PC. Expect cache miss */
     275               "l.sw     16(%1),r1     \n\t"
     276               "l.sw     20(%1),r2     \n\t"
     277               "l.sw     24(%1),r3     \n\t"
     278               "l.sw     28(%1),r4     \n\t"
     279               "l.sw     32(%1),r5     \n\t"
     280               "l.sw     36(%1),r6     \n\t"
     281               "l.sw     40(%1),r7     \n\t"
     282               "l.sw     44(%1),r8     \n\t"
     283               "l.sw     48(%1),r9     \n\t"
     284               "l.sw     52(%1),r10    \n\t"
     285               "l.sw     56(%1),r11    \n\t"
     286               "l.sw     60(%1),r12    \n\t"
     287               "l.sw     64(%1),r13    \n\t"
     288               "l.sw     68(%1),r14    \n\t"
     289               "l.sw     72(%1),r15    \n\t"
     290               "l.sw     76(%1),r16    \n\t"
     291               "l.sw     80(%1),r17    \n\t"
     292               "l.sw     84(%1),r18    \n\t"
     293               "l.sw     88(%1),r19    \n\t"
     294               "l.sw     92(%1),r20    \n\t"
     295               "l.sw     96(%1),r21    \n\t"
     296               "l.sw     100(%1),r22   \n\t"
     297               "l.sw     104(%1),r23   \n\t"
     298               "l.sw     108(%1),r24   \n\t"
     299               "l.sw     112(%1),r25   \n\t"
     300               "l.sw     116(%1),r26   \n\t"
     301               "l.sw     120(%1),r27   \n\t"
     302               "l.sw     124(%1),r28   \n\t"
     303               "l.sw     128(%1),r29   \n\t"
     304               "l.sw     132(%1),r30   \n\t"
     305               "l.jr     %0            \n\t"  /* Go there */
     306               "l.sw     136(%1),r31   \n"    /* Store the last reg */
     307
     308               /**** 64 bit implementation ****/
     309               "_L_64bit:              \n\t"
     310               "l.ori    %0,%0,lo(_L_restore)\n\t"
     311               "l.sw     264(%1),%0    \n\t"
     312               "l.sd     16(%1),r1     \n\t"
     313               "l.sd     24(%1),r2     \n\t"
     314               "l.sd     32(%1),r3     \n\t"
     315               "l.sd     40(%1),r4     \n\t"
     316               "l.sd     48(%1),r5     \n\t"
     317               "l.sd     56(%1),r6     \n\t"
     318               "l.sd     64(%1),r7     \n\t"
     319               "l.sd     72(%1),r8     \n\t"
     320               "l.sd     80(%1),r9     \n\t"
     321               "l.sd     88(%1),r10    \n\t"
     322               "l.sd     96(%1),r11    \n\t"
     323               "l.sd     104(%1),r12   \n\t"
     324               "l.sd     112(%1),r13   \n\t"
     325               "l.sd     120(%1),r14   \n\t"
     326               "l.sd     128(%1),r15   \n\t"
     327               "l.sd     136(%1),r16   \n\t"
     328               "l.sd     144(%1),r17   \n\t"
     329               "l.sd     152(%1),r18   \n\t"
     330               "l.sd     160(%1),r19   \n\t"
     331               "l.sd     168(%1),r20   \n\t"
     332               "l.sd     176(%1),r21   \n\t"
     333               "l.sd     184(%1),r22   \n\t"
     334               "l.sd     192(%1),r23   \n\t"
     335               "l.sd     200(%1),r24   \n\t"
     336               "l.sd     208(%1),r25   \n\t"
     337               "l.sd     216(%1),r26   \n\t"
     338               "l.sd     224(%1),r27   \n\t"
     339               "l.sd     232(%1),r28   \n\t"
     340               "l.sd     240(%1),r29   \n\t"
     341               "l.sd     248(%1),r30   \n\t"
     342               "l.jr     %0            \n\t"  /* Go to the new PC */
     343               "l.sd     256(%1),r31   \n"    /* Store the last reg */
     344
     345               /**** The restoration routine. ****/
     346               
     347               /* Note that when we return from this function,
     348                  we will actually be returning to a different
     349                  context than when we left. The debugger might
     350                  have conniptions over this, but we'll have to
     351                  reengineer that later. The stack and status
     352                  registers will all be changed, however we
     353                  will not touch the global interrupt mask. */
     354
     355               /* Also note, when doing any restore, the most
     356                  important registers are r1, r2, and r9. These
     357                  will be accessed immediately upon exiting the
     358                  routine, and so we want to make sure we load
     359                  them as early as possible in case they are
     360                  not in cache */
     361
     362               "_L_restore:            \n\t"  /* Restore "heir" */
     363               "l.mfspr  %2,r0,0x11    \n\t"  /* Status Register */
     364               "l.movhi  %0,0x07FF     \n\t"  /* ~SR mask  */
     365               "l.ori    %0,%0,0xD1FF  \n\t"
     366               "l.and    %2,%0,%2      \n\t"  /* save the global bits */
     367               "l.movhi  %0,0xF800     \n\t"  /* SR mask  */
     368               "l.ori    %0,%0,0x2E00  \n\t"
     369               "l.lwz    %1,0(%3)      \n\t"  /* Get the previous SR */
     370               "l.and    %0,%1,%0      \n\t"  /* Mask out the global bits */
     371               "l.or     %2,%2,%0      \n\t"  /* Combine local/global */
     372               "l.mtspr  r0,%2,0x11    \n\t"  /* Restore the status register */
     373
     374               "l.mfspr  %0,r0,0x02    \n\t"  /* CPUCFGR */
     375               "l.andi   %0,%0,0x40    \n\t"  /* OB64S */
     376               "l.sfnei  %0,0x0        \n\t"  /* Save the 64 bit flag */
     377
     378               "l.srli   %2,%2,28      \n\t"  /* Move CID into low byte */
     379               "l.lwz    %0,4(%3)      \n\t"
     380               "l.mtspr  %2,%0,0x20    \n\t"  /* Offset from EPCR */
     381               "l.lwz    %0,8(%3)      \n\t"
     382               "l.mtspr  %2,%0,0x30    \n\t"  /* Offset from EEAR */
     383               "l.lwz    %0,12(%3)     \n\t"
     384
     385               "l.bf     _L_r64bit     \n\t"  /* 64 bit architecture */
     386               "l.mtspr  %2,%0,0x30    \n\t"  /* Offset from EEAR (DELAY) */
     387
     388               /**** 32 bit restore ****/
     389               "l.lwz   r1,16(%3)      \n\t"
     390               "l.lwz   r2,20(%3)      \n\t"
     391               "l.lwz   r9,48(%3)      \n\t"
     392               "l.lwz   r3,24(%3)      \n\t"
     393               "l.lwz   r4,28(%3)      \n\t"
     394               "l.lwz   r5,32(%3)      \n\t"
     395               "l.lwz   r6,36(%3)      \n\t"
     396               "l.lwz   r7,40(%3)      \n\t"
     397               "l.lwz   r8,44(%3)      \n\t"
     398               "l.lwz   r10,52(%3)     \n\t"
     399               "l.lwz   r11,56(%3)     \n\t"
     400               "l.lwz   r12,60(%3)     \n\t"
     401               "l.lwz   r13,64(%3)     \n\t"
     402               "l.lwz   r14,68(%3)     \n\t"
     403               "l.lwz   r15,72(%3)     \n\t"
     404               "l.lwz   r16,76(%3)     \n\t"
     405               "l.lwz   r17,80(%3)     \n\t"
     406               "l.lwz   r18,84(%3)     \n\t"
     407               "l.lwz   r19,88(%3)     \n\t"
     408               "l.lwz   r20,92(%3)     \n\t"
     409               "l.lwz   r21,96(%3)     \n\t"
     410               "l.lwz   r22,100(%3)    \n\t"
     411               "l.lwz   r23,104(%3)    \n\t"
     412               "l.lwz   r24,108(%3)    \n\t"
     413               "l.lwz   r25,112(%3)    \n\t"
     414               "l.lwz   r26,116(%3)    \n\t"
     415               "l.lwz   r27,120(%3)    \n\t"
     416               "l.lwz   r28,124(%3)    \n\t"
     417               "l.lwz   r29,128(%3)    \n\t"
     418               "l.lwz   r30,132(%3)    \n\t"
     419               "l.j     _L_return      \n\t"
     420               "l.lwz   r31,136(%3)    \n"
     421
     422               /****  64 bit restore ****/
     423               "_L_r64bit:             \n\t"
     424               "l.ld    r1,16(%3)      \n\t"
     425               "l.ld    r2,24(%3)      \n\t"
     426               "l.ld   r9,80(%3)       \n\t"
     427               "l.ld   r3,32(%3)       \n\t"
     428               "l.ld   r4,40(%3)       \n\t"
     429               "l.ld   r5,48(%3)       \n\t"
     430               "l.ld   r6,56(%3)       \n\t"
     431               "l.ld   r7,64(%3)       \n\t"
     432               "l.ld   r8,72(%3)       \n\t"
     433               "l.ld   r10,88(%3)      \n\t"
     434               "l.ld   r11,96(%3)      \n\t"
     435               "l.ld   r12,104(%3)     \n\t"
     436               "l.ld   r13,112(%3)     \n\t"
     437               "l.ld   r14,120(%3)     \n\t"
     438               "l.ld   r15,128(%3)     \n\t"
     439               "l.ld   r16,136(%3)     \n\t"
     440               "l.ld   r17,144(%3)     \n\t"
     441               "l.ld   r18,152(%3)     \n\t"
     442               "l.ld   r19,160(%3)     \n\t"
     443               "l.ld   r20,168(%3)     \n\t"
     444               "l.ld   r21,176(%3)     \n\t"
     445               "l.ld   r22,184(%3)     \n\t"
     446               "l.ld   r23,192(%3)     \n\t"
     447               "l.ld   r24,200(%3)     \n\t"
     448               "l.ld   r25,208(%3)     \n\t"
     449               "l.ld   r26,216(%3)     \n\t"
     450               "l.ld   r27,224(%3)     \n\t"
     451               "l.ld   r28,232(%3)     \n\t"
     452               "l.ld   r29,240(%3)     \n\t"
     453               "l.ld   r30,248(%3)     \n\t"
     454               "l.ld   r31,256(%3)     \n"
     455
     456               "_L_return:             \n\t"  /* End of routine */
     457               
     458                : "=&r" (temp1), "+r" (run), "=&r" (temp2)
     459                : "r" (heir));
     460 
     461  /* Note that some registers were used for parameter passing and
     462     temporary registeres (temp1 and temp2). These values were
     463     saved and restored across context calls, but the values that
     464     the caller needs should have been stored on the stack. The
     465     C code should now restore these from the stack, since r1 and
     466     r2 have been restored, and return to the location specified
     467     by r9. Then, all should be happy in the world. */
    89468}
    90469
     
    97476 *  NOTE: May be unnecessary to reload some registers.
    98477 *
    99  *  OR32 Specific Information:
    100  *
    101  *  XXX document implementation including references if appropriate
     478 *  Or1k Specific Information:
     479 *
     480 *  In our implementation, this simply redirects to swich context
    102481 */
    103482
    104483void _CPU_Context_restore(
    105   Context_Control *new_context
     484  Context_Control  *run
    106485)
    107486{
     487  _CPU_Context_switch(run,NULL);
    108488}
    109489
     490
    110491/*  void __ISR_Handler()
    111492 *
    112493 *  This routine provides the RTEMS interrupt management.
    113494 *
    114  *  OR32 Specific Information:
    115  *
    116  *  XXX document implementation including references if appropriate
    117  */
    118 
    119 void _ISR_Handler()
     495 *  Or1k Specific Information:
     496 *
     497 *  Based on the Or1k interrupt architecture described in chapter 16
     498 *  and the exception architecture described in chapter 9
     499 */
     500
     501void _ISR_Handler(unsigned32 vector,unsigned32 ProgramCounter,
     502                  unsigned32 EffectiveAddress,unsigned32 StatusRegister)
    120503{
    121504   /*
     
    180563   *  return from interrupt
    181564   */
     565
     566  /* In the Or1k architecture, exceptions are handled in the
     567     startup code of the board support package. Thus, this
     568     routine is never called. Or1k exception routines are called
     569     with the following prototype:
     570
     571     function(int vector#, int PC, int Address, int StatusRegister);
     572
     573     These parameters are snapshots of the system when the exception
     574     was encountered. If virtual memory is active, things like the
     575     PC and Address may have little meaning, as they are referenced
     576     in physical space, not the virtual space of the process.
     577  */
    182578}
    183579
  • cpukit/score/cpu/or32/rtems/asm.h

    rbf1f6531 r098755b3  
    2424 */
    2525
    26 #ifndef __OR32_ASM_h
    27 #define __OR32_ASM_h
     26#ifndef __OR1K_ASM_h
     27#define __OR1K_ASM_h
    2828
    2929/*
     
    3434#define ASM
    3535#endif
    36 #include <rtems/score/cpuopts.h>
    37 #include <rtems/score/or32.h>
     36#include <rtems/score/targopts.h>
     37#include <rtems/score/or1k.h>
    3838
    3939/*
     
    9393 */
    9494
    95 #define PUBLIC(sym) .globl SYM (sym)
    96 #define EXTERN(sym) .globl SYM (sym)
     95#define PUBLIC(sym) .global SYM (sym)
     96#define EXTERN(sym) .global SYM (sym)
    9797
    9898#endif
  • cpukit/score/cpu/or32/rtems/score/cpu.h

    rbf1f6531 r098755b3  
    11/*  cpu.h
    22 *
    3  *  This include file contains information pertaining to the XXX
    4  *  processor.
     3 *  This include file contains macros pertaining to the Opencores
     4 *  or1k processor family.
    55 *
    66 *  COPYRIGHT (c) 1989-1999.
     
    1111 *  http://www.OARcorp.com/rtems/license.html.
    1212 *
    13  *  $Id$
    14  */
    15 
    16 #ifndef __CPU_h
    17 #define __CPU_h
     13 *  This file adapted from no_cpu example of the RTEMS distribution.
     14 *  The body has been modified for the Opencores Or1k implementation by
     15 *  Chris Ziomkowski. <chris@asics.ws>
     16 *
     17 */
     18
     19#ifndef _OR1K_CPU_h
     20#define _OR1K_CPU_h
    1821
    1922#ifdef __cplusplus
     
    2124#endif
    2225
    23 #include <rtems/score/or32.h>            /* pick up machine definitions */
     26#include "rtems/score/or1k.h"            /* pick up machine definitions */
    2427#ifndef ASM
    25 #include <rtems/score/types.h>
     28#include "rtems/score/or1ktypes.h"
    2629#endif
    2730
     
    4447 *  one subroutine call is avoided entirely.]
    4548 *
    46  *  OR32 Specific Information:
    47  *
    48  *  XXX document implementation including references if appropriate
    4949 */
    5050
     
    6868 *  necessary to strike a balance when setting this parameter.
    6969 *
    70  *  OR32 Specific Information:
    71  *
    72  *  XXX document implementation including references if appropriate
    7370 */
    7471
     
    9895 *  procedure on that CPU.
    9996 *
    100  *  OR32 Specific Information:
    101  *
    102  *  XXX document implementation including references if appropriate
     97 *  For the first cut of an Or1k implementation, let's not worry
     98 *  about this, and assume that our C code will autoperform any
     99 *  frame/stack allocation for us when the procedure is entered.
     100 *  If we write assembly code, we may have to deal with this manually.
     101 *  This can be changed later if we find it is impossible. This
     102 *  behavior is desireable as it allows us to work in low memory
     103 *  environments where we don't have room for a dedicated stack.
    103104 */
    104105
     
    119120 *  procedure on that CPU.
    120121 *
    121  *  OR32 Specific Information:
    122  *
    123  *  XXX document implementation including references if appropriate
    124  */
    125 
    126 #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
     122 */
     123
     124#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    127125
    128126/*
     
    135133 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
    136134 *
    137  *  OR32 Specific Information:
    138  *
    139  *  XXX document implementation including references if appropriate
    140  */
    141 
    142 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
     135 */
     136
     137#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
    143138
    144139/*
     
    147142 *  number (0)?
    148143 *
    149  *  OR32 Specific Information:
    150  *
    151  *  XXX document implementation including references if appropriate
    152144 */
    153145
     
    163155 *  the answer is TRUE.
    164156 *
    165  *  The macro name "OR32_HAS_FPU" should be made CPU specific.
     157 *  The macro name "OR1K_HAS_FPU" should be made CPU specific.
    166158 *  It indicates whether or not this CPU model has FP support.  For
    167159 *  example, it would be possible to have an i386_nofp CPU model
     
    175167 *  compiler specific.
    176168 *
    177  *  OR32 Specific Information:
    178  *
    179  *  XXX document implementation including references if appropriate
    180  */
    181 
    182 #if ( OR32_HAS_FPU == 1 )
     169 *  Or1k Specific Information:
     170 *
     171 *  At this time there are no implementations of Or1k that are
     172 *  expected to implement floating point. More importantly, the
     173 *  floating point architecture is expected to change significantly
     174 *  before such chips are fabricated.
     175 */
     176
     177#if ( OR1K_HAS_FPU == 1 )
    183178#define CPU_HARDWARE_FP     TRUE
     179#define CPU_SOFTWARE_FP     FALSE
    184180#else
    185181#define CPU_HARDWARE_FP     FALSE
     182#define CPU_SOFTWARE_FP     TRUE
    186183#endif
    187 #define CPU_SOFTWARE_FP     FALSE
     184
    188185
    189186/*
     
    202199 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
    203200 *
    204  *  OR32 Specific Information:
    205  *
    206  *  XXX document implementation including references if appropriate
    207  */
    208 
    209 #define CPU_ALL_TASKS_ARE_FP     TRUE
     201 */
     202
     203#define CPU_ALL_TASKS_ARE_FP     FALSE
    210204
    211205/*
     
    220214 *  must be saved as part of the preemption.
    221215 *
    222  *  OR32 Specific Information:
    223  *
    224  *  XXX document implementation including references if appropriate
    225216 */
    226217
     
    252243 *  be saved or restored.
    253244 *
    254  *  OR32 Specific Information:
    255  *
    256  *  XXX document implementation including references if appropriate
    257245 */
    258246
     
    279267 *    3.  generic (if no BSP and no CPU dependent)
    280268 *
    281  *  OR32 Specific Information:
    282  *
    283  *  XXX document implementation including references if appropriate
    284  */
    285 
    286 #define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
     269 */
     270
     271#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
    287272
    288273/*
     
    293278 *  If FALSE, then the grows toward smaller addresses.
    294279 *
    295  *  OR32 Specific Information:
    296  *
    297  *  XXX document implementation including references if appropriate
    298  */
    299 
    300 #define CPU_STACK_GROWS_UP               TRUE
     280 *  Or1k Specific Information:
     281 * 
     282 *  Previously I had misread the documentation and set this
     283 *  to true. Surprisingly, it seemed to work anyway. I'm
     284 *  therefore not 100% sure exactly what this does. It should
     285 *  be correct as it is now, however.
     286 */
     287
     288#define CPU_STACK_GROWS_UP               FALSE
    301289
    302290/*
     
    319307 *         in the executive to justify turning this on.
    320308 *
    321  *  OR32 Specific Information:
    322  *
    323  *  XXX document implementation including references if appropriate
    324  */
    325 
    326 #define CPU_STRUCTURE_ALIGNMENT
     309 */
     310
     311#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
    327312
    328313/*
     
    330315 *  routines are handled.
    331316 *
    332  *  OR32 Specific Information:
    333  *
    334  *  XXX document implementation including references if appropriate
     317 *  Or1k Specific Information:
     318 *
     319 *  This version of RTEMS is designed specifically to run with
     320 *  big endian architectures. If you want little endian, you'll
     321 *  have to make the appropriate adjustments here and write
     322 *  efficient routines for byte swapping. The Or1k architecture
     323 *  doesn't do this very well.
    335324 */
    336325
     
    344333 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
    345334 *
    346  *  OR32 Specific Information:
    347  *
    348  *  XXX document implementation including references if appropriate
    349335 */
    350336
     
    357343 *  and the processor control structure on the i960ca.
    358344 *
    359  *  OR32 Specific Information:
    360  *
    361  *  XXX document implementation including references if appropriate
    362  */
    363 
    364 /* may need to put some structures here.  */
     345 */
     346
    365347
    366348/*
     
    398380 *  a debugger such as gdb.  But that is another problem.
    399381 *
    400  *  OR32 Specific Information:
    401  *
    402  *  XXX document implementation including references if appropriate
    403  */
     382 * 
     383 */
     384
     385#ifdef OR1K_64BIT_ARCH
     386#define or1kreg unsigned64
     387#else
     388#define or1kreg unsigned32
     389#endif
     390
     391/* SR_MASK is the mask of values that will be copied to/from the status
     392   register on a context switch. Some values, like the flag state, are
     393   specific on the context, while others, such as interrupt enables,
     394   are global. The currently defined global bits are:
     395
     396   0x00001 SUPV:     Supervisor mode
     397   0x00002 EXR:      Exceptions on/off
     398   0x00004 EIR:      Interrupts enabled/disabled
     399   0x00008 DCE:      Data cache enabled/disabled
     400   0x00010 ICE:      Instruction cache enabled/disabled
     401   0x00020 DME:      Data MMU enabled/disabled
     402   0x00040 IME:      Instruction MMU enabled/disabled
     403   0x00080 LEE:      Little/Big Endian enable
     404   0x00100 CE:       Context ID/shadow regs enabled/disabled
     405   0x01000 OVE:      Overflow causes exception
     406   0x04000 EP:       Exceptions @ 0x0 or 0xF0000000
     407   0x08000 PXR:      Partial exception recognition enabled/disabled
     408   0x10000 SUMRA:    SPR's accessible/inaccessible
     409
     410   The context specific bits are:
     411
     412   0x00200 F         Branch flag indicator
     413   0x00400 CY        Carry flag indicator
     414   0x00800 OV        Overflow flag indicator
     415   0x02000 DSX       Delay slot exception occurred
     416   0xF8000000 CID    Current Context ID
     417*/
     418
     419#define SR_MASK 0xF8002E00
     420
     421typedef enum {
     422  SR_SUPV = 0x00001,
     423  SR_EXR = 0x00002,
     424  SR_EIR = 0x00004,
     425  SR_DCE = 0x00008,
     426  SR_ICE = 0x00010,
     427  SR_DME = 0x00020,
     428  SR_IME = 0x00040,
     429  SR_LEE = 0x00080,
     430  SR_CE = 0x00100,
     431  SR_F = 0x00200,
     432  SR_CY = 0x00400,
     433  SR_OV = 0x00800,
     434  SR_OVE = 0x01000,
     435  SR_DSX = 0x02000,
     436  SR_EP = 0x04000,
     437  SR_PXR = 0x08000,
     438  SR_SUMRA = 0x10000,
     439  SR_CID = 0xF8000000,
     440} StatusRegisterBits;
    404441
    405442typedef struct {
    406     unsigned32 some_integer_register;
    407     unsigned32 some_system_register;
     443  unsigned32  sr;     /* Current status register non persistent values */
     444  unsigned32  esr;    /* Saved exception status register */
     445  unsigned32  ear;    /* Saved exception effective address register */
     446  unsigned32  epc;    /* Saved exception PC register    */
     447  or1kreg     r[31];  /* Registers */
     448  or1kreg     pc;     /* Context PC 4 or 8 bytes for 64 bit alignment */
    408449} Context_Control;
    409450
    410 typedef struct {
    411     double      some_float_register;
    412 } Context_Control_fp;
    413 
    414 typedef struct {
    415     unsigned32 special_interrupt_register;
    416 } CPU_Interrupt_frame;
    417 
     451typedef int Context_Control_fp;
     452typedef Context_Control CPU_Interrupt_frame;
     453#define _CPU_Null_fp_context 0
     454#define _CPU_Interrupt_stack_low 0
     455#define _CPU_Interrupt_stack_high 0
    418456
    419457/*
     
    421459 *  the XXX processor specific parameters.
    422460 *
    423  *  OR32 Specific Information:
    424  *
    425  *  XXX document implementation including references if appropriate
    426461 */
    427462
     
    438473  void       (*stack_free_hook)( void* );
    439474  /* end of fields required on all CPUs */
    440 
    441475}   rtems_cpu_table;
    442476
     
    445479 *  the file rtems/system.h.
    446480 *
    447  *  OR32 Specific Information:
    448  *
    449  *  XXX document implementation including references if appropriate
    450  */
    451 
    452 /*
    453  *  Macros to access OR32 specific additions to the CPU Table
    454  *
    455  *  OR32 Specific Information:
    456  *
    457  *  XXX document implementation including references if appropriate
     481 */
     482
     483/*
     484 *  Macros to access OR1K specific additions to the CPU Table
     485 *
    458486 */
    459487
     
    466494 *  _CPU_Context_Initialize.
    467495 *
    468  *  OR32 Specific Information:
    469  *
    470  *  XXX document implementation including references if appropriate
    471  */
    472 
    473 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
     496 */
     497
     498/* SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context; */
    474499
    475500/*
     
    485510 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    486511 *
    487  *  OR32 Specific Information:
    488  *
    489  *  XXX document implementation including references if appropriate
    490  */
    491 
     512 */
     513
     514/*
    492515SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    493516SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
     517*/
    494518
    495519/*
     
    502526 *  sequence (if a dispatch is necessary).
    503527 *
    504  *  OR32 Specific Information:
    505  *
    506  *  XXX document implementation including references if appropriate
    507528 */
    508529
     
    512533 *  Nothing prevents the porter from declaring more CPU specific variables.
    513534 *
    514  *  OR32 Specific Information:
    515  *
    516  *  XXX document implementation including references if appropriate
    517535 */
    518536
     
    525543 *  CPUs with a "floating point save context" instruction.
    526544 *
    527  *  OR32 Specific Information:
    528  *
    529  *  XXX document implementation including references if appropriate
    530  */
    531 
    532 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
     545 *  Or1k Specific Information:
     546 *
     547 *  We don't support floating point in this version, so the size is 0
     548 */
     549
     550#define CPU_CONTEXT_FP_SIZE 0
    533551
    534552/*
     
    537555 *  system this thread must exist and be able to process all directives.
    538556 *
    539  *  OR32 Specific Information:
    540  *
    541  *  XXX document implementation including references if appropriate
    542557 */
    543558
     
    548563 *  by RTEMS.
    549564 *
    550  *  OR32 Specific Information:
    551  *
    552  *  XXX document implementation including references if appropriate
    553  */
    554 
    555 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
     565 */
     566
     567#define CPU_INTERRUPT_NUMBER_OF_VECTORS      16
    556568#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
    557 
    558 /*
    559  *  This is defined if the port has a special way to report the ISR nesting
    560  *  level.  Most ports maintain the variable _ISR_Nest_level.
    561  */
    562 
    563 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
    564569
    565570/*
     
    567572 *  that a "reasonable" small application should not have any problems.
    568573 *
    569  *  OR32 Specific Information:
    570  *
    571  *  XXX document implementation including references if appropriate
    572  */
    573 
    574 #define CPU_STACK_MINIMUM_SIZE          (1024*4)
     574 */
     575
     576#define CPU_STACK_MINIMUM_SIZE          4096
    575577
    576578/*
     
    578580 *  alignment does not take into account the requirements for the stack.
    579581 *
    580  *  OR32 Specific Information:
    581  *
    582  *  XXX document implementation including references if appropriate
    583582 */
    584583
     
    604603 *         elements allocated from the heap meet all restrictions.
    605604 *
    606  *  OR32 Specific Information:
    607  *
    608  *  XXX document implementation including references if appropriate
    609605 */
    610606
     
    622618 *         be greater or equal to than CPU_ALIGNMENT.
    623619 *
    624  *  OR32 Specific Information:
    625  *
    626  *  XXX document implementation including references if appropriate
    627620 */
    628621
     
    637630 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
    638631 *
    639  *  OR32 Specific Information:
    640  *
    641  *  XXX document implementation including references if appropriate
    642632 */
    643633
    644634#define CPU_STACK_ALIGNMENT        0
    645635
    646 /*
    647  *  ISR handler macros
    648  */
    649 
    650 /*
    651  *  Support routine to initialize the RTEMS vector table after it is allocated.
    652  *
    653  *  OR32 Specific Information:
    654  *
    655  *  XXX document implementation including references if appropriate
    656  */
    657  
    658 #define _CPU_Initialize_vectors()
     636/* ISR handler macros */
    659637
    660638/*
     
    662640 *  level is returned in _level.
    663641 *
    664  *  OR32 Specific Information:
    665  *
    666  *  XXX document implementation including references if appropriate
    667642 */
    668643
     
    677652 *  _level is not modified.
    678653 *
    679  *  OR32 Specific Information:
    680  *
    681  *  XXX document implementation including references if appropriate
    682654 */
    683655
     
    692664 * modified.
    693665 *
    694  *  OR32 Specific Information:
    695  *
    696  *  XXX document implementation including references if appropriate
    697666 */
    698667
     
    713682 *  The get routine usually must be implemented as a subroutine.
    714683 *
    715  *  OR32 Specific Information:
    716  *
    717  *  XXX document implementation including references if appropriate
    718684 */
    719685
     
    748714 *        where the PSR contains an enable FPU bit.
    749715 *
    750  *  OR32 Specific Information:
    751  *
    752  *  XXX document implementation including references if appropriate
    753716 */
    754717
     
    756719                                 _isr, _entry_point, _is_fp ) \
    757720  { \
     721  memset(_the_context,'\0',sizeof(Context_Control)); \
     722  (_the_context)->r[1] = (unsigned32*) ((unsigned32) (_stack_base) + (_size) ); \
     723  (_the_context)->r[2] = (unsigned32*) ((unsigned32) (_stack_base)); \
     724  (_the_context)->sr  = (_isr) ? 0x0000001B : 0x0000001F; \
     725  (_the_context)->pc  = (unsigned32*) _entry_point ; \
    758726  }
    759727
     
    767735 *  assumptions of restoring a context.
    768736 *
    769  *  OR32 Specific Information:
    770  *
    771  *  XXX document implementation including references if appropriate
    772737 */
    773738
     
    788753 *  or low to high based on the whim of the CPU designers.
    789754 *
    790  *  OR32 Specific Information:
    791  *
    792  *  XXX document implementation including references if appropriate
    793755 */
    794756
     
    807769 *  a "null FP status word" in the correct place in the FP context.
    808770 *
    809  *  OR32 Specific Information:
    810  *
    811  *  XXX document implementation including references if appropriate
    812771 */
    813772
     
    826785 *  halts/stops the CPU.
    827786 *
    828  *  OR32 Specific Information:
    829  *
    830  *  XXX document implementation including references if appropriate
    831787 */
    832788
     
    893849 *      bit set
    894850 *
    895  *  OR32 Specific Information:
    896  *
    897  *  XXX document implementation including references if appropriate
    898  */
    899 
    900 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
     851 */
     852
     853  /* #define CPU_USE_GENERIC_BITFIELD_CODE FALSE */
     854#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
    901855#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
    902856
    903857#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
    904858
     859  /* Get a value between 0 and N where N is the bit size */
     860  /* This routine makes use of the fact that CPUCFGR defines
     861     OB32S to have value 32, and OB64S to have value 64. If
     862     this ever changes then this routine will fail. */
    905863#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
    906   { \
    907     (_output) = 0;   /* do something to prevent warnings */ \
    908   }
     864     asm volatile ("l.mfspr %0,r0,0x2   \n\t"\
     865                   "l.andi  %0,%0,0x60  \n\t"\
     866                   "l.ff1   %1,%1,r0    \n\t"\
     867                   "l.sub   %0,%0,%1    \n\t" : "=&r" (_output), "+r" (_value));
    909868
    910869#endif
    911 
     870   
    912871/* end of Bitfield handler macros */
    913872
     
    917876 *  for that routine.
    918877 *
    919  *  OR32 Specific Information:
    920  *
    921  *  XXX document implementation including references if appropriate
    922878 */
    923879
     
    925881
    926882#define _CPU_Priority_Mask( _bit_number ) \
    927   ( 1 << (_bit_number) )
     883    (1 << _bit_number)
    928884
    929885#endif
     
    935891 *  for that routine.
    936892 *
    937  *  OR32 Specific Information:
    938  *
    939  *  XXX document implementation including references if appropriate
    940893 */
    941894
     
    956909 *  This routine performs CPU dependent initialization.
    957910 *
    958  *  OR32 Specific Information:
    959  *
    960  *  XXX document implementation including references if appropriate
    961911 */
    962912
     
    972922 *  processor's vector table.
    973923 *
    974  *  OR32 Specific Information:
    975  *
    976  *  XXX document implementation including references if appropriate
    977924 */
    978925 
     
    988935 *  This routine installs an interrupt vector.
    989936 *
    990  *  OR32 Specific Information:
     937 *  NO_CPU Specific Information:
    991938 *
    992939 *  XXX document implementation including references if appropriate
     
    1007954 *         is TRUE.
    1008955 *
    1009  *  OR32 Specific Information:
    1010  *
    1011  *  XXX document implementation including references if appropriate
    1012956 */
    1013957
     
    1022966 *         is TRUE.
    1023967 *
    1024  *  OR32 Specific Information:
    1025  *
    1026  *  XXX document implementation including references if appropriate
    1027968 */
    1028969
     
    1034975 *  This routine switches from the run context to the heir context.
    1035976 *
    1036  *  OR32 Specific Information:
    1037  *
    1038  *  XXX document implementation including references if appropriate
     977 *  Or1k Specific Information:
     978 *
     979 *  Please see the comments in the .c file for a description of how
     980 *  this function works. There are several things to be aware of.
    1039981 */
    1040982
     
    1052994 *  NOTE: May be unnecessary to reload some registers.
    1053995 *
    1054  *  OR32 Specific Information:
    1055  *
    1056  *  XXX document implementation including references if appropriate
    1057996 */
    1058997
     
    10661005 *  This routine saves the floating point context passed to it.
    10671006 *
    1068  *  OR32 Specific Information:
    1069  *
    1070  *  XXX document implementation including references if appropriate
    10711007 */
    10721008
     
    10801016 *  This routine restores the floating point context passed to it.
    10811017 *
    1082  *  OR32 Specific Information:
    1083  *
    1084  *  XXX document implementation including references if appropriate
    10851018 */
    10861019
     
    11081041 *  will be fetched incorrectly.
    11091042 *
    1110  *  OR32 Specific Information:
    1111  *
    1112  *  XXX document implementation including references if appropriate
    11131043 */
    11141044 
  • cpukit/score/cpu/or32/rtems/score/or32.h

    rbf1f6531 r098755b3  
    1 /*  or32.h
     1/*  or1k.h
    22 *
    3  *  This file sets up basic CPU dependency settings based on
    4  *  compiler settings.  For example, it can determine if
    5  *  floating point is available.  This particular implementation
    6  *  is specified to the OPENCORES.ORG OR32 port.
    7  *
     3 *  This include file contains Or1k definitions pertaining to the Opencores
     4 *  or1k processor family.
    85 *
    96 *  COPYRIGHT (c) 1989-1999.
     
    1411 *  http://www.OARcorp.com/rtems/license.html.
    1512 *
    16  *  $Id$
     13 *  This file adapted from no_cpu example of the RTEMS distribution.
     14 *  The body has been modified for the Opencores Or1k implementation by
     15 *  Chris Ziomkowski. <chris@asics.ws>
    1716 *
    1817 */
    1918
    20 #ifndef _INCLUDE_OR32_h
    21 #define _INCLUDE_OR32_h
     19#ifndef _OR1K_H
     20#define _OR1K_H
    2221
    2322#ifdef __cplusplus
     
    2726/*
    2827 *  This file contains the information required to build
    29  *  RTEMS for a particular member of the OPENCORES.ORG OR32 family.
     28 *  RTEMS for a particular member of the or1k CPU family.
    3029 *  It does this by setting variables to indicate which
    3130 *  implementation dependent features are present in a particular
     
    4443
    4544#define CPU_MODEL_NAME  "rtems_multilib"
    46 #define OR32_HAS_FPU     1
     45#define OR1K_HAS_FPU     1
    4746
    48 #elif defined(__or1k__) || defined(__OR1K__)
     47#elif defined(or1200)
    4948 
    50 #define CPU_MODEL_NAME  "or32_model"
    51 #define OR32_HAS_FPU     1
     49#define CPU_MODEL_NAME  "OR1200"
     50#define OR1K_HAS_FPU     0
    5251 
    5352#else
    5453 
    55 #error "Unsupported CPU Model"
     54#define CPU_MODEL_NAME "Generic Or1k Compatible"
     55#define OR1K_HAS_FPU    0
    5656 
    5757#endif
     
    6161 */
    6262
    63 #define CPU_NAME "OPENCORES.ORG OR32"
     63#define CPU_NAME "OpenRisc 1000"
    6464
    6565#ifdef __cplusplus
     
    6767#endif
    6868
    69 #endif /* ! _INCLUDE_OR32_h */
     69#endif /* ! _INCLUDE_NO_CPU_h */
    7070/* end of include file */
  • cpukit/score/cpu/or32/rtems/score/types.h

    rbf1f6531 r098755b3  
    1 /*  or32types.h
     1/*  or1ktypes.h
    22 *
    3  *  This include file contains type definitions pertaining to the Intel
    4  *  or32 processor family.
     3 *  This include file contains type definitions pertaining to the Opencores
     4 *  or1k processor family.
    55 *
    66 *  COPYRIGHT (c) 1989-1999.
     
    1111 *  http://www.OARcorp.com/rtems/license.html.
    1212 *
    13  *  $Id$
     13 *  This file adapted from no_cpu example of the RTEMS distribution.
     14 *  The body has been modified for the Opencores Or1k implementation by
     15 *  Chris Ziomkowski. <chris@asics.ws>
    1416 */
    1517
    16 #ifndef __OR32_TYPES_h
    17 #define __OR32_TYPES_h
     18#ifndef __OR1K_TYPES_h
     19#define __OR1K_TYPES_h
    1820
    1921#ifndef ASM
     
    4446typedef double         double_precision;     /* double precision float */
    4547
    46 typedef void or32_isr;
    47 typedef void ( *or32_isr_entry )( void );
     48typedef void no_cpu_isr;
     49typedef void ( *no_cpu_isr_entry )( void );
     50
     51/*
     52 * Turns out the that the disable POSIX option doesn't work
     53 * too well. Specifically, the libc library still wants to know
     54 * these POSIX values. We'll go ahead and include them here
     55 * until such time as someone like OAR who is familiar with this
     56 * can figure out what should really be done.
     57 */
     58
     59#define NAME_MAX 255
     60#define LINK_MAX 8
    4861
    4962#ifdef __cplusplus
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