Changeset 090760c in rtems
- Timestamp:
- 03/31/04 04:20:42 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 945ace0d
- Parents:
- 5601b2b2
- Location:
- c/src/lib/libbsp/i960/cvme961
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/i960/cvme961/ChangeLog
r5601b2b2 r090760c 1 2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * clock/ckinit.c, include/bsp.h, shmsupp/addrconv.c, 4 shmsupp/getcfg.c, shmsupp/lock.c, shmsupp/mpisr.c, 5 startup/bspstart.c, timer/timer.c: Convert to using c99 fixed size 6 types. 7 1 8 2004-02-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> 2 9 -
c/src/lib/libbsp/i960/cvme961/clock/ckinit.c
r5601b2b2 r090760c 25 25 #define CLOCK_VECTOR 5 26 26 27 rtems_unsigned32Clock_isrs; /* ISRs until next tick */27 uint32_t Clock_isrs; /* ISRs until next tick */ 28 28 i960_isr_entry Old_ticker; 29 volatile rtems_unsigned32Clock_driver_ticks;29 volatile uint32_t Clock_driver_ticks; 30 30 /* ticks since initialization */ 31 31 … … 94 94 ) 95 95 { 96 rtems_unsigned32isrlevel;96 uint32_t isrlevel; 97 97 rtems_libio_ioctl_args_t *args = pargp; 98 98 -
c/src/lib/libbsp/i960/cvme961/include/bsp.h
r5601b2b2 r090760c 73 73 74 74 #define rtems_bsp_delay( microseconds ) \ 75 { register rtems_unsigned32_delay=(microseconds); \76 register rtems_unsigned32_tmp = 0; /* initialized to avoid warning */ \75 { register uint32_t _delay=(microseconds); \ 76 register uint32_t _tmp = 0; /* initialized to avoid warning */ \ 77 77 asm volatile( "0: \ 78 78 remo 3,31,%0 ; \ -
c/src/lib/libbsp/i960/cvme961/shmsupp/addrconv.c
r5601b2b2 r090760c 29 29 ) 30 30 { 31 rtems_unsigned32 workaddr = (rtems_unsigned32) address;31 uint32_t workaddr = (uint32_t) address; 32 32 33 33 if ( workaddr >= 0xffff0000 ) 34 34 workaddr = (workaddr & 0xffff) | 0xb4000000; 35 return ( ( rtems_unsigned32*)workaddr );35 return ( (uint32_t*)workaddr ); 36 36 } -
c/src/lib/libbsp/i960/cvme961/shmsupp/getcfg.c
r5601b2b2 r090760c 55 55 56 56 void Shm_Get_configuration( 57 rtems_unsigned32localnode,57 uint32_t localnode, 58 58 shm_config_table **shmcfg 59 59 ) … … 61 61 #if ( USE_ONBOARD_RAM == 1 ) 62 62 if ( Shm_RTEMS_MP_Configuration->node == MASTER ) 63 BSP_shm_cfgtbl.base = ( rtems_unsigned32*)0x00300000;63 BSP_shm_cfgtbl.base = (uint32_t*)0x00300000; 64 64 else 65 BSP_shm_cfgtbl.base = ( rtems_unsigned32*)0x10300000;65 BSP_shm_cfgtbl.base = (uint32_t*)0x10300000; 66 66 #else 67 BSP_shm_cfgtbl.base = ( rtems_unsigned32*)0x20000000;67 BSP_shm_cfgtbl.base = (uint32_t*)0x20000000; 68 68 #endif 69 69 … … 87 87 BSP_shm_cfgtbl.poll_intr = INTR_MODE; 88 88 BSP_shm_cfgtbl.Intr.address = 89 ( rtems_unsigned32*) (0xffff0021|((localnode-1) << 12));89 (uint32_t*) (0xffff0021|((localnode-1) << 12)); 90 90 /* use ICMS0 */ 91 91 BSP_shm_cfgtbl.Intr.value = 1; -
c/src/lib/libbsp/i960/cvme961/shmsupp/lock.c
r5601b2b2 r090760c 45 45 ) 46 46 { 47 rtems_unsigned32isr_level, oldlock;47 uint32_t isr_level, oldlock; 48 48 49 49 rtems_interrupt_disable( isr_level ); … … 67 67 ) 68 68 { 69 rtems_unsigned32isr_level;69 uint32_t isr_level; 70 70 71 71 lq_cb->lock = SHM_UNLOCK_VALUE; -
c/src/lib/libbsp/i960/cvme961/shmsupp/mpisr.c
r5601b2b2 r090760c 26 26 ) 27 27 { 28 rtems_unsigned32vic_vector;28 uint32_t vic_vector; 29 29 30 30 /* enable_tracing(); */ 31 vic_vector = (*(volatile rtems_unsigned8*)0xb6000007);31 vic_vector = (*(volatile uint8_t*)0xb6000007); 32 32 /* reset intr by reading */ 33 33 /* vector at IPL=3 */ 34 34 Shm_Interrupt_count += 1; 35 35 rtems_multiprocessing_announce(); 36 (*(volatile rtems_unsigned8*)0xa000005f) = 0; /* clear ICMS0 */36 (*(volatile uint8_t*)0xa000005f) = 0; /* clear ICMS0 */ 37 37 i960_clear_intr( 6 ); 38 38 … … 53 53 void Shm_setvec() 54 54 { 55 rtems_unsigned32isrlevel;55 uint32_t isrlevel; 56 56 57 57 rtems_interrupt_disable( isrlevel ); 58 58 /* set SQSIO4 CTL REG for */ 59 59 /* VME slave address */ 60 (*( rtems_unsigned8*)0xc00000b0) =60 (*(uint8_t*)0xc00000b0) = 61 61 (Shm_RTEMS_MP_Configuration->node - 1) | 0x10; 62 62 set_vector( Shm_isr_cvme961, 6, 1 ); 63 63 /* set ICMS Bector Base Register */ 64 (*( rtems_unsigned8*)0xa0000053) = 0x60; /* XINT6 vector is 0x62 */64 (*(uint8_t*)0xa0000053) = 0x60; /* XINT6 vector is 0x62 */ 65 65 /* set ICMS Intr Control Reg */ 66 (*( rtems_unsigned8*)0xa0000047) = 0xeb; /* ICMS0 enabled, IPL=0 */67 (*( rtems_unsigned8*)0xa000005f) = 0; /* clear ICMS0 */66 (*(uint8_t*)0xa0000047) = 0xeb; /* ICMS0 enabled, IPL=0 */ 67 (*(uint8_t*)0xa000005f) = 0; /* clear ICMS0 */ 68 68 rtems_interrupt_enable( isrlevel ); 69 69 } -
c/src/lib/libbsp/i960/cvme961/startup/bspstart.c
r5601b2b2 r090760c 41 41 42 42 void bsp_postdriver_hook(void); 43 void bsp_libc_init( void *, u nsigned32, int );43 void bsp_libc_init( void *, uint32_t, int ); 44 44 45 45 /* … … 60 60 { 61 61 extern int end; 62 rtems_unsigned32heap_start;62 uint32_t heap_start; 63 63 64 heap_start = ( rtems_unsigned32) &end;64 heap_start = (uint32_t) &end; 65 65 if (heap_start & (CPU_ALIGNMENT-1)) 66 66 heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); … … 83 83 /* set node number in SQSIO4 CTL REG */ 84 84 85 *(( rtems_unsigned32*)0xc00000b0) =85 *((uint32_t*)0xc00000b0) = 86 86 (Configuration.User_multiprocessing_table) ? 87 87 Configuration.User_multiprocessing_table->node : 0; -
c/src/lib/libbsp/i960/cvme961/timer/timer.c
r5601b2b2 r090760c 75 75 int Read_timer() 76 76 { 77 rtems_unsigned8msb, lsb;78 rtems_unsigned32remaining, total;77 uint8_t msb, lsb; 78 uint32_t remaining, total; 79 79 80 80 Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0xce ); /* read the counter value */
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