- Timestamp:
- 06/07/11 07:58:16 (13 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 25874f0
- Parents:
- 479f8768
- Location:
- c/src/lib/libcpu/arm
- Files:
-
- 1 deleted
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/arm/ChangeLog
r479f8768 r07f8af1 1 2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de> 2 3 * shared/include/cache_.h: Moved content of "cache.h" to "cache_.h". 4 * shared/include/cache.h: Removed file. 5 1 6 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org> 2 7 -
c/src/lib/libcpu/arm/shared/include/cache_.h
r479f8768 r07f8af1 4 4 * @ingroup arm 5 5 * 6 * @brief Empty file.6 * @brief ARM cache defines and implementation. 7 7 */ 8 8 9 9 /* 10 * Copyright (c) 2009 11 * embedded brains GmbH 12 * Obere Lagerstr. 30 13 * D-82178 Puchheim 14 * Germany 15 * <rtems@embedded-brains.de> 10 * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. 11 * 12 * embedded brains GmbH 13 * Obere Lagerstr. 30 14 * 82178 Puchheim 15 * Germany 16 * <rtems@embedded-brains.de> 16 17 * 17 18 * The license and distribution terms for this file may be 18 19 * found in the file LICENSE in this distribution or at 19 20 * http://www.rtems.com/license/LICENSE. 21 * 22 * $Id$ 20 23 */ 21 24 … … 23 26 #define LIBCPU_ARM_CACHE__H 24 27 25 /* Empty */ 28 #ifdef __ARM_ARCH_5TEJ__ 29 #include <libcpu/arm-cp15.h> 30 31 #define CPU_DATA_CACHE_ALIGNMENT 32 32 #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 33 34 static inline void _CPU_cache_flush_1_data_line(const void *d_addr) 35 { 36 arm_cp15_data_cache_clean_line(d_addr); 37 } 38 39 static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr) 40 { 41 arm_cp15_data_cache_invalidate_line(d_addr); 42 } 43 44 static inline void _CPU_cache_freeze_data(void) 45 { 46 /* TODO */ 47 } 48 49 static inline void _CPU_cache_unfreeze_data(void) 50 { 51 /* TODO */ 52 } 53 54 static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) 55 { 56 arm_cp15_instruction_cache_invalidate_line(d_addr); 57 } 58 59 static inline void _CPU_cache_freeze_instruction(void) 60 { 61 /* TODO */ 62 } 63 64 static inline void _CPU_cache_unfreeze_instruction(void) 65 { 66 /* TODO */ 67 } 68 69 static inline void _CPU_cache_flush_entire_data(void) 70 { 71 arm_cp15_data_cache_test_and_clean(); 72 } 73 74 static inline void _CPU_cache_invalidate_entire_data(void) 75 { 76 arm_cp15_data_cache_invalidate(); 77 } 78 79 static inline void _CPU_cache_enable_data(void) 80 { 81 rtems_interrupt_level level; 82 uint32_t ctrl; 83 84 rtems_interrupt_disable(level); 85 ctrl = arm_cp15_get_control(); 86 ctrl |= ARM_CP15_CTRL_C; 87 arm_cp15_set_control(ctrl); 88 rtems_interrupt_enable(level); 89 } 90 91 static inline void _CPU_cache_disable_data(void) 92 { 93 rtems_interrupt_level level; 94 uint32_t ctrl; 95 96 rtems_interrupt_disable(level); 97 arm_cp15_data_cache_test_and_clean_and_invalidate(); 98 ctrl = arm_cp15_get_control(); 99 ctrl &= ~ARM_CP15_CTRL_C; 100 arm_cp15_set_control(ctrl); 101 rtems_interrupt_enable(level); 102 } 103 104 static inline void _CPU_cache_invalidate_entire_instruction(void) 105 { 106 arm_cp15_instruction_cache_invalidate(); 107 } 108 109 static inline void _CPU_cache_enable_instruction(void) 110 { 111 rtems_interrupt_level level; 112 uint32_t ctrl; 113 114 rtems_interrupt_disable(level); 115 ctrl = arm_cp15_get_control(); 116 ctrl |= ARM_CP15_CTRL_I; 117 arm_cp15_set_control(ctrl); 118 rtems_interrupt_enable(level); 119 } 120 121 static inline void _CPU_cache_disable_instruction(void) 122 { 123 rtems_interrupt_level level; 124 uint32_t ctrl; 125 126 rtems_interrupt_disable(level); 127 ctrl = arm_cp15_get_control(); 128 ctrl &= ~ARM_CP15_CTRL_I; 129 arm_cp15_set_control(ctrl); 130 rtems_interrupt_enable(level); 131 } 132 #endif 26 133 27 134 #endif /* LIBCPU_ARM_CACHE__H */
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