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Changeset 0789abef in rtems for c/src/lib/include
- Timestamp:
- 08/04/97 22:17:17 (26 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 19fd334
- Parents:
- 89a32784
- File:
-
- 1 edited
-
c/src/lib/include/motorola/mc68681.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/include/motorola/mc68681.h
r89a32784 r0789abef 1 1 /* 2 2 * mc68681-duart.h -- Low level support code for the Motorola mc68681 3 * DUART. This one is one the mc68ec0x0 board. 4 * Written by rob@cygnus.com (Rob Savoye) 3 * DUART. 4 * 5 * Originally written by rob@cygnus.com (Rob Savoye) for the libgloss 6 * IDP support. 5 7 * 6 8 * $Id$ … … 9 11 #ifndef __MC68681_H__ 10 12 #define __MC68681_H__ 11 #define DUART_ADDR 0xb00003 /* base address of the DUART */ 12 13 /* 14 * mc68681 register offsets 15 */ 16 #define DUART_MR1A 0x00 /* Mode Register A */ 17 #define DUART_MR2A 0x00 /* Mode Register A */ 18 #define DUART_SRA 0x04 /* Status Register A */ 19 #define DUART_CSRA 0x04 /* Clock-Select Register A */ 20 #define DUART_CRA 0x08 /* Command Register A */ 21 #define DUART_RBA 0x0c /* Receive Buffer A */ 22 #define DUART_TBA 0x0c /* Transmit Buffer A */ 23 #define DUART_IPCR 0x10 /* Input Port Change Register */ 24 #define DUART_ACR 0x10 /* Auxiliary Control Register */ 25 #define DUART_ISR 0x14 /* Interrupt Status Register */ 26 #define DUART_IMR 0x14 /* Interrupt Mask Register */ 27 #define DUART_CUR 0x18 /* Counter Mode: current MSB */ 28 #define DUART_CTUR 0x18 /* Counter/Timer upper reg */ 29 #define DUART_CLR 0x1c /* Counter Mode: current LSB */ 30 #define DUART_CTLR 0x1c /* Counter/Timer lower reg */ 31 #define DUART_MR1B 0x20 /* Mode Register B */ 32 #define DUART_MR2B 0x20 /* Mode Register B */ 33 #define DUART_SRB 0x24 /* Status Register B */ 34 #define DUART_CSRB 0x24 /* Clock-Select Register B */ 35 #define DUART_CRB 0x28 /* Command Register B */ 36 #define DUART_RBB 0x2c /* Receive Buffer B */ 37 #define DUART_TBB 0x2c /* Transmit Buffer A */ 38 #define DUART_IVR 0x30 /* Interrupt Vector Register */ 39 #define DUART_IP 0x34 /* Input Port */ 40 #define DUART_OPCR 0x34 /* Output Port Configuration Reg. */ 41 #define DUART_STRTCC 0x38 /* Start-Counter command */ 42 #define DUART_OPRSET 0x38 /* Output Port Reg, SET bits */ 43 #define DUART_STOPCC 0x3c /* Stop-Counter command */ 44 #define DUART_OPRRST 0x3c /* Output Port Reg, ReSeT bits */ 45 46 /* this is just if you want a copy of the chip's registers */ 47 struct duart_regs { 48 unsigned char mr1a_reg; /* Mode Register A */ 49 unsigned char mr2a_reg; /* Mode Register A */ 50 unsigned char sra_reg; /* Status Register A */ 51 unsigned char csra_reg; /* Clock-Select Register A */ 52 unsigned char cra_reg; /* Command Register A */ 53 unsigned char ipcr_reg; /* Input Port Change Register */ 54 unsigned char acr_reg; /* Auxiliary Control Register */ 55 unsigned char isr_reg; /* Interrupt Status Register */ 56 unsigned char imr_reg; /* Interrupt Mask Register */ 57 unsigned char cur_reg; /* Counter Mode: current MSB */ 58 unsigned char ctur_reg; /* Counter/Timer upper reg */ 59 unsigned char clr_reg; /* Counter Mode: current LSB */ 60 unsigned char ctlr_reg; /* Counter/Timer lower reg */ 61 unsigned char mr1b_reg; /* Mode Register B */ 62 unsigned char mr2b_reg; /* Mode Register B */ 63 unsigned char srb_reg; /* Status Register B */ 64 unsigned char csrb_reg; /* Clock-Select Register B */ 65 unsigned char crb_reg; /* Command Register B */ 66 unsigned char ivr_reg; /* Interrupt Vector Register */ 67 unsigned char ip_reg; /* Input Port */ 68 unsigned char opcr_reg; /* Output Port Configuration Reg. */ 69 unsigned char oprset_reg; /* Output Port Reg; bit SET */ 70 unsigned char strtcc_reg; /* Start-Counter command */ 71 unsigned char oprrst_reg; /* Output Port Reg; bit ReSeT */ 72 unsigned char stopcc_reg; /* Stop-Counter command */ 73 unsigned char pad; 74 }; 75 76 /* Some RTEMS style defines: */ 77 #ifndef VOL8 78 #define VOL8( ptr ) ((volatile rtems_unsigned8 *)(ptr)) 13 14 /* 15 * In the dark ages when this controller was designed, it was actually 16 * possible to access data on unaligned byte boundaries with no penalty. 17 * Now we find this chip in configurations in which the registers are 18 * at 16-bit, 32-bit, and 64-bit boundaries at the whim of the board 19 * designer. If the registers are not at byte addresses, then 20 * set this multiplier before including this file to correct the offsets. 21 */ 22 23 #ifndef MC68681_OFFSET_MULTIPLIER 24 #define MC68681_OFFSET_MULTIPLIER 1 79 25 #endif 80 26 81 #define MC68681_WRITE( reg, data ) \ 82 *(VOL8(DUART_ADDR+reg)) = (data) 83 84 #define MC68681_READ( reg, data ) \ 85 (data) = *(VOL8(DUART_ADDR+reg)) 86 27 #define __MC68681_REG(_R) ((_R) * MC68681_OFFSET_MULTIPLIER) 28 29 /* 30 * mc68681 register offsets Read/Write Addresses 31 */ 32 #define MC68681_MODE_REG_1A __MC68681_REG(0) /* MR1A-MR Prior to Read */ 33 #define MC68681_MODE_REG_2A __MC68681_REG(0) /* MR2A-MR After Read */ 34 35 #define MC68681_COUNT_MODE_CURRENT_MSB __MC68681_REG(6) /* CTU */ 36 #define MC68681_COUNTER_TIMER_UPPER_REG __MC68681_REG(6) /* CTU */ 37 #define MC68681_COUNT_MODE_CURRENT_LSB __MC68681_REG(7) /* CTL */ 38 #define MC68681_COUNTER_TIMER_LOWER_REG __MC68681_REG(7) /* CTL */ 39 #define MC68681_INTERRUPT_VECTOR_REG __MC68681_REG(12) /* IVR */ 40 41 #define MC68681_MODE_REG_1B __MC68681_REG(8) /* MR1B-MR Prior to Read */ 42 #define MC68681_MODE_REG_2B __MC68681_REG(8) /* MR2BA-MR After Read */ 43 44 /* 45 * mc68681 register offsets Read Only Addresses 46 */ 47 #define MC68681_STATUS_REG_A __MC68681_REG(1) /* SRA */ 48 #define MC68681_MASK_ISR_REG __MC68681_REG(2) /* MISR */ 49 #define MC68681_RECEIVE_BUFFER_A __MC68681_REG(3) /* RHRA */ 50 #define MC68681_INPUT_PORT_CHANGE_REG __MC68681_REG(4) /* IPCR */ 51 #define MC68681_INTERRUPT_STATUS_REG __MC68681_REG(5) /* ISR */ 52 #define MC68681_STATUS_REG_B __MC68681_REG(9) /* SRB */ 53 #define MC68681_RECEIVE_BUFFER_B __MC68681_REG(11) /* RHRB */ 54 #define MC68681_INPUT_PORT __MC68681_REG(13) /* IP */ 55 #define MC68681_START_COUNT_CMD __MC68681_REG(14) /* SCC */ 56 #define MC68681_STOP_COUNT_CMD __MC68681_REG(15) /* STC */ 57 58 /* 59 * mc68681 register offsets Write Only Addresses 60 */ 61 #define MC68681_CLOCK_SELECT_REG_A __MC68681_REG(1) /* CSRA */ 62 #define MC68681_COMMAND_REG_A __MC68681_REG(2) /* CRA */ 63 #define MC68681_TRANSMIT_BUFFER_A __MC68681_REG(3) /* THRA */ 64 #define MC68681_AUX_CTRL_REG __MC68681_REG(4) /* ACR */ 65 #define MC68681_INTERRUPT_MASK_REG __MC68681_REG(5) /* IMR */ 66 #define MC68681_CLOCK_SELECT_REG_B __MC68681_REG(9) /* CSRB */ 67 #define MC68681_COMMAND_REG_B __MC68681_REG(10) /* CRB */ 68 #define MC68681_TRANSMIT_BUFFER_B __MC68681_REG(11) /* THRB */ 69 #define MC68681_OUTPUT_PORT_CONFIG_REG __MC68681_REG(13) /* OPCR */ 70 #define MC68681_OUTPUT_PORT_SET_REG __MC68681_REG(14) /* SOPBC */ 71 #define MC68681_OUTPUT_PORT_RESET_BITS __MC68681_REG(15) /* COPBC */ 72 73 74 #ifndef MC6681_VOL 75 #define MC6681_VOL( ptr ) ((volatile unsigned char *)(ptr)) 87 76 #endif 77 78 #define MC68681_WRITE( _base, _reg, _data ) \ 79 *((volatile unsigned char *)_base+_reg) = (_data) 80 81 #define MC68681_READ( _base, _reg ) \ 82 *(((volatile unsigned char *)_base+_reg)) 83 84 85 86 #define MC68681_CLEAR 0x00 87 88 #define MC68681_PORT_A 0 89 #define MC68681_PORT_B 1 90 91 /* 92 * DUART Command Register Definations: 93 * 94 * MC68681_COMMAND_REG_A,MC68681_COMMAND_REG_B 95 */ 96 #define MC68681_MODE_REG_ENABLE_RX 0x01 97 #define MC68681_MODE_REG_DISABLE_RX 0x02 98 #define MC68681_MODE_REG_ENABLE_TX 0x04 99 #define MC68681_MODE_REG_DISABLE_TX 0x08 100 #define MC68681_MODE_REG_RESET_MR_PTR 0x10 101 #define MC68681_MODE_REG_RESET_RX 0x20 102 #define MC68681_MODE_REG_RESET_TX 0x30 103 #define MC68681_MODE_REG_RESET_ERROR 0x40 104 #define MC68681_MODE_REG_RESET_BREAK 0x50 105 #define MC68681_MODE_REG_START_BREAK 0x60 106 #define MC68681_MODE_REG_STOP_BREAK 0x70 107 #define MC68681_MODE_REG_SET_RX_BRG 0x80 108 #define MC68681_MODE_REG_CLEAR_RX_BRG 0x90 109 #define MC68681_MODE_REG_SET_TX_BRG 0xa0 110 #define MC68681_MODE_REG_CLEAR_TX_BRG 0xb0 111 #define MC68681_MODE_REG_SET_STANDBY 0xc0 112 #define MC68681_MODE_REG_SET_ACTIVE 0xd0 113 114 /* 115 * Mode Register Definations 116 * 117 * MC68681_MODE_REG_1A 118 * MC68681_MODE_REG_1B 119 */ 120 #define MC68681_5BIT_CHARS 0x00 121 #define MC68681_6BIT_CHARS 0x01 122 #define MC68681_7BIT_CHARS 0x02 123 #define MC68681_8BIT_CHARS 0x03 124 125 #define MC68681_ODD_PARITY 0x00 126 #define MC68681_EVEN_PARITY 0x04 127 128 #define MC68681_WITH_PARITY 0x00 129 #define MC68681_FORCE_PARITY 0x08 130 #define MC68681_NO_PARITY 0x10 131 #define MC68681_MULTI_DROP 0x18 132 133 #define MC68681_ERR_MODE_CHAR 0x00 134 #define MC68681_ERR_MODE_BLOCK 0x20 135 136 #define MC68681_RX_INTR_RX_READY 0x00 137 #define MC68681_RX_INTR_FFULL 0x40 138 139 #define MC68681_NO_RX_RTS_CTL 0x00 140 #define MC68681_RX_RTS_CTRL 0x80 141 142 143 /* 144 * Mode Register Definations 145 * 146 * MC68681_MODE_REG_2A 147 * MC68681_MODE_REG_2B 148 */ 149 #define MC68681_STOP_BIT_LENGTH__563 0x00 150 #define MC68681_STOP_BIT_LENGTH__625 0x01 151 #define MC68681_STOP_BIT_LENGTH__688 0x02 152 #define MC68681_STOP_BIT_LENGTH__75 0x03 153 #define MC68681_STOP_BIT_LENGTH__813 0x04 154 #define MC68681_STOP_BIT_LENGTH__875 0x05 155 #define MC68681_STOP_BIT_LENGTH__938 0x06 156 #define MC68681_STOP_BIT_LENGTH_1 0x07 157 #define MC68681_STOP_BIT_LENGTH_1_563 0x08 158 #define MC68681_STOP_BIT_LENGTH_1_625 0x09 159 #define MC68681_STOP_BIT_LENGTH_1_688 0x0a 160 #define MC68681_STOP_BIT_LENGTH_1_75 0x0b 161 #define MC68681_STOP_BIT_LENGTH_1_813 0x0c 162 #define MC68681_STOP_BIT_LENGTH_1_875 0x0d 163 #define MC68681_STOP_BIT_LENGTH_1_938 0x0e 164 #define MC68681_STOP_BIT_LENGTH_2 0x0f 165 166 #define MC68681_CTS_ENABLE_TX 0x10 167 #define MC68681_TX_RTS_CTRL 0x20 168 169 #define MC68681_CHANNEL_MODE_NORMAL 0x00 170 #define MC68681_CHANNEL_MODE_ECHO 0x40 171 #define MC68681_CHANNEL_MODE_LOCAL_LOOP 0x80 172 #define MC68681_CHANNEL_MODE_REMOTE_LOOP 0xc0 173 174 /* 175 * Status Register Definations 176 * 177 * MC68681_STATUS_REG_A, MC68681_STATUS_REG_B 178 */ 179 #define MC68681_RX_READY 0x01 180 #define MC68681_FFULL 0x02 181 #define MC68681_TX_READY 0x04 182 #define MC68681_TX_EMPTY 0x08 183 #define MC68681_OVERRUN_ERROR 0x10 184 #define MC68681_PARITY_ERROR 0x20 185 #define MC68681_FRAMING_ERROR 0x40 186 #define MC68681_RECEIVED_BREAK 0x80 187 188 189 /* 190 * Interupt Status Register Definations. 191 * 192 * MC68681_INTERRUPT_STATUS_REG 193 */ 194 195 196 /* 197 * Interupt Mask Register Definations 198 * 199 * MC68681_INTERRUPT_MASK_REG 200 */ 201 #define MC68681_IR_TX_READY_A 0x01 202 #define MC68681_IR_RX_READY_A 0x02 203 #define MC68681_IR_BREAK_A 0x04 204 #define MC68681_IR_COUNTER_READY 0x08 205 #define MC68681_IR_TX_READY_B 0x10 206 #define MC68681_IR_RX_READY_B 0x20 207 #define MC68681_IR_BREAK_B 0x40 208 #define MC68681_IR_INPUT_PORT_CHANGE 0x80 209 210 /* 211 * Status Register Definations. 212 * 213 * MC68681_STATUS_REG_A,MC68681_STATUS_REG_B 214 */ 215 #define MC68681_STATUS_RXRDY 0x01 216 #define MC68681_STATUS_FFULL 0x02 217 #define MC68681_STATUS_TXRDY 0x04 218 #define MC68681_STATUS_TXEMT 0x08 219 #define MC68681_STATUS_OVERRUN_ERROR 0x10 220 #define MC68681_STATUS_PARITY_ERROR 0x20 221 #define MC68681_STATUS_FRAMING_ERROR 0x40 222 #define MC68681_STATUS_RECEIVED_BREAK 0x80 223 224 /* 225 * Definations for the Interrupt Vector Register: 226 * 227 * MC68681_INTERRUPT_VECTOR_REG 228 */ 229 #define MC68681_INTERRUPT_VECTOR_INIT 0x0f 230 231 /* 232 * Definations for the Auxiliary Control Register 233 * 234 * MC68681_AUX_CTRL_REG 235 */ 236 #define MC68681_AUX_BRG_SET1 0x00 237 #define MC68681_AUX_BRG_SET2 0x80 238 239 240 /* 241 * The following Baud rates assume the X1 clock pin is driven with a 242 * 3.6864 MHz signal. If a different frequency is used the DUART channel 243 * is running at the follwoing baud rate: 244 * ((Table Baud Rate)*frequency)/3.6864 MHz 245 */ 246 247 /* 248 * Definations for the Clock Select Register: 249 * 250 * MC68681_CLOCK_SELECT_REG_A,MC68681_CLOCK_SELECT_REG_A 251 * 252 * Note: ACR[7] is the MSB of the Auxiliary Control register 253 * X is the extend bit. 254 * CRA - 0x08 Set Rx BRG Select Extend Bit (X=1) 255 * CRA - 0x09 Clear Rx BRG Select Extend Bit (X=0) 256 * CRB - 0x0a Set Tx BRG Select Extend Bit (X=1) 257 * CRB - 0x0b Clear Tx BRG Select Extend Bit (x=1) 258 */ 259 #define MC68681_BAUD_RATE_MASK_50 0x00 /* ACR[7]=0,X=0 */ 260 /* ARC[7]=1,X=1 */ 261 #define MC68681_BAUD_RATE_MASK_75 0x00 /* ACR[7]=0,X=0 */ 262 /* ARC[7]=1,X=1 */ 263 #define MC68681_BAUD_RATE_MASK_110 0x01 264 #define MC68681_BAUD_RATE_MASK_134_5 0x02 265 #define MC68681_BAUD_RATE_MASK_150 0x03 /* ACR[7]=0,X=0 */ 266 /* ARC[7]=1,X=1 */ 267 #define MC68681_BAUD_RATE_MASK_200 0x03 /* ACR[7]=0,X=0 */ 268 /* ARC[7]=1,X=1 */ 269 #define MC68681_BAUD_RATE_MASK_300 0x04 /* ACR[7]=0,X=0 */ 270 /* ARC[7]=1,X=1 */ 271 #define MC68681_BAUD_RATE_MASK_600 0x05 /* ACR[7]=0,X=0 */ 272 /* ARC[7]=1,X=1 */ 273 #define MC68681_BAUD_RATE_MASK_1050 0x07 /* ACR[7]=0,X=0 */ 274 /* ARC[7]=1,X=1 */ 275 #define MC68681_BAUD_RATE_MASK_1200 0x06 /* ACR[7]=0,X=0 */ 276 /* ARC[7]=1,X=1 */ 277 #define MC68681_BAUD_RATE_MASK_1800 0x0a /* ACR[7]=0,X=0 */ 278 /* ARC[7]=1,X=1 */ 279 #define MC68681_BAUD_RATE_MASK_2400 0x08 /* ACR[7]=0,X=0 */ 280 /* ARC[7]=1,X=1 */ 281 #define MC68681_BAUD_RATE_MASK_3600 0x04 /* ACR[7]=0,X=0 */ 282 /* ARC[7]=1,X=1 */ 283 #define MC68681_BAUD_RATE_MASK_4800 0x09 284 #define MC68681_BAUD_RATE_MASK_7200 0x0a /* ACR[7]=0,X=0 */ 285 /* ARC[7]=1,X=1 */ 286 #define MC68681_BAUD_RATE_MASK_9600 0xbb 287 288 #define MC68681_BAUD_RATE_MASK_14_4K 0x05 /* ACR[7]=0,X=0 */ 289 /* ARC[7]=1,X=1 */ 290 #define MC68681_BAUD_RATE_MASK_19_2K 0xcc /* ACR[7]=1,X=0 */ 291 /* ARC[7]=0,X=1 */ 292 #define MC68681_BAUD_RATE_MASK_28_8K 0x06 /* ACR[7]=0,X=0 */ 293 /* ARC[7]=1,X=1 */ 294 #define MC68681_BAUD_RATE_MASK_38_4K 0xcc /* ACR[7]=0,X=0 */ 295 /* ARC[7]=1,X=1 */ 296 #define MC68681_BAUD_RATE_MASK_57_6K 0x07 /* ACR[7]=0,X=0 */ 297 /* ARC[7]=1,X=1 */ 298 #define MC68681_BAUD_RATE_MASK_115_5K 0x08 299 #define MC68681_BAUD_RATE_MASK_TIMER 0xdd 300 #define MC68681_BAUD_RATE_MASK_TIMER_16X 0xee 301 #define MC68681_BAUD_RATE_MASK_TIMER_1X 0xff 302 303 #endif 304 305 306
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