Ignore:
Timestamp:
Jul 16, 2015, 12:14:32 PM (5 years ago)
Author:
Premysl Houdek <kom541000@…>
Branches:
4.11, master
Children:
7e14385
Parents:
602e395
git-author:
Premysl Houdek <kom541000@…> (07/16/15 12:14:32)
git-committer:
Joel Sherrill <joel.sherrill@…> (07/16/15 18:15:52)
Message:

bsp/tms570: source changes reflecting new headers.

Signed-off-by: Premysl Houdek <kom541000@…>

Location:
c/src/lib/libbsp/arm/tms570/include
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/tms570/include/system-clocks.h

    r602e395 r069560a  
    5050static inline unsigned tms570_timer(void)
    5151{
    52   uint32_t actual_fcr0 = TMS570_RTI.RTIFRC0;
     52  uint32_t actual_fcr0 = TMS570_RTI.CNT[0].FRCx;
    5353  return actual_fcr0;
    5454}
  • c/src/lib/libbsp/arm/tms570/include/tms570-pom.h

    r602e395 r069560a  
    2222
    2323#include <stdint.h>
     24#include <bsp/tms570.h>
    2425
    2526#ifdef __cplusplus
     
    4849#define TMS570_POM_REGADDRMASK    ((1<<23)-1)
    4950
    50 typedef struct tms570_pom_region_t {
    51   uint32_t PROGSTART;
    52   uint32_t OVLSTART;
    53   uint32_t REGSIZE;
    54   uint32_t res0;
    55 } tms570_pom_region_t;
    56 
    57 typedef struct tms570_pom_t {
    58   uint32_t GLBCTRL;                    /* 000h Global Control Register */
    59   uint32_t REV;                        /* 004h Revision ID */
    60   uint32_t CLKCTRL;                    /* 008h Clock Gate Control Register */
    61   uint32_t FLG;                        /* 00Ch Status Register */
    62   uint32_t reserved1[0x1f0/4];
    63   tms570_pom_region_t REG[TMS570_POM_REGIONS]; /* 200h Program Regions */
    64   uint32_t reserved2[0xb00/4];
    65   uint32_t ITCTRL;                     /* F00h Integration Control Register */
    66   uint32_t reserved3[0x09c/4];
    67   uint32_t CLAIMSET;                   /* FA0h Claim Set Register */
    68   uint32_t CLAIMCLR;                   /* FA4h Claim Clear Register */
    69   uint32_t reserved4[0x008/4];
    70   uint32_t LOCKACCESS;                 /* FB0h Lock Access Register */
    71   uint32_t LOCKSTATUS;                 /* FB4h Lock Status Register */
    72   uint32_t AUTHSTATUS;                 /* FB8h Authentication Status Register */
    73   uint32_t reserved5[0x00c/4];
    74   uint32_t DEVID;                      /* FC8h Device ID Register */
    75   uint32_t DEVTYPE;                    /* FCCh Device Type Register */
    76   uint32_t PERIPHERALID4;              /* FD0h Peripheral ID 4 Register */
    77   uint32_t PERIPHERALID5;              /* FD4h Peripheral ID 5 Register */
    78   uint32_t PERIPHERALID6;              /* FD8h Peripheral ID 6 Register */
    79   uint32_t PERIPHERALID7;              /* FDCh Peripheral ID 7 Register */
    80   uint32_t PERIPHERALID0;              /* FE0h Peripheral ID 0 Register */
    81   uint32_t PERIPHERALID1;              /* FE4h Peripheral ID 1 Register */
    82   uint32_t PERIPHERALID2;              /* FE8h Peripheral ID 2 Register */
    83   uint32_t PERIPHERALID3;              /* FECh Peripheral ID 3 Register */
    84   uint32_t COMPONENTID0;               /* FF0h Component ID 0 Register */
    85   uint32_t COMPONENTID1;               /* FF4h Component ID 1 Register */
    86   uint32_t COMPONENTID2;               /* FF8h Component ID 2 Register */
    87   uint32_t COMPONENTID3;               /* FFCh Component ID 3 Register */
    88 } tms570_pom_t;
    89 
    90 #define TMS570_POM (*(volatile tms570_pom_t*)0xffa04000)
    9151
    9252int mem_dump(void *buf, unsigned long start, unsigned long len, int blen);
  • c/src/lib/libbsp/arm/tms570/include/tms570-rti.h

    r602e395 r069560a  
    3030
    3131#include <stdint.h>
     32#include <bsp/tms570.h>
    3233
    3334#ifdef __cplusplus
    3435extern "C" {
    3536#endif /* __cplusplus */
    36 
    37 typedef struct {
    38   uint32_t RTIGCTRL;       /* RTIGlobalControlRegister */
    39   uint32_t RTITBCTRL;      /* RTITimebaseControlRegister */
    40   uint32_t RTICAPCTRL;     /* RTICaptureControlRegister */
    41   uint32_t RTICOMPCTRL;    /* RTICompareControlRegister */
    42   uint32_t RTIFRC0;        /* RTIFreeRunningCounter0Register */
    43   uint32_t RTIUC0;         /* RTIUpCounter0Register */
    44   uint32_t RTICPUC0;       /* RTICompareUpCounter0Register */
    45   uint32_t reserved1 [0x4/4];
    46   uint32_t RTICAFRC0;      /* RTICaptureFreeRunningCounter0Register */
    47   uint32_t RTICAUC0;       /* RTICaptureUpCounter0Register */
    48   uint32_t reserved2 [0x8/4];
    49   uint32_t RTIFRC1;        /* RTIFreeRunningCounter1Register */
    50   uint32_t RTIUC1;         /* RTIUpCounter1Register */
    51   uint32_t RTICPUC1;       /* RTICompareUpCounter1Register */
    52   uint32_t reserved3 [0x4/4];
    53   uint32_t RTICAFRC1;      /* RTICaptureFreeRunningCounter1Register */
    54   uint32_t RTICAUC1;       /* RTICaptureUpCounter1Register */
    55   uint32_t reserved4 [0x8/4];
    56   uint32_t RTICOMP0;       /* RTICompare0Register */
    57   uint32_t RTIUDCP0;       /* RTIUpdateCompare0Register */
    58   uint32_t RTICOMP1;       /* RTICompare1Register */
    59   uint32_t RTIUDCP1;       /* RTIUpdateCompare1Register */
    60   uint32_t RTICOMP2;       /* RTICompare2Register */
    61   uint32_t RTIUDCP2;       /* RTIUpdateCompare2Register */
    62   uint32_t RTICOMP3;       /* RTICompare3Register */
    63   uint32_t RTIUDCP3;       /* RTIUpdateCompare3Register */
    64   uint32_t RTITBLCOMP;     /* RTITimebaseLowCompareRegister */
    65   uint32_t RTITBHCOMP;     /* RTITimebaseHighCompareRegister */
    66   uint32_t reserved5 [0x8/4];
    67   uint32_t RTISETINTENA;   /* RTISetInterruptEnableRegister */
    68   uint32_t RTICLEARINTENA; /* RTIClearInterruptEnableRegister */
    69   uint32_t RTIINTFLAG;     /* RTIInterruptFlagRegister */
    70   uint32_t reserved6 [0x4/4];
    71   uint32_t RTIDWDCTRL;     /* DigitalWatchdogControlRegister */
    72   uint32_t RTIDWDPRLD;     /* DigitalWatchdogPreloadRegister */
    73   uint32_t RTIWDSTATUS;    /* WatchdogStatusRegister */
    74   uint32_t RTIWDKEY;       /* RTIWatchdogKeyRegister */
    75   uint32_t RTIDWDCNTR;     /* RTIDigitalWatchdogDownCounterRegister */
    76   uint32_t RTIWWDRXNCTRL;  /* DigitalWindowedWatchdogReactionControlRegister */
    77   uint32_t RTIWWDSIZECTRL; /* DigitalWindowedWatchdogWindowSizeControlRegister */
    78   uint32_t RTIINTCLRENABLE;/* RTICompareInterruptClearEnableRegister */
    79   uint32_t RTICOMP0CLR;    /* RTICompare0ClearRegister */
    80   uint32_t RTICOMP1CLR;    /* RTICompare1ClearRegister */
    81   uint32_t RTICOMP2CLR;    /* RTICompare2ClearRegister */
    82   uint32_t RTICOMP3CLR;    /* RTICompare3ClearRegister */
    83 }tms570_rti_t;
    84 
    85 #define TMS570_RTI (*(volatile tms570_rti_t*)0xFFFFFC00)
    8637
    8738/** @} */
  • c/src/lib/libbsp/arm/tms570/include/tms570-sci.h

    r602e395 r069560a  
    3131#include <rtems.h>
    3232#include <stdint.h>
     33#include <bsp/tms570.h>
    3334
    3435#ifdef __cplusplus
    3536extern "C" {
    3637#endif /* __cplusplus */
    37 
    38 typedef struct {
    39   uint32_t SCIGCR0;         /*SCIGlobalControlRegister0*/
    40   uint32_t SCIGCR1;         /*SCIGlobalControlRegister1*/
    41   uint32_t reserved1 [0x4/4];
    42   uint32_t SCISETINT;       /*SCISetInterruptRegister*/
    43   uint32_t SCICLEARINT;     /*SCIClearInterruptRegister*/
    44   uint32_t SCISETINTLVL;    /*SCISetInterruptLevelRegister*/
    45   uint32_t SCICLEARINTLVL;  /*SCIClearInterruptLevelRegister*/
    46   uint32_t SCIFLR;          /*SCIFlagsRegister*/
    47   uint32_t SCIINTVECT0;     /*SCIInterruptVectorOffset0*/
    48   uint32_t SCIINTVECT1;     /*SCIInterruptVectorOffset1*/
    49   uint32_t SCIFORMAT;       /*SCIFormatControlRegister*/
    50   uint32_t BRS;             /*BaudRateSelectionRegister*/
    51   uint32_t SCIED;           /*ReceiverEmulationDataBuffer*/
    52   uint32_t SCIRD;           /*ReceiverDataBuffer*/
    53   uint32_t SCITD;           /*TransmitDataBuffer*/
    54   uint32_t SCIPIO0;         /*SCIPinI/OControlRegister0*/
    55   uint32_t SCIPIO1;         /*SCIPinI/OControlRegister1*/
    56   uint32_t SCIPIO2;         /*SCIPinI/OControlRegister2*/
    57   uint32_t SCIPIO3;         /*SCIPinI/OControlRegister3*/
    58   uint32_t SCIPIO4;         /*SCIPinI/OControlRegister4*/
    59   uint32_t SCIPIO5;         /*SCIPinI/OControlRegister5*/
    60   uint32_t SCIPIO6;         /*SCIPinI/OControlRegister6*/
    61   uint32_t SCIPIO7;         /*SCIPinI/OControlRegister7*/
    62   uint32_t SCIPIO8;         /*SCIPinI/OControlRegister8*/
    63   uint32_t reserved2 [0x30/4];
    64   uint32_t IODFTCTRL;       /*Input/OutputErrorEnableRegister*/
    65 }tms570_sci_t;
    66 
    67 #define TMS570_SCI (*(volatile tms570_sci_t*)0xFFF7E400U)
    68 #define TMS570_SCI2 (*(volatile tms570_sci_t*)0xFFF7E500U)
    6938
    7039/** @} */
  • c/src/lib/libbsp/arm/tms570/include/tms570-vim.h

    r602e395 r069560a  
    3030#include <rtems.h>
    3131#include <stdint.h>
     32#include <bsp/tms570.h>
    3233
    3334#ifdef __cplusplus
     
    3536#endif /* __cplusplus */
    3637
    37 typedef struct{
    38     uint32_t PARFLG;            /* InterruptVectorTableParityFlagRegister */
    39     uint32_t PARCTL;            /* InterruptVectorTableParityControlRegister */
    40     uint32_t ADDERR;            /* AddressParityErrorRegister */
    41     uint32_t FBPARERR;          /* Fall-BackAddressParityErrorRegister */
    42     uint32_t reserved1 [0x4/4];
    43     uint32_t IRQINDEX;          /* IRQIndexOffsetVectorRegister */
    44     uint32_t FIQINDEX;          /* FIQIndexOffsetVectorRegister */
    45     uint32_t reserved2 [0x8/4];
    46     uint32_t FIRQPR[3];         /* FIQ/IRQProgramControlRegister0 */
    47     uint32_t reserved3 [0x4/4];
    48     uint32_t INTREQ[3];         /* PendingInterruptReadLocationRegister0 */
    49     uint32_t reserved4 [0x4/4];
    50     uint32_t REQENASET[3];      /* InterruptEnableSetRegister0 */
    51     uint32_t reserved5 [0x4/4];
    52     uint32_t REQENACLR[3];      /* InterruptEnableClearRegister0 */
    53     uint32_t reserved6 [0x4/4];
    54     uint32_t WAKEENASET[3];     /* Wake-upEnableSetRegister0 */
    55     uint32_t reserved7 [0x4/4];
    56     uint32_t WAKEENACLR[3];     /* Wake-upEnableClearRegister0 */
    57     uint32_t reserved8 [0x4/4];
    58     uint32_t IRQVECREG;         /* IRQInterruptVectorRegister */
    59     uint32_t FIQVECREG;         /* FIQInterruptVectorRegister */
    60     uint32_t CAPEVT;            /* CaptureEventRegister */
    61     uint32_t reserved9 [0x4/4];
    62     uint32_t CHANCTRL [0x5c/4]; /* VIM Interrupt Control Register (PARSER ERROR) */
    63 }tms570_vim_t;
    6438
    65 #define TMS570_VIM (*(volatile tms570_vim_t*)0xFFFFFDEC)
    6639
    6740#endif
  • c/src/lib/libbsp/arm/tms570/include/tms570.h

    r602e395 r069560a  
    1 /**
    2  * @file tms570.h
    3  *
    4  * @ingroup tms570
    5  *
    6  * @brief Specific register definitions according to tms570 family boards.
    7  */
     1/* This file is generated by make_central_header.py */
     2/* Current script's version can be found at: */
     3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
    84
    95/*
    10  * Copyright (c) 2015 Taller Technologies.
     6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
    117 *
    12  * @author Martin Galvan <martin.galvan@tallertechnologies.com>
     8 * Czech Technical University in Prague
     9 * Zikova 1903/4
     10 * 166 36 Praha 6
     11 * Czech Republic
    1312 *
    14  * The license and distribution terms for this file may be
    15  * found in the file LICENSE in this distribution or at
    16  * http://www.rtems.org/license/LICENSE.
    17  */
     13 * All rights reserved.
     14 *
     15 * Redistribution and use in source and binary forms, with or without
     16 * modification, are permitted provided that the following conditions are met:
     17 *
     18 * 1. Redistributions of source code must retain the above copyright notice, this
     19 *    list of conditions and the following disclaimer.
     20 * 2. Redistributions in binary form must reproduce the above copyright notice,
     21 *    this list of conditions and the following disclaimer in the documentation
     22 *    and/or other materials provided with the distribution.
     23 *
     24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
     25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
     28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
     33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     34 *
     35 * The views and conclusions contained in the software and documentation are those
     36 * of the authors and should not be interpreted as representing official policies,
     37 * either expressed or implied, of the FreeBSD Project.
     38*/
     39#ifndef LIBBSP_ARM_TMS570
     40#define LIBBSP_ARM_TMS570
     41#include <bsp/ti_herc/reg_adc.h>
     42#include <bsp/ti_herc/reg_ccmsr.h>
     43#include <bsp/ti_herc/reg_crc.h>
     44#include <bsp/ti_herc/reg_dcan.h>
     45#include <bsp/ti_herc/reg_dcc.h>
     46#include <bsp/ti_herc/reg_dma.h>
     47#include <bsp/ti_herc/reg_dmm.h>
     48#include <bsp/ti_herc/reg_efuse.h>
     49#include <bsp/ti_herc/reg_emac.h>
     50#include <bsp/ti_herc/reg_emacm.h>
     51#include <bsp/ti_herc/reg_emif.h>
     52#include <bsp/ti_herc/reg_esm.h>
     53#include <bsp/ti_herc/reg_flash.h>
     54#include <bsp/ti_herc/reg_flex_ray.h>
     55#include <bsp/ti_herc/reg_gio.h>
     56#include <bsp/ti_herc/reg_htu.h>
     57#include <bsp/ti_herc/reg_i2c.h>
     58#include <bsp/ti_herc/reg_iomm.h>
     59#include <bsp/ti_herc/reg_lin.h>
     60#include <bsp/ti_herc/reg_mdio.h>
     61#include <bsp/ti_herc/reg_n2het.h>
     62#include <bsp/ti_herc/reg_pbist.h>
     63#include <bsp/ti_herc/reg_pll.h>
     64#include <bsp/ti_herc/reg_pmm.h>
     65#include <bsp/ti_herc/reg_rti.h>
     66#include <bsp/ti_herc/reg_rtp.h>
     67#include <bsp/ti_herc/reg_sci.h>
     68#include <bsp/ti_herc/reg_tcr.h>
     69#include <bsp/ti_herc/reg_tcram.h>
     70#include <bsp/ti_herc/reg_vim.h>
     71#include <bsp/ti_herc/reg_pom.h>
     72#include <bsp/ti_herc/reg_spi.h>
     73#include <bsp/ti_herc/reg_stc.h>
     74#include <bsp/ti_herc/reg_sys.h>
     75#include <bsp/ti_herc/reg_sys2.h>
     76#include <bsp/ti_herc/reg_pcr.h>
    1877
    19 #ifndef LIBBSP_ARM_TMS570_H
    20 #define LIBBSP_ARM_TMS570_H
    21 
    22 #define SYSECR (*(uint32_t *)0xFFFFFFE0u) /* System Exception Control Register */
    23 #define ESMIOFFHR (*(uint32_t *)0xFFFFF528) /* ESM Interrupt Offset High Register */
    24 #define ESMSR1 (*(uint32_t *)0xFFFFF518u) /* ESM Status Register 1 */
    25 #define ESMSR2 (*(uint32_t *)0xFFFFF51Cu) /* ESM Status Register 2 */
    26 #define ESMSR3 (*(uint32_t *)0xFFFFF520u) /* ESM Status Register 3 */
    27 #define ESMSR4 (*(uint32_t *)0xFFFFF558u) /* ESM Status Register 4 */
    28 
    29 #define SYSECR_RESET 0x80000u
    30 
    31 #endif /* LIBBSP_ARM_TMS570_H */
     78#define TMS570_ADC1 (*(volatile tms570_adc_t*)0xFFF7C000)
     79#define TMS570_ADC2 (*(volatile tms570_adc_t*)0xFFF7C200)
     80#define TMS570_CCMSR (*(volatile tms570_ccmsr_t*)0XFFFFF600)
     81#define TMS570_CRC (*(volatile tms570_crc_t*)0xFE000000)
     82#define TMS570_DCAN1 (*(volatile tms570_dcan_t*)0xFFF7DC00)
     83#define TMS570_DCAN2 (*(volatile tms570_dcan_t*)0xFFF7DE00)
     84#define TMS570_DCAN3 (*(volatile tms570_dcan_t*)0xFFF7E000)
     85#define TMS570_DCC1 (*(volatile tms570_dcc_t*)0xFFFFEC00)
     86#define TMS570_DCC2 (*(volatile tms570_dcc_t*)0xFFFFF400)
     87#define TMS570_DMA (*(volatile tms570_dma_t*)0xFFFFF000)
     88#define TMS570_DMM (*(volatile tms570_dmm_t*)0xFFFFF700)
     89#define TMS570_EFUSE (*(volatile tms570_efuse_t*)0XFFF8C01C)
     90#define TMS570_EMAC (*(volatile tms570_emac_t*)0xFCF78900)
     91#define TMS570_EMACM (*(volatile tms570_emacm_t*)0xFCF78000)
     92#define TMS570_EMIF (*(volatile tms570_emif_t*)0xFCFFE800)
     93#define TMS570_ESM (*(volatile tms570_esm_t*)0XFFFFF500)
     94#define TMS570_FLASH (*(volatile tms570_flash_t*)0XFFF87000)
     95#define TMS570_FLEX_RAY (*(volatile tms570_flex_ray_t*)0xFFF7C800)
     96#define TMS570_GIO (*(volatile tms570_gio_t*)0xFFF7BC00)
     97#define TMS570_GIO_PORTA (*(volatile tms570_gio_port_t*)0xFFF7BC34)
     98#define TMS570_GIO_PORTB (*(volatile tms570_gio_port_t*)0xFFF7BC54)
     99#define TMS570_GIO_PORTC (*(volatile tms570_gio_port_t*)0xFFF7BC74)
     100#define TMS570_GIO_PORTD (*(volatile tms570_gio_port_t*)0xFFF7BC94)
     101#define TMS570_GIO_PORTE (*(volatile tms570_gio_port_t*)0xFFF7BCB4)
     102#define TMS570_GIO_PORTF (*(volatile tms570_gio_port_t*)0xFFF7BCD4)
     103#define TMS570_GIO_PORTG (*(volatile tms570_gio_port_t*)0xFFF7BCF4)
     104#define TMS570_GIO_PORTH (*(volatile tms570_gio_port_t*)0xFFF7BD14)
     105#define TMS570_HTU1 (*(volatile tms570_htu_t*)0xFFF7A400)
     106#define TMS570_HTU2 (*(volatile tms570_htu_t*)0xFFF7A500)
     107#define TMS570_I2C (*(volatile tms570_i2c_t*)0xFFF7D400)
     108#define TMS570_IOMM (*(volatile tms570_iomm_t*)0XFFFFEA00)
     109#define TMS570_PINMUX (*(volatile tms570_pinmux_t*)0xFFFFEB10)
     110#define TMS570_LIN (*(volatile tms570_lin_t*)0xFFF7E400)
     111#define TMS570_MDIO (*(volatile tms570_mdio_t*)0xFCF78900)
     112#define TMS570_NHET1 (*(volatile tms570_nhet_t*)0xFFF7B800)
     113#define TMS570_NHET2 (*(volatile tms570_nhet_t*)0xFFF7B900)
     114#define TMS570_PBIST (*(volatile tms570_pbist_t*)0xFFFFE400)
     115#define TMS570_PLL (*(volatile tms570_pll_t*)0XFFFFE100)
     116#define TMS570_PMM (*(volatile tms570_pmm_t*)0xFFFF0000)
     117#define TMS570_RTI (*(volatile tms570_rti_t*)0xFFFFFC00)
     118#define TMS570_RTP (*(volatile tms570_rtp_t*)0xFFFFFA00)
     119#define TMS570_SCI (*(volatile tms570_sci_t*)0xFFF7E500)
     120#define TMS570_TCR (*(volatile tms570_tcr_t*)0xFFF7C800)
     121#define TMS570_TCRAM1 (*(volatile tms570_tcram_t*)0xFFFFF800)
     122#define TMS570_TCRAM2 (*(volatile tms570_tcram_t*)0xFFFFF900)
     123#define TMS570_VIM (*(volatile tms570_vim_t*)0XFFFFFDEC)
     124#define TMS570_POM (*(volatile tms570_pom_t*)0XFFA04000)
     125#define TMS570_SPI (*(volatile tms570_spi_t*)0xFFF7F400)
     126#define TMS570_STC (*(volatile tms570_stc_t*)0xFFFFE600)
     127#define TMS570_SYS1 (*(volatile tms570_sys1_t*)0xFFFFFF00)
     128#define TMS570_SYS2 (*(volatile tms570_sys2_t*)0xFFFFE100)
     129#define TMS570_PCR (*(volatile tms570_pcr_t*)0xFFFFE000)
     130#endif /* LIBBSP_ARM_TMS570 */
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