Changeset 0656a00a in rtems


Ignore:
Timestamp:
Jan 23, 2014, 9:56:31 AM (5 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
f241977
Parents:
a502d677
git-author:
Ralf Kirchner <ralf.kirchner@…> (01/23/14 09:56:31)
git-committer:
Sebastian Huber <sebastian.huber@…> (03/13/14 15:10:53)
Message:

bsp/arm: Add CP15 methods

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/arm/shared/include/arm-cp15.h

    ra502d677 r0656a00a  
    573573 */
    574574
     575/* Read cache type register CTR */
    575576static inline uint32_t arm_cp15_get_cache_type(void)
    576577{
     
    588589}
    589590
     591/* Read size of smallest cache line of all instruction/data caches controlled by the processor */
    590592static inline uint32_t arm_cp15_get_min_cache_line_size(void)
    591593{
     
    595597
    596598  if (format == 0x4) {
     599    /* ARMv7 format */
    597600    mcls = (1U << (ct & 0xf)) * 4;
    598601  } else if (format == 0x0) {
     602    /* ARMv6 format */
    599603    uint32_t mask = (1U << 12) - 1;
    600604    uint32_t dcls = (ct >> 12) & mask;
     
    607611}
    608612
     613/* Read size of smallest data cache lines */
     614static inline uint32_t arm_cp15_get_data_cache_line_size(void)
     615{
     616  uint32_t mcls = 0;
     617  uint32_t ct = arm_cp15_get_cache_type();
     618  uint32_t format = (ct >> 29) & 0x7U;
     619
     620  if (format == 0x4) {
     621    /* ARMv7 format */
     622    mcls = (1U << ((ct & 0xf0000) >> 16)) * 4;
     623  } else if (format == 0x0) {
     624    /* ARMv6 format */
     625    uint32_t mask = (1U << 12) - 1;
     626    mcls = (ct >> 12) & mask;
     627  }
     628
     629  return mcls;
     630}
     631
     632/* Read size of smallest instruction cache lines */
     633static inline uint32_t arm_cp15_get_instruction_cche_line_size(void)
     634{
     635  uint32_t mcls = 0;
     636  uint32_t ct = arm_cp15_get_cache_type();
     637  uint32_t format = (ct >> 29) & 0x7U;
     638
     639  if (format == 0x4) {
     640    /* ARMv7 format */
     641    mcls = (1U << (ct & 0x0000f)) * 4;
     642  } else if (format == 0x0) {
     643    /* ARMv6 format */
     644    uint32_t mask = (1U << 12) - 1;
     645    mcls = ct & mask;;
     646  }
     647
     648  return mcls;
     649}
     650
    609651/* CCSIDR, Cache Size ID Register */
    610652
     
    641683}
    642684
     685static inline uint32_t arm_cp15_get_level_of_cache_coherency(const uint32_t clidr)
     686{
     687  return( (clidr & 0x7000000) >> 23 );
     688}
     689
    643690/* CSSELR, Cache Size Selection Register */
    644691
     
    680727    ARM_SWITCH_TO_ARM
    681728    "mcr p15, 0, %[sbz], c7, c7, 0\n"
     729    ARM_SWITCH_BACK
     730    : ARM_SWITCH_OUTPUT
     731    : [sbz] "r" (sbz)
     732    : "memory"
     733  );
     734}
     735
     736/* ICIALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable */
     737
     738static inline void arm_cp15_instruction_cache_inner_shareable_invalidate_all(void)
     739{
     740  ARM_SWITCH_REGISTERS;
     741  uint32_t sbz = 0;
     742
     743  __asm__ volatile (
     744    ARM_SWITCH_TO_ARM
     745    "mcr p15, 0, %[sbz], c7, c1, 0\n"
     746    ARM_SWITCH_BACK
     747    : ARM_SWITCH_OUTPUT
     748    : [sbz] "r" (sbz)
     749    : "memory"
     750  );
     751}
     752
     753/* BPIALLIS, Branch Predictor Invalidate All, Inner Shareable */
     754
     755static inline void arm_cp15_branch_predictor_inner_shareable_invalidate_all(void)
     756{
     757  ARM_SWITCH_REGISTERS;
     758  uint32_t sbz = 0;
     759
     760  __asm__ volatile (
     761    ARM_SWITCH_TO_ARM
     762    "mcr p15, 0, %[sbz], c7, c1, 6\n"
     763    ARM_SWITCH_BACK
     764    : ARM_SWITCH_OUTPUT
     765    : [sbz] "r" (sbz)
     766    : "memory"
     767  );
     768}
     769
     770/* BPIALL, Branch Predictor Invalidate All */
     771
     772static inline void arm_cp15_branch_predictor_invalidate_all(void)
     773{
     774  ARM_SWITCH_REGISTERS;
     775  uint32_t sbz = 0;
     776
     777  __asm__ volatile (
     778    ARM_SWITCH_TO_ARM
     779    "mcr p15, 0, %[sbz], c7, c5, 6\n"
    682780    ARM_SWITCH_BACK
    683781    : ARM_SWITCH_OUTPUT
     
    856954    : "memory"
    857955  );
    858 
    859956}
    860957
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