Changeset 0626dba in rtems for c/src/lib/libbsp/sh
- Timestamp:
- 10/15/14 19:20:14 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- d4ab6611
- Parents:
- 694debe
- git-author:
- Joel Sherrill <joel.sherrill@…> (10/15/14 19:20:14)
- git-committer:
- Joel Sherrill <joel.sherrill@…> (10/16/14 13:58:49)
- Location:
- c/src/lib/libbsp/sh
- Files:
-
- 1 added
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/sh/gensh1/include/bsp.h
r694debe r0626dba 1 1 /* 2 * This include file contains all board IO definitions.3 *4 2 * generic sh1 5 3 * 4 * This include file contains all board IO definitions. 5 */ 6 7 /* 6 8 * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) 7 9 * … … 69 71 70 72 /* 71 * NOTE: Use the standard Clock driver entry73 * BSP methods that cross file boundaries. 72 74 */ 75 void bsp_hw_init(void); 73 76 74 77 #ifdef __cplusplus -
c/src/lib/libbsp/sh/gensh2/include/bsp.h
r694debe r0626dba 1 1 /* 2 * This include file contains all board IO definitions.3 *4 2 * generic sh2 5 3 * 4 * This include file contains all board IO definitions. 5 */ 6 7 /* 6 8 * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) 7 9 * … … 46 48 #include <bsp/default-initial-extension.h> 47 49 48 #if 0 49 #include <rtems/devnull.h> 50 #define BSP_CONSOLE_DEVNAME "/dev/null" 51 #define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVNULL_DRIVER_TABLE_ENTRY 52 #else 50 #include <termios.h> /* for tcflag_t */ 51 53 52 #include <sh/sci.h> 53 54 #if 1 54 55 /* FIXME: 55 56 * These definitions will be no longer necessary if the old … … 67 68 * Defined in the linker script 'linkcmds' 68 69 */ 69 70 70 extern void *CPU_Interrupt_stack_low; 71 71 extern void *CPU_Interrupt_stack_high; 72 72 73 73 /* 74 * Device Driver Table Entries74 * BSP methods that cross file boundaries. 75 75 */ 76 77 /* 78 * NOTE: Use the standard Clock driver entry 79 */ 76 void bsp_hw_init(void); 77 extern int _sci_get_brparms( 78 tcflag_t cflag, 79 unsigned char *smr, 80 unsigned char *brr 81 ); 80 82 81 83 #ifdef __cplusplus -
c/src/lib/libbsp/sh/gensh4/hw_init/hw_init.c
r694debe r0626dba 1 1 /* 2 2 * SMFD board hardware initialization. 3 * 3 */ 4 5 /* 4 6 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia 5 7 * Author: Victor V. Vengerov <vvv@oktet.ru> 6 * 8 * Alexandra Kossovsky <sasha@oktet.ru> 7 9 * 8 10 * The license and distribution terms for this file may be … … 26 28 * This function should not access the memory! It should be compiled 27 29 * with -fomit-frame-pointer to avoid stack access. 28 * 29 * PARAMETERS: 30 * none 31 * 32 * RETURNS: 33 * none 34 */ 35 void 36 early_hw_init(void) 30 */ 31 void early_hw_init(void) 37 32 { 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 33 /* Explicitly turn off the MMU */ 34 write32(0, SH7750_MMUCR); 35 36 /* Disable instruction and operand caches */ 37 write32(0, SH7750_CCR); 38 39 /* Setup Clock Generator */ 40 /* 41 * Input clock frequency is 16 MHz, MD0=1, 42 * CPU clock frequency already selected to 96MHz. 43 * Bus clock frequency should be set to 48 MHz, therefore divider 2 44 * should be applied (bus frequency is 48 MHz, clock period is 20.84ns). 45 * Peripheral frequency should be set to 24 MHz, therefore divider 4 46 * should be used. 47 */ 48 /* Prepare watchdog timer for frequency changing */ 49 write16((read8(SH7750_WTCSR) & ~SH7750_WTCSR_TME) | 50 SH7750_WTCSR_KEY, SH7750_WTCSR); 51 write16(SH7750_WTCSR_MODE_IT | SH7750_WTCSR_CKS_DIV4096 | 52 SH7750_WTCSR_KEY, SH7750_WTCSR); 53 54 /* Turn PLL1 on */ 55 write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT); 56 write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL1EN, SH7750_FRQCR); 57 58 /* Perform Frequency Selection */ 59 write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT); 60 write16(SH7750_FRQCR_CKOEN | SH7750_FRQCR_PLL1EN | 61 SH7750_FRQCR_IFCDIV1 | SH7750_FRQCR_BFCDIV2 | SH7750_FRQCR_PFCDIV4, 62 SH7750_FRQCR); 63 64 /* Turn PLL2 on */ 65 write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT); 66 write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL2EN, SH7750_FRQCR); 67 68 /* Bus State Controller Initialization */ 69 /* 70 * Area assignments: 71 * Area 0: Flash memory, SRAM interface 72 * Area 1: GDC 73 * Area 2: SDRAM 74 * Area 3-6: unused 75 */ 76 write32( 77 /* Pull-ups (IPUP, OPUP) enabled */ 78 /* No Byte-Control SRAM mode for Area 1 and Area 3 */ 79 SH7750_BCR1_BREQEN | /* Enable external bus requests */ 80 /* No Partial Sharing Mode */ 81 /* No MPX interface */ 82 /* Memory and Control Signals are in HiZ */ 83 SH7750_BCR1_A0BST_SRAM | /* No burst ROM in flash */ 84 SH7750_BCR1_A5BST_SRAM | /* Area 5 is not in use */ 85 SH7750_BCR1_A6BST_SRAM | /* Area 6 is not in use */ 86 SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM /* Select Area 2 SDRAM type */ 87 /* Area 5,6 programmed as a SRAM interface (not PCMCIA) */, 88 SH7750_BCR1); 89 90 write16( 91 (SH7750_BCR2_SZ_8 << SH7750_BCR2_A0SZ_S) | /* These bits is read-only 92 and set during reset */ 93 (SH7750_BCR2_SZ_32 << SH7750_BCR2_A6SZ_S) | /* Area 6 not used */ 94 (SH7750_BCR2_SZ_32 << SH7750_BCR2_A5SZ_S) | /* Area 5 not used */ 95 (SH7750_BCR2_SZ_32 << SH7750_BCR2_A4SZ_S) | /* Area 4 not used */ 96 (SH7750_BCR2_SZ_32 << SH7750_BCR2_A3SZ_S) | /* Area 3 not used */ 97 (SH7750_BCR2_SZ_32 << SH7750_BCR2_A2SZ_S) | /* SDRAM is 32-bit width */ 98 (SH7750_BCR2_SZ_32 << SH7750_BCR2_A1SZ_S) | /* GDC is 32-bit width */ 99 SH7750_BCR2_PORTEN, /* Use D32-D51 as a port */ 100 SH7750_BCR2); 101 102 write32( 103 (0 << SH7750_WCR1_DMAIW_S) | /* 0 required for SDRAM RAS down mode */ 104 (7 << SH7750_WCR1_A6IW_S) | /* Area 6 not used */ 105 (7 << SH7750_WCR1_A5IW_S) | /* Area 5 not used */ 106 (7 << SH7750_WCR1_A4IW_S) | /* Area 4 not used */ 107 (7 << SH7750_WCR1_A3IW_S) | /* Area 3 not used */ 108 (1 << SH7750_WCR1_A2IW_S) | /* 1 idle cycles inserted between acc */ 109 (7 << SH7750_WCR1_A1IW_S) | /* Don't have GDC specs... Set safer. */ 110 (1 << SH7750_WCR1_A0IW_S), /* 1 idle cycles inserted between acc */ 111 SH7750_WCR1); 112 113 write32( 114 (SH7750_WCR2_WS15 << SH7750_WCR2_A6W_S) | /* Area 6 not used */ 115 (SH7750_WCR2_BPWS7 << SH7750_WCR2_A6B_S) | 116 (SH7750_WCR2_WS15 << SH7750_WCR2_A5W_S) | /* Area 5 not used */ 117 (SH7750_WCR2_BPWS7 << SH7750_WCR2_A5B_S) | 118 (SH7750_WCR2_WS15 << SH7750_WCR2_A4W_S) | /* Area 4 not used */ 119 (SH7750_WCR2_WS15 << SH7750_WCR2_A3W_S) | /*Area 3 not used*/ 120 (SH7750_WCR2_SDRAM_CAS_LAT2 << SH7750_WCR2_A2W_S) | /* SDRAM CL = 2 */ 121 (SH7750_WCR2_WS15 << SH7750_WCR2_A1W_S) | /* Area 1 (GDC) 122 requirements not known*/ 123 (SH7750_WCR2_WS6 << SH7750_WCR2_A0W_S) | /* 4 wait states required 124 at 48MHz for 70ns mem., 125 set closest greater */ 126 (SH7750_WCR2_BPWS7 << SH7750_WCR2_A0B_S), /* burst mode disabled for 127 Area 0 flash ROM */ 128 SH7750_WCR2); 129 write32( 130 SH7750_WCR3_A6S | /* Area 6 not used */ 131 (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A6H_S) | 132 SH7750_WCR3_A5S | /* Area 5 not used */ 133 (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A5H_S) | 134 SH7750_WCR3_A4S | /* Area 4 not used */ 135 (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A4H_S) | 136 SH7750_WCR3_A3S | /* Area 3 not used */ 137 (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A3H_S) | 138 SH7750_WCR3_A2S | /* SDRAM - ignored */ 139 (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A2H_S) | 140 SH7750_WCR3_A1S | /* GDC - unknown, set max*/ 141 (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A1H_S) | 142 0 | /* flash ROM - no write strobe setup time required */ 143 (SH7750_WCR3_DHWS_0 << SH7750_WCR3_A0H_S), 144 SH7750_WCR3); 145 146 #define MCRDEF \ 147 /* SH7750_MCR_RASD | */ /* Set RAS Down mode */ \ 148 (SH7750_MCR_TRC_0 | SH7750_MCR_TRAS_SDRAM_TRC_4 | \ 149 /* RAS precharge time is 63ns; it corresponds to 4 clocks */ \ 150 /* TCAS valid only for DRAM interface */ \ 151 SH7750_MCR_TPC_SDRAM_1 | /* TPC = 20ns = 1 clock */ \ 152 SH7750_MCR_RCD_SDRAM_2 | /* RCD = 21ns = 2 clock */ \ 153 /* After write, next active command is not issued for a period of \ 154 TPC + TRWL. SDRAM specifies that it should be BL+Trp clocks when \ 155 CL=2. Trp = 20ns = 1clock; BL=8. Therefore we should wait 9 \ 156 clocks. Don't know why, but 6 clocks (TRWL=5 and TPC=1) seems \ 157 working. May be, something wrong in documentation? */ \ 158 SH7750_MCR_TRWL_5 | /* TRWL = 5 clock */ \ 159 SH7750_MCR_BE | /* Always enabled for SDRAM */ \ 160 SH7750_MCR_SZ_32 | /* Memory data size is 32 bit */ \ 161 (4 << SH7750_MCR_AMX_S) | /* Select memory device type */ \ 162 SH7750_MCR_RFSH | /* Refresh is performed */ \ 163 SH7750_MCR_RMODE_NORMAL) /* Auto-Refresh mode */ 164 165 /* Clear refresh timer counter */ 166 write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT); 167 168 /* Time between auto-refresh commands is 15.6 microseconds; refresh 169 timer counter frequency is 12 MHz; 1.56e-5*1.2e7= 187.2, therefore 170 program the refresh timer divider to 187 */ 171 write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR); 172 173 /* Clear refresh counter */ 174 write16(SH7750_RFCR_KEY | 0, SH7750_RFCR); 175 176 /* Select refresh counter base frequency as bus frequency/4 = 12 MHz */ 177 write16(SH7750_RTCSR_CKS_CKIO_DIV4 | SH7750_RTCSR_KEY, SH7750_RTCSR); 178 179 /* Initialize Memory Control Register; disable refresh */ 180 write32((MCRDEF & ~SH7750_MCR_RFSH) | SH7750_MCR_PALL, SH7750_MCR); 181 182 /* SDRAM power-up initialization require 100 microseconds delay after 183 stable power and clock fed; 100 microseconds corresponds to 7 refresh 184 intervals */ 185 while (read16(SH7750_RFCR) <= 7); 186 187 /* Clear refresh timer counter */ 188 write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT); 189 190 /* Clear refresh counter */ 191 write16(SH7750_RFCR_KEY | 0, SH7750_RFCR); 192 193 /* Execute Precharge All command */ 194 write32(0, SH7750_SDRAM_MODE_A2_32BIT(0)); 195 196 /* Initialize Memory Control Register; enable refresh, prepare to 197 SDRAM mode register setting */ 198 write32(MCRDEF | SH7750_MCR_MRSET, SH7750_MCR); 199 200 /* Wait until at least 2 auto-refresh commands to be executed */ 201 while (read16(SH7750_RFCR) <= 10); 202 203 /* SDRAM data width is 32 bit (4 bytes), cache line size is 32 bytes, 204 therefore burst length is 8 (32 / 4) */ 205 write8(0,SH7750_SDRAM_MODE_A2_32BIT( 206 SDRAM_MODE_BL_8 | 207 SDRAM_MODE_BT_SEQ | /* Only sequential burst mode supported 208 in SH7750 */ 209 SDRAM_MODE_CL_2 | /* CAS latency is 2 */ 210 SDRAM_MODE_OPC_BRBW) /* Burst read/burst write */ 211 ); 212 /* Bus State Controller initialized now */ 213 214 /* Disable DMA controller */ 215 write32(0, SH7750_DMAOR); 216 217 /* I/O port setup */ 218 /* Configure all port bits as output - to fasciliate debugging */ 219 write32( 220 SH7750_PCTRA_PBOUT(0) | SH7750_PCTRA_PBOUT(1) | 221 SH7750_PCTRA_PBOUT(2) | SH7750_PCTRA_PBOUT(3) | 222 SH7750_PCTRA_PBOUT(4) | SH7750_PCTRA_PBOUT(5) | 223 SH7750_PCTRA_PBOUT(6) | SH7750_PCTRA_PBOUT(7) | 224 SH7750_PCTRA_PBOUT(8) | SH7750_PCTRA_PBOUT(9) | 225 SH7750_PCTRA_PBOUT(10) | SH7750_PCTRA_PBOUT(11) | 226 SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) | 227 SH7750_PCTRA_PBOUT(14) | SH7750_PCTRA_PBOUT(15), 228 SH7750_PCTRA); 229 write32( 230 SH7750_PCTRB_PBOUT(16) | SH7750_PCTRB_PBOUT(17) | 231 SH7750_PCTRB_PBOUT(18) | SH7750_PCTRB_PBOUT(19), 232 SH7750_PCTRB); 233 /* Clear data in port */ 234 write32(0, SH7750_PDTRA); 235 write32(0, SH7750_PDTRB); 236 237 /* Interrupt Controller Initialization */ 238 write16(SH7750_ICR_IRLM, SH7750_ICR); /* IRLs serves as an independent 239 interrupt request lines */ 240 /* Mask all requests at this time */ 241 write16( 242 (0 << SH7750_IPRA_TMU0_S) | 243 (0 << SH7750_IPRA_TMU1_S) | 244 (0 << SH7750_IPRA_TMU2_S) | 245 (0 << SH7750_IPRA_RTC_S), 246 SH7750_IPRA); 247 write16( 248 (0 << SH7750_IPRB_WDT_S) | 249 (0 << SH7750_IPRB_REF_S) | 250 (0 << SH7750_IPRB_SCI1_S), 251 SH7750_IPRB); 252 write16( 253 (0 << SH7750_IPRC_GPIO_S) | 254 (0 << SH7750_IPRC_DMAC_S) | 255 (0 << SH7750_IPRC_SCIF_S) | 256 (0 << SH7750_IPRC_HUDI_S), 257 SH7750_IPRC); 263 258 264 259 } … … 270 265 void bsp_cache_on(void) 271 266 { 272 switch (boot_mode) 273 { 274 case SH4_BOOT_MODE_FLASH: 275 write32(SH7750_CCR_ICI | SH7750_CCR_ICE | 276 SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE, 277 SH7750_CCR); 278 break; 279 case SH4_BOOT_MODE_IPL: 280 __asm__ volatile ( 281 "mov #6, r0\n" 282 "xor r4, r4\n" 283 "trapa #0x3f\n" 284 : : : "r0", "r4"); 285 break; 286 default: /* unreachable */ 287 break; 288 } 267 switch (boot_mode) { 268 case SH4_BOOT_MODE_FLASH: 269 write32(SH7750_CCR_ICI | SH7750_CCR_ICE | 270 SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE, 271 SH7750_CCR); 272 break; 273 case SH4_BOOT_MODE_IPL: 274 __asm__ volatile ( 275 "mov #6, r0\n" 276 "xor r4, r4\n" 277 "trapa #0x3f\n" 278 : : : "r0", "r4"); 279 break; 280 default: /* unreachable */ 281 break; 282 } 289 283 } -
c/src/lib/libbsp/sh/gensh4/include/bsp.h
r694debe r0626dba 1 1 /* 2 * This include file contains all board IO definitions.3 *4 2 * generic sh4 BSP 5 3 * 4 * This include file contains all board IO definitions. 5 */ 6 7 /* 6 8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia 7 9 * Author: Victor V. Vengerov <vvv@oktet.ru> … … 48 50 #include <bspopts.h> 49 51 #include <bsp/default-initial-extension.h> 52 #include <termios.h> /* for tcflag_t */ 50 53 51 54 #include "rtems/score/sh7750_regs.h" … … 80 83 81 84 /* 82 * NOTE: Use the standard Clock driver entry85 * BSP methods that cross file boundaries. 83 86 */ 87 void bsp_hw_init(void); 88 void early_hw_init(void); 89 void bsp_cache_on(void); 90 extern int _sci_get_brparms( 91 tcflag_t cflag, 92 unsigned char *smr, 93 unsigned char *brr 94 ); 84 95 85 96 #ifdef __cplusplus -
c/src/lib/libbsp/sh/shared/bsphwinit.c
r694debe r0626dba 1 1 /* 2 2 * This is a dummy bsp_hw_init routine. 3 * 4 * COPYRIGHT (c) 1989-2008. 3 */ 4 5 /* 6 * COPYRIGHT (c) 1989-2014. 5 7 * On-Line Applications Research Corporation (OAR). 6 8 * … … 10 12 */ 11 13 14 #include <bsp.h> 15 12 16 void bsp_hw_init( void ) 13 17 { -
c/src/lib/libbsp/sh/shsim/console/console-debugio.c
r694debe r0626dba 2 2 * @file 3 3 * @brief Stub printk() support 4 *5 * This file contains a stub for the required printk() support.6 * It is NOT functional!!!7 4 */ 8 5 … … 28 25 ); 29 26 30 void BSP_output_char_f(char c)27 static void BSP_output_char_f(char c) 31 28 { 32 29 console_outbyte_polled( 0, c ); -
c/src/lib/libbsp/sh/shsim/console/console-io.c
r694debe r0626dba 21 21 #include <bsp/syscall.h> 22 22 23 int errno;24 25 extern int __trap34(int, int, void*, int );26 27 23 /* 28 24 * console_initialize_hardware 29 25 * 30 26 * This routine initializes the console hardware. 31 *32 27 */ 33 34 28 void console_initialize_hardware(void) 35 29 { 36 return;37 30 } 38 31 … … 42 35 * This routine transmits a character using polling. 43 36 */ 44 45 37 void console_outbyte_polled( 46 38 int port, … … 49 41 { 50 42 __trap34 (SYS_write, 1, &ch, 1); 51 return;52 43 } 53 44 … … 57 48 * This routine polls for a character. 58 49 */ 59 60 50 int console_inbyte_nonblocking( 61 51 int port … … 66 56 return __trap34 (SYS_read, 0, &c, 1); 67 57 } 68 69 /* XXX wrong place for this */70 int _sys_exit (int n)71 {72 return __trap34 (SYS_exit, n, 0, 0);73 } -
c/src/lib/libbsp/sh/shsim/include/bsp.h
r694debe r0626dba 1 1 /* 2 * This include file contains all board IO definitions.3 *4 2 * SH-gdb simulator BSP 5 3 * 4 * This include file contains all board IO definitions. 5 */ 6 7 /* 6 8 * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) 7 9 * … … 22 24 #ifndef _BSP_H 23 25 #define _BSP_H 26 27 #ifndef ASM 24 28 25 29 #ifdef __cplusplus … … 47 51 * Defined in the linker script 'linkcmds' 48 52 */ 49 50 53 extern void *CPU_Interrupt_stack_low; 51 54 extern void *CPU_Interrupt_stack_high; 55 56 /* 57 * BSP methods that cross file boundaries. 58 */ 59 int __trap34(int, int, void*, int ); 60 int _sys_exit (int n); 61 void bsp_hw_init(void); 52 62 53 63 #ifdef __cplusplus … … 55 65 #endif 56 66 67 #endif /* !ASM */ 57 68 #endif -
c/src/lib/libbsp/sh/shsim/start/start.S
r694debe r0626dba 19 19 20 20 #include <rtems/asm.h> 21 #include <bsp.h> 21 22 22 23 BEGIN_CODE
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