Changeset 0626dba in rtems


Ignore:
Timestamp:
Oct 15, 2014, 7:20:14 PM (6 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.11, 5, master
Children:
d4ab6611
Parents:
694debe
git-author:
Joel Sherrill <joel.sherrill@…> (10/15/14 19:20:14)
git-committer:
Joel Sherrill <joel.sherrill@…> (10/16/14 13:58:49)
Message:

SH libcpu and libbsp: Fix warnings

Location:
c/src/lib
Files:
1 added
14 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sh/gensh1/include/bsp.h

    r694debe r0626dba  
    11/*
    2  *  This include file contains all board IO definitions.
    3  *
    42 *  generic sh1
    53 *
     4 *  This include file contains all board IO definitions.
     5 */
     6
     7/*
    68 *  Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
    79 *
     
    6971
    7072/*
    71  * NOTE: Use the standard Clock driver entry
     73 * BSP methods that cross file boundaries.
    7274 */
     75void bsp_hw_init(void);
    7376
    7477#ifdef __cplusplus
  • c/src/lib/libbsp/sh/gensh2/include/bsp.h

    r694debe r0626dba  
    11/*
    2  *  This include file contains all board IO definitions.
    3  *
    42 *  generic sh2
    53 *
     4 *  This include file contains all board IO definitions.
     5 */
     6
     7/*
    68 *  Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
    79 *
     
    4648#include <bsp/default-initial-extension.h>
    4749
    48 #if 0
    49 #include <rtems/devnull.h>
    50 #define BSP_CONSOLE_DEVNAME "/dev/null"
    51 #define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVNULL_DRIVER_TABLE_ENTRY
    52 #else
     50#include <termios.h> /* for tcflag_t */
     51
    5352#include <sh/sci.h>
     53
     54#if 1
    5455/* FIXME:
    5556 *   These definitions will be no longer necessary if the old
     
    6768 * Defined in the linker script 'linkcmds'
    6869 */
    69 
    7070extern void *CPU_Interrupt_stack_low;
    7171extern void *CPU_Interrupt_stack_high;
    7272
    7373/*
    74  *  Device Driver Table Entries
     74 * BSP methods that cross file boundaries.
    7575 */
    76 
    77 /*
    78  * NOTE: Use the standard Clock driver entry
    79  */
     76void bsp_hw_init(void);
     77extern int _sci_get_brparms(
     78  tcflag_t      cflag,
     79  unsigned char *smr,
     80  unsigned char *brr
     81);
    8082
    8183#ifdef __cplusplus
  • c/src/lib/libbsp/sh/gensh4/hw_init/hw_init.c

    r694debe r0626dba  
    11/*
    22 * SMFD board hardware initialization.
    3  *
     3 */
     4
     5/*
    46 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
    57 * Author: Victor V. Vengerov <vvv@oktet.ru>
    6  *         Alexandra Kossovsky <sasha@oktet.ru>
     8 *         Alexandra Kossovsky <sasha@oktet.ru>
    79 *
    810 *  The license and distribution terms for this file may be
     
    2628 *     This function should not access the memory! It should be compiled
    2729 *     with -fomit-frame-pointer to avoid stack access.
    28  *
    29  * PARAMETERS:
    30  *     none
    31  *
    32  * RETURNS:
    33  *     none
    34  */
    35 void
    36 early_hw_init(void)
     30 */
     31void early_hw_init(void)
    3732{
    38     /* Explicitly turn off the MMU */
    39     write32(0, SH7750_MMUCR);
    40 
    41     /* Disable instruction and operand caches */
    42     write32(0, SH7750_CCR);
    43 
    44     /* Setup Clock Generator */
    45     /*
    46      * Input clock frequency is 16 MHz, MD0=1,
    47      * CPU clock frequency already selected to 96MHz.
    48      * Bus clock frequency should be set to 48 MHz, therefore divider 2
    49      * should be applied (bus frequency is 48 MHz, clock period is 20.84ns).
    50      * Peripheral frequency should be set to 24 MHz, therefore divider 4
    51      * should be used.
    52      */
    53     /* Prepare watchdog timer for frequency changing */
    54     write16((read8(SH7750_WTCSR) & ~SH7750_WTCSR_TME) |
    55             SH7750_WTCSR_KEY, SH7750_WTCSR);
    56     write16(SH7750_WTCSR_MODE_IT | SH7750_WTCSR_CKS_DIV4096 |
    57             SH7750_WTCSR_KEY, SH7750_WTCSR);
    58 
    59     /* Turn PLL1 on */
    60     write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
    61     write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL1EN, SH7750_FRQCR);
    62 
    63     /* Perform Frequency Selection */
    64     write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
    65     write16(SH7750_FRQCR_CKOEN | SH7750_FRQCR_PLL1EN |
    66             SH7750_FRQCR_IFCDIV1 | SH7750_FRQCR_BFCDIV2 | SH7750_FRQCR_PFCDIV4,
    67             SH7750_FRQCR);
    68 
    69     /* Turn PLL2 on */
    70     write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
    71     write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL2EN, SH7750_FRQCR);
    72 
    73     /* Bus State Controller Initialization */
    74     /*
    75      * Area assignments:
    76      *     Area 0: Flash memory, SRAM interface
    77      *     Area 1: GDC
    78      *     Area 2: SDRAM
    79      *     Area 3-6: unused
    80      */
    81     write32(
    82         /* Pull-ups (IPUP, OPUP) enabled */
    83         /* No Byte-Control SRAM mode for Area 1 and Area 3 */
    84         SH7750_BCR1_BREQEN | /* Enable external bus requests */
    85         /* No Partial Sharing Mode */
    86         /* No MPX interface */
    87         /* Memory and Control Signals are in HiZ */
    88         SH7750_BCR1_A0BST_SRAM | /* No burst ROM in flash */
    89         SH7750_BCR1_A5BST_SRAM | /* Area 5 is not in use */
    90         SH7750_BCR1_A6BST_SRAM | /* Area 6 is not in use */
    91         SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM  /* Select Area 2 SDRAM type */
    92         /* Area 5,6 programmed as a SRAM interface (not PCMCIA) */,
    93         SH7750_BCR1);
    94 
    95     write16(
    96         (SH7750_BCR2_SZ_8 << SH7750_BCR2_A0SZ_S) |  /* These bits is read-only
    97                                                        and set during reset */
    98         (SH7750_BCR2_SZ_32 << SH7750_BCR2_A6SZ_S) | /* Area 6 not used */
    99         (SH7750_BCR2_SZ_32 << SH7750_BCR2_A5SZ_S) | /* Area 5 not used */
    100         (SH7750_BCR2_SZ_32 << SH7750_BCR2_A4SZ_S) | /* Area 4 not used */
    101         (SH7750_BCR2_SZ_32 << SH7750_BCR2_A3SZ_S) | /* Area 3 not used */
    102         (SH7750_BCR2_SZ_32 << SH7750_BCR2_A2SZ_S) | /* SDRAM is 32-bit width */
    103         (SH7750_BCR2_SZ_32 << SH7750_BCR2_A1SZ_S) | /* GDC is 32-bit width */
    104         SH7750_BCR2_PORTEN,                         /* Use D32-D51 as a port */
    105         SH7750_BCR2);
    106 
    107     write32(
    108         (0 << SH7750_WCR1_DMAIW_S) |  /* 0 required for SDRAM RAS down mode */
    109         (7 << SH7750_WCR1_A6IW_S) |   /* Area 6 not used */
    110         (7 << SH7750_WCR1_A5IW_S) |   /* Area 5 not used */
    111         (7 << SH7750_WCR1_A4IW_S) |   /* Area 4 not used */
    112         (7 << SH7750_WCR1_A3IW_S) |   /* Area 3 not used */
    113         (1 << SH7750_WCR1_A2IW_S) |   /* 1 idle cycles inserted between acc */
    114         (7 << SH7750_WCR1_A1IW_S) |   /* Don't have GDC specs... Set safer. */
    115         (1 << SH7750_WCR1_A0IW_S),    /* 1 idle cycles inserted between acc */
    116         SH7750_WCR1);
    117 
    118     write32(
    119         (SH7750_WCR2_WS15   << SH7750_WCR2_A6W_S) | /* Area 6 not used */
    120         (SH7750_WCR2_BPWS7  << SH7750_WCR2_A6B_S) |
    121         (SH7750_WCR2_WS15   << SH7750_WCR2_A5W_S) | /* Area 5 not used */
    122         (SH7750_WCR2_BPWS7  << SH7750_WCR2_A5B_S) |
    123         (SH7750_WCR2_WS15   << SH7750_WCR2_A4W_S) | /* Area 4 not used */
    124         (SH7750_WCR2_WS15   << SH7750_WCR2_A3W_S) | /*Area 3 not used*/
    125         (SH7750_WCR2_SDRAM_CAS_LAT2 << SH7750_WCR2_A2W_S) | /* SDRAM CL = 2 */
    126         (SH7750_WCR2_WS15   << SH7750_WCR2_A1W_S) | /* Area 1 (GDC)
    127                                                        requirements not known*/
    128         (SH7750_WCR2_WS6    << SH7750_WCR2_A0W_S) | /* 4 wait states required
    129                                                        at 48MHz for 70ns mem.,
    130                                                        set closest greater */
    131         (SH7750_WCR2_BPWS7  << SH7750_WCR2_A0B_S),  /* burst mode disabled for
    132                                                        Area 0 flash ROM */
    133         SH7750_WCR2);
    134     write32(
    135         SH7750_WCR3_A6S |                           /* Area 6 not used */
    136         (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A6H_S) |
    137         SH7750_WCR3_A5S |                           /* Area 5 not used */
    138         (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A5H_S) |
    139         SH7750_WCR3_A4S |                           /* Area 4 not used */
    140         (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A4H_S) |
    141         SH7750_WCR3_A3S |                           /* Area 3 not used */
    142         (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A3H_S) |
    143         SH7750_WCR3_A2S |                           /* SDRAM - ignored */
    144         (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A2H_S) |
    145         SH7750_WCR3_A1S |                           /* GDC - unknown, set max*/
    146         (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A1H_S) |
    147         0 |               /* flash ROM - no write strobe setup time required */
    148         (SH7750_WCR3_DHWS_0 << SH7750_WCR3_A0H_S),
    149         SH7750_WCR3);
    150 
    151     #define MCRDEF \
    152         /* SH7750_MCR_RASD | */  /* Set RAS Down mode */                      \
    153         (SH7750_MCR_TRC_0 | SH7750_MCR_TRAS_SDRAM_TRC_4 |                     \
    154                  /* RAS precharge time is 63ns; it corresponds to 4 clocks */ \
    155         /* TCAS valid only for DRAM interface */                              \
    156         SH7750_MCR_TPC_SDRAM_1 | /* TPC = 20ns = 1 clock */                   \
    157         SH7750_MCR_RCD_SDRAM_2 | /* RCD = 21ns = 2 clock */                   \
    158         /* After write, next active command is not issued for a period of     \
    159            TPC + TRWL. SDRAM specifies that it should be BL+Trp clocks when   \
    160            CL=2. Trp = 20ns = 1clock; BL=8. Therefore we should wait 9        \
    161            clocks. Don't know why, but 6 clocks (TRWL=5 and TPC=1) seems      \
    162            working. May be, something wrong in documentation? */              \
    163         SH7750_MCR_TRWL_5 |      /* TRWL = 5 clock        */                  \
    164         SH7750_MCR_BE |          /* Always enabled for SDRAM */               \
    165         SH7750_MCR_SZ_32 |       /* Memory data size is 32 bit */             \
    166         (4 << SH7750_MCR_AMX_S) | /* Select memory device type */             \
    167         SH7750_MCR_RFSH |        /* Refresh is performed */                   \
    168         SH7750_MCR_RMODE_NORMAL) /* Auto-Refresh mode */
    169 
    170     /* Clear refresh timer counter */
    171     write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
    172 
    173     /* Time between auto-refresh commands is 15.6 microseconds; refresh
    174        timer counter frequency is 12 MHz; 1.56e-5*1.2e7= 187.2, therefore
    175        program the refresh timer divider to 187 */
    176     write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR);
    177 
    178     /* Clear refresh counter */
    179     write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
    180 
    181     /* Select refresh counter base frequency as bus frequency/4 = 12 MHz */
    182     write16(SH7750_RTCSR_CKS_CKIO_DIV4 | SH7750_RTCSR_KEY, SH7750_RTCSR);
    183 
    184     /* Initialize Memory Control Register; disable refresh */
    185     write32((MCRDEF & ~SH7750_MCR_RFSH) | SH7750_MCR_PALL, SH7750_MCR);
    186 
    187     /* SDRAM power-up initialization require 100 microseconds delay after
    188        stable power and clock fed; 100 microseconds corresponds to 7 refresh
    189        intervals */
    190     while (read16(SH7750_RFCR) <= 7);
    191 
    192     /* Clear refresh timer counter */
    193     write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
    194 
    195     /* Clear refresh counter */
    196     write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
    197 
    198     /* Execute Precharge All command */
    199     write32(0, SH7750_SDRAM_MODE_A2_32BIT(0));
    200 
    201     /* Initialize Memory Control Register; enable refresh, prepare to
    202        SDRAM mode register setting */
    203     write32(MCRDEF | SH7750_MCR_MRSET, SH7750_MCR);
    204 
    205     /* Wait until at least 2 auto-refresh commands to be executed */
    206     while (read16(SH7750_RFCR) <= 10);
    207 
    208     /* SDRAM data width is 32 bit (4 bytes), cache line size is 32 bytes,
    209        therefore burst length is 8 (32 / 4) */
    210     write8(0,SH7750_SDRAM_MODE_A2_32BIT(
    211         SDRAM_MODE_BL_8 |
    212         SDRAM_MODE_BT_SEQ |    /* Only sequential burst mode supported
    213                                   in SH7750 */
    214         SDRAM_MODE_CL_2 |      /* CAS latency is 2 */
    215         SDRAM_MODE_OPC_BRBW)   /* Burst read/burst write */
    216     );
    217     /* Bus State Controller initialized now */
    218 
    219     /* Disable DMA controller */
    220     write32(0, SH7750_DMAOR);
    221 
    222     /* I/O port setup */
    223     /* Configure all port bits as output - to fasciliate debugging */
    224     write32(
    225         SH7750_PCTRA_PBOUT(0)  | SH7750_PCTRA_PBOUT(1) |
    226         SH7750_PCTRA_PBOUT(2)  | SH7750_PCTRA_PBOUT(3) |
    227         SH7750_PCTRA_PBOUT(4)  | SH7750_PCTRA_PBOUT(5) |
    228         SH7750_PCTRA_PBOUT(6)  | SH7750_PCTRA_PBOUT(7) |
    229         SH7750_PCTRA_PBOUT(8)  | SH7750_PCTRA_PBOUT(9) |
    230         SH7750_PCTRA_PBOUT(10) | SH7750_PCTRA_PBOUT(11) |
    231         SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) |
    232         SH7750_PCTRA_PBOUT(14) | SH7750_PCTRA_PBOUT(15),
    233         SH7750_PCTRA);
    234     write32(
    235         SH7750_PCTRB_PBOUT(16) | SH7750_PCTRB_PBOUT(17) |
    236         SH7750_PCTRB_PBOUT(18) | SH7750_PCTRB_PBOUT(19),
    237         SH7750_PCTRB);
    238     /* Clear data in port */
    239     write32(0, SH7750_PDTRA);
    240     write32(0, SH7750_PDTRB);
    241 
    242     /* Interrupt Controller Initialization */
    243     write16(SH7750_ICR_IRLM, SH7750_ICR); /* IRLs serves as an independent
    244                                              interrupt request lines */
    245     /* Mask all requests at this time */
    246     write16(
    247         (0 << SH7750_IPRA_TMU0_S) |
    248         (0 << SH7750_IPRA_TMU1_S) |
    249         (0 << SH7750_IPRA_TMU2_S) |
    250         (0 << SH7750_IPRA_RTC_S),
    251         SH7750_IPRA);
    252     write16(
    253         (0 << SH7750_IPRB_WDT_S) |
    254         (0 << SH7750_IPRB_REF_S) |
    255         (0 << SH7750_IPRB_SCI1_S),
    256         SH7750_IPRB);
    257     write16(
    258         (0 << SH7750_IPRC_GPIO_S) |
    259         (0 << SH7750_IPRC_DMAC_S) |
    260         (0 << SH7750_IPRC_SCIF_S) |
    261         (0 << SH7750_IPRC_HUDI_S),
    262         SH7750_IPRC);
     33  /* Explicitly turn off the MMU */
     34  write32(0, SH7750_MMUCR);
     35
     36  /* Disable instruction and operand caches */
     37  write32(0, SH7750_CCR);
     38
     39  /* Setup Clock Generator */
     40  /*
     41   * Input clock frequency is 16 MHz, MD0=1,
     42   * CPU clock frequency already selected to 96MHz.
     43   * Bus clock frequency should be set to 48 MHz, therefore divider 2
     44   * should be applied (bus frequency is 48 MHz, clock period is 20.84ns).
     45   * Peripheral frequency should be set to 24 MHz, therefore divider 4
     46   * should be used.
     47   */
     48  /* Prepare watchdog timer for frequency changing */
     49  write16((read8(SH7750_WTCSR) & ~SH7750_WTCSR_TME) |
     50          SH7750_WTCSR_KEY, SH7750_WTCSR);
     51  write16(SH7750_WTCSR_MODE_IT | SH7750_WTCSR_CKS_DIV4096 |
     52          SH7750_WTCSR_KEY, SH7750_WTCSR);
     53
     54  /* Turn PLL1 on */
     55  write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
     56  write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL1EN, SH7750_FRQCR);
     57
     58  /* Perform Frequency Selection */
     59  write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
     60  write16(SH7750_FRQCR_CKOEN | SH7750_FRQCR_PLL1EN |
     61          SH7750_FRQCR_IFCDIV1 | SH7750_FRQCR_BFCDIV2 | SH7750_FRQCR_PFCDIV4,
     62          SH7750_FRQCR);
     63
     64  /* Turn PLL2 on */
     65  write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
     66  write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL2EN, SH7750_FRQCR);
     67
     68  /* Bus State Controller Initialization */
     69  /*
     70   * Area assignments:
     71   *     Area 0: Flash memory, SRAM interface
     72   *     Area 1: GDC
     73   *     Area 2: SDRAM
     74   *     Area 3-6: unused
     75   */
     76  write32(
     77      /* Pull-ups (IPUP, OPUP) enabled */
     78      /* No Byte-Control SRAM mode for Area 1 and Area 3 */
     79      SH7750_BCR1_BREQEN | /* Enable external bus requests */
     80      /* No Partial Sharing Mode */
     81      /* No MPX interface */
     82      /* Memory and Control Signals are in HiZ */
     83      SH7750_BCR1_A0BST_SRAM | /* No burst ROM in flash */
     84      SH7750_BCR1_A5BST_SRAM | /* Area 5 is not in use */
     85      SH7750_BCR1_A6BST_SRAM | /* Area 6 is not in use */
     86      SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM  /* Select Area 2 SDRAM type */
     87      /* Area 5,6 programmed as a SRAM interface (not PCMCIA) */,
     88      SH7750_BCR1);
     89
     90  write16(
     91      (SH7750_BCR2_SZ_8 << SH7750_BCR2_A0SZ_S) |  /* These bits is read-only
     92                                                     and set during reset */
     93      (SH7750_BCR2_SZ_32 << SH7750_BCR2_A6SZ_S) | /* Area 6 not used */
     94      (SH7750_BCR2_SZ_32 << SH7750_BCR2_A5SZ_S) | /* Area 5 not used */
     95      (SH7750_BCR2_SZ_32 << SH7750_BCR2_A4SZ_S) | /* Area 4 not used */
     96      (SH7750_BCR2_SZ_32 << SH7750_BCR2_A3SZ_S) | /* Area 3 not used */
     97      (SH7750_BCR2_SZ_32 << SH7750_BCR2_A2SZ_S) | /* SDRAM is 32-bit width */
     98      (SH7750_BCR2_SZ_32 << SH7750_BCR2_A1SZ_S) | /* GDC is 32-bit width */
     99      SH7750_BCR2_PORTEN,                         /* Use D32-D51 as a port */
     100      SH7750_BCR2);
     101
     102  write32(
     103      (0 << SH7750_WCR1_DMAIW_S) |  /* 0 required for SDRAM RAS down mode */
     104      (7 << SH7750_WCR1_A6IW_S) |   /* Area 6 not used */
     105      (7 << SH7750_WCR1_A5IW_S) |   /* Area 5 not used */
     106      (7 << SH7750_WCR1_A4IW_S) |   /* Area 4 not used */
     107      (7 << SH7750_WCR1_A3IW_S) |   /* Area 3 not used */
     108      (1 << SH7750_WCR1_A2IW_S) |   /* 1 idle cycles inserted between acc */
     109      (7 << SH7750_WCR1_A1IW_S) |   /* Don't have GDC specs... Set safer. */
     110      (1 << SH7750_WCR1_A0IW_S),    /* 1 idle cycles inserted between acc */
     111      SH7750_WCR1);
     112
     113  write32(
     114      (SH7750_WCR2_WS15   << SH7750_WCR2_A6W_S) | /* Area 6 not used */
     115      (SH7750_WCR2_BPWS7  << SH7750_WCR2_A6B_S) |
     116      (SH7750_WCR2_WS15   << SH7750_WCR2_A5W_S) | /* Area 5 not used */
     117      (SH7750_WCR2_BPWS7  << SH7750_WCR2_A5B_S) |
     118      (SH7750_WCR2_WS15   << SH7750_WCR2_A4W_S) | /* Area 4 not used */
     119      (SH7750_WCR2_WS15   << SH7750_WCR2_A3W_S) | /*Area 3 not used*/
     120      (SH7750_WCR2_SDRAM_CAS_LAT2 << SH7750_WCR2_A2W_S) | /* SDRAM CL = 2 */
     121      (SH7750_WCR2_WS15   << SH7750_WCR2_A1W_S) | /* Area 1 (GDC)
     122                                                     requirements not known*/
     123      (SH7750_WCR2_WS6    << SH7750_WCR2_A0W_S) | /* 4 wait states required
     124                                                     at 48MHz for 70ns mem.,
     125                                                     set closest greater */
     126      (SH7750_WCR2_BPWS7  << SH7750_WCR2_A0B_S),  /* burst mode disabled for
     127                                                     Area 0 flash ROM */
     128      SH7750_WCR2);
     129  write32(
     130      SH7750_WCR3_A6S |                           /* Area 6 not used */
     131      (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A6H_S) |
     132      SH7750_WCR3_A5S |                           /* Area 5 not used */
     133      (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A5H_S) |
     134      SH7750_WCR3_A4S |                           /* Area 4 not used */
     135      (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A4H_S) |
     136      SH7750_WCR3_A3S |                           /* Area 3 not used */
     137      (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A3H_S) |
     138      SH7750_WCR3_A2S |                           /* SDRAM - ignored */
     139      (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A2H_S) |
     140      SH7750_WCR3_A1S |                           /* GDC - unknown, set max*/
     141      (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A1H_S) |
     142      0 |               /* flash ROM - no write strobe setup time required */
     143      (SH7750_WCR3_DHWS_0 << SH7750_WCR3_A0H_S),
     144      SH7750_WCR3);
     145
     146  #define MCRDEF \
     147      /* SH7750_MCR_RASD | */  /* Set RAS Down mode */                      \
     148      (SH7750_MCR_TRC_0 | SH7750_MCR_TRAS_SDRAM_TRC_4 |                     \
     149               /* RAS precharge time is 63ns; it corresponds to 4 clocks */ \
     150      /* TCAS valid only for DRAM interface */                              \
     151      SH7750_MCR_TPC_SDRAM_1 | /* TPC = 20ns = 1 clock */                   \
     152      SH7750_MCR_RCD_SDRAM_2 | /* RCD = 21ns = 2 clock */                   \
     153      /* After write, next active command is not issued for a period of     \
     154         TPC + TRWL. SDRAM specifies that it should be BL+Trp clocks when   \
     155         CL=2. Trp = 20ns = 1clock; BL=8. Therefore we should wait 9        \
     156         clocks. Don't know why, but 6 clocks (TRWL=5 and TPC=1) seems      \
     157         working. May be, something wrong in documentation? */              \
     158      SH7750_MCR_TRWL_5 |      /* TRWL = 5 clock        */                  \
     159      SH7750_MCR_BE |          /* Always enabled for SDRAM */               \
     160      SH7750_MCR_SZ_32 |       /* Memory data size is 32 bit */             \
     161      (4 << SH7750_MCR_AMX_S) | /* Select memory device type */             \
     162      SH7750_MCR_RFSH |        /* Refresh is performed */                   \
     163      SH7750_MCR_RMODE_NORMAL) /* Auto-Refresh mode */
     164
     165  /* Clear refresh timer counter */
     166  write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
     167
     168  /* Time between auto-refresh commands is 15.6 microseconds; refresh
     169     timer counter frequency is 12 MHz; 1.56e-5*1.2e7= 187.2, therefore
     170     program the refresh timer divider to 187 */
     171  write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR);
     172
     173  /* Clear refresh counter */
     174  write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
     175
     176  /* Select refresh counter base frequency as bus frequency/4 = 12 MHz */
     177  write16(SH7750_RTCSR_CKS_CKIO_DIV4 | SH7750_RTCSR_KEY, SH7750_RTCSR);
     178
     179  /* Initialize Memory Control Register; disable refresh */
     180  write32((MCRDEF & ~SH7750_MCR_RFSH) | SH7750_MCR_PALL, SH7750_MCR);
     181
     182  /* SDRAM power-up initialization require 100 microseconds delay after
     183     stable power and clock fed; 100 microseconds corresponds to 7 refresh
     184     intervals */
     185  while (read16(SH7750_RFCR) <= 7);
     186
     187  /* Clear refresh timer counter */
     188  write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
     189
     190  /* Clear refresh counter */
     191  write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
     192
     193  /* Execute Precharge All command */
     194  write32(0, SH7750_SDRAM_MODE_A2_32BIT(0));
     195
     196  /* Initialize Memory Control Register; enable refresh, prepare to
     197     SDRAM mode register setting */
     198  write32(MCRDEF | SH7750_MCR_MRSET, SH7750_MCR);
     199
     200  /* Wait until at least 2 auto-refresh commands to be executed */
     201  while (read16(SH7750_RFCR) <= 10);
     202
     203  /* SDRAM data width is 32 bit (4 bytes), cache line size is 32 bytes,
     204     therefore burst length is 8 (32 / 4) */
     205  write8(0,SH7750_SDRAM_MODE_A2_32BIT(
     206      SDRAM_MODE_BL_8 |
     207      SDRAM_MODE_BT_SEQ |    /* Only sequential burst mode supported
     208                                in SH7750 */
     209      SDRAM_MODE_CL_2 |      /* CAS latency is 2 */
     210      SDRAM_MODE_OPC_BRBW)   /* Burst read/burst write */
     211  );
     212  /* Bus State Controller initialized now */
     213
     214  /* Disable DMA controller */
     215  write32(0, SH7750_DMAOR);
     216
     217  /* I/O port setup */
     218  /* Configure all port bits as output - to fasciliate debugging */
     219  write32(
     220      SH7750_PCTRA_PBOUT(0)  | SH7750_PCTRA_PBOUT(1) |
     221      SH7750_PCTRA_PBOUT(2)  | SH7750_PCTRA_PBOUT(3) |
     222      SH7750_PCTRA_PBOUT(4)  | SH7750_PCTRA_PBOUT(5) |
     223      SH7750_PCTRA_PBOUT(6)  | SH7750_PCTRA_PBOUT(7) |
     224      SH7750_PCTRA_PBOUT(8)  | SH7750_PCTRA_PBOUT(9) |
     225      SH7750_PCTRA_PBOUT(10) | SH7750_PCTRA_PBOUT(11) |
     226      SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) |
     227      SH7750_PCTRA_PBOUT(14) | SH7750_PCTRA_PBOUT(15),
     228      SH7750_PCTRA);
     229  write32(
     230      SH7750_PCTRB_PBOUT(16) | SH7750_PCTRB_PBOUT(17) |
     231      SH7750_PCTRB_PBOUT(18) | SH7750_PCTRB_PBOUT(19),
     232      SH7750_PCTRB);
     233  /* Clear data in port */
     234  write32(0, SH7750_PDTRA);
     235  write32(0, SH7750_PDTRB);
     236
     237  /* Interrupt Controller Initialization */
     238  write16(SH7750_ICR_IRLM, SH7750_ICR); /* IRLs serves as an independent
     239                                           interrupt request lines */
     240  /* Mask all requests at this time */
     241  write16(
     242      (0 << SH7750_IPRA_TMU0_S) |
     243      (0 << SH7750_IPRA_TMU1_S) |
     244      (0 << SH7750_IPRA_TMU2_S) |
     245      (0 << SH7750_IPRA_RTC_S),
     246      SH7750_IPRA);
     247  write16(
     248      (0 << SH7750_IPRB_WDT_S) |
     249      (0 << SH7750_IPRB_REF_S) |
     250      (0 << SH7750_IPRB_SCI1_S),
     251      SH7750_IPRB);
     252  write16(
     253      (0 << SH7750_IPRC_GPIO_S) |
     254      (0 << SH7750_IPRC_DMAC_S) |
     255      (0 << SH7750_IPRC_SCIF_S) |
     256      (0 << SH7750_IPRC_HUDI_S),
     257      SH7750_IPRC);
    263258
    264259}
     
    270265void bsp_cache_on(void)
    271266{
    272     switch (boot_mode)
    273     {
    274         case SH4_BOOT_MODE_FLASH:
    275             write32(SH7750_CCR_ICI | SH7750_CCR_ICE |
    276                     SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE,
    277                     SH7750_CCR);
    278             break;
    279         case SH4_BOOT_MODE_IPL:
    280             __asm__ volatile (
    281                 "mov     #6, r0\n"
    282                 "xor     r4, r4\n"
    283                 "trapa   #0x3f\n"
    284                 : : : "r0", "r4");
    285             break;
    286         default: /* unreachable */
    287             break;
    288     }
     267  switch (boot_mode) {
     268    case SH4_BOOT_MODE_FLASH:
     269      write32(SH7750_CCR_ICI | SH7750_CCR_ICE |
     270              SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE,
     271              SH7750_CCR);
     272      break;
     273    case SH4_BOOT_MODE_IPL:
     274      __asm__ volatile (
     275          "mov     #6, r0\n"
     276          "xor     r4, r4\n"
     277          "trapa   #0x3f\n"
     278          : : : "r0", "r4");
     279      break;
     280    default: /* unreachable */
     281      break;
     282  }
    289283}
  • c/src/lib/libbsp/sh/gensh4/include/bsp.h

    r694debe r0626dba  
    11/*
    2  *  This include file contains all board IO definitions.
    3  *
    42 *  generic sh4 BSP
    53 *
     4 *  This include file contains all board IO definitions.
     5 */
     6
     7/*
    68 *  Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
    79 *  Author: Victor V. Vengerov <vvv@oktet.ru>
     
    4850#include <bspopts.h>
    4951#include <bsp/default-initial-extension.h>
     52#include <termios.h> /* for tcflag_t */
    5053
    5154#include "rtems/score/sh7750_regs.h"
     
    8083
    8184/*
    82  * NOTE: Use the standard Clock driver entry
     85 * BSP methods that cross file boundaries.
    8386 */
     87void bsp_hw_init(void);
     88void early_hw_init(void);
     89void bsp_cache_on(void);
     90extern int _sci_get_brparms(
     91  tcflag_t      cflag,
     92  unsigned char *smr,
     93  unsigned char *brr
     94);
    8495
    8596#ifdef __cplusplus
  • c/src/lib/libbsp/sh/shared/bsphwinit.c

    r694debe r0626dba  
    11/*
    22 *  This is a dummy bsp_hw_init routine.
    3  *
    4  *  COPYRIGHT (c) 1989-2008.
     3 */
     4
     5/*
     6 *  COPYRIGHT (c) 1989-2014.
    57 *  On-Line Applications Research Corporation (OAR).
    68 *
     
    1012 */
    1113
     14#include <bsp.h>
     15
    1216void bsp_hw_init( void )
    1317{
  • c/src/lib/libbsp/sh/shsim/console/console-debugio.c

    r694debe r0626dba  
    22 *  @file
    33 *  @brief Stub printk() support
    4  *
    5  *  This file contains a stub for the required printk() support.
    6  *  It is NOT functional!!!
    74 */
    85
     
    2825);
    2926
    30 void BSP_output_char_f(char c)
     27static void BSP_output_char_f(char c)
    3128{
    3229  console_outbyte_polled( 0, c );
  • c/src/lib/libbsp/sh/shsim/console/console-io.c

    r694debe r0626dba  
    2121#include <bsp/syscall.h>
    2222
    23 int errno;
    24 
    25 extern int __trap34(int, int, void*, int );
    26 
    2723/*
    2824 *  console_initialize_hardware
    2925 *
    3026 *  This routine initializes the console hardware.
    31  *
    3227 */
    33 
    3428void console_initialize_hardware(void)
    3529{
    36   return;
    3730}
    3831
     
    4235 *  This routine transmits a character using polling.
    4336 */
    44 
    4537void console_outbyte_polled(
    4638  int  port,
     
    4941{
    5042  __trap34 (SYS_write, 1, &ch, 1);
    51   return;
    5243}
    5344
     
    5748 *  This routine polls for a character.
    5849 */
    59 
    6050int console_inbyte_nonblocking(
    6151  int port
     
    6656  return __trap34 (SYS_read, 0, &c, 1);
    6757}
    68 
    69 /* XXX wrong place for this */
    70 int _sys_exit (int n)
    71 {
    72   return __trap34 (SYS_exit, n, 0, 0);
    73 }
  • c/src/lib/libbsp/sh/shsim/include/bsp.h

    r694debe r0626dba  
    11/*
    2  *  This include file contains all board IO definitions.
    3  *
    42 *  SH-gdb simulator BSP
    53 *
     4 *  This include file contains all board IO definitions.
     5 */
     6
     7/*
    68 *  Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
    79 *
     
    2224#ifndef _BSP_H
    2325#define _BSP_H
     26
     27#ifndef ASM
    2428
    2529#ifdef __cplusplus
     
    4751 * Defined in the linker script 'linkcmds'
    4852 */
    49 
    5053extern void *CPU_Interrupt_stack_low;
    5154extern void *CPU_Interrupt_stack_high;
     55
     56/*
     57 * BSP methods that cross file boundaries.
     58 */
     59int __trap34(int, int, void*, int );
     60int _sys_exit (int n);
     61void bsp_hw_init(void);
    5262
    5363#ifdef __cplusplus
     
    5565#endif
    5666
     67#endif /* !ASM */
    5768#endif
  • c/src/lib/libbsp/sh/shsim/start/start.S

    r694debe r0626dba  
    1919
    2020#include <rtems/asm.h>
     21#include <bsp.h>
    2122
    2223        BEGIN_CODE
  • c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c

    r694debe r0626dba  
    3636#include <rtems/score/threaddispatch.h>
    3737#include <rtems/score/sh.h>
     38#include <rtems/score/ispsh7032.h>
    3839
    3940#include <rtems/score/ispsh7032.h>
  • c/src/lib/libcpu/sh/sh7045/sci/sci.c

    r694debe r0626dba  
    99 * another device. If rtems once will support sym-links for devices files,
    1010 * this implementation could be dropped.
    11  *
     11 */
     12
     13/*
    1214 *  Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
    1315 *
     
    7678
    7779struct scidev_t {
    78   char *                        name;
    79   uint32_t                      addr;
    80   rtems_device_minor_number     minor;
    81   unsigned short                opened;
    82   tcflag_t                      cflags;
     80  char *                     name;
     81  uint32_t                   addr;
     82  rtems_device_minor_number  minor;
     83  unsigned short             opened;
     84  tcflag_t                   cflags;
    8385} sci_device[SCI_MINOR_DEVICES] =
    8486{
     
    105107)
    106108{
    107   uint8_t       smr;
    108   uint8_t       brr;
     109  uint8_t  smr;
     110  uint8_t  brr;
    109111
    110112  if ( c_cflag & CBAUD )
     
    149151 * called from polling routines or ISRs
    150152 */
    151 bool wrtSCI0(unsigned char ch)
     153static bool wrtSCI0(unsigned char ch)
    152154{
    153155  uint8_t   temp;
     
    165167} /* wrtSCI0 */
    166168
    167 bool wrtSCI1(unsigned char ch)
     169static bool wrtSCI1(unsigned char ch)
    168170{
    169171  uint8_t   temp;
     
    182184
    183185/* polled output steers byte to selected port */
    184 void sh_sci_outbyte_polled(
     186static void sh_sci_outbyte_polled(
    185187  rtems_device_minor_number  minor,
    186188  char ch )
    187189{
    188         if (minor == 0) /* blocks until port ready */
    189                 while (wrtSCI0(ch) != true); /* SCI0*/
    190         else
    191                 while (wrtSCI1(ch) != true); /* SCI1*/
     190  if (minor == 0) /* blocks until port ready */
     191    while (wrtSCI0(ch) != true); /* SCI0*/
     192  else
     193    while (wrtSCI1(ch) != true); /* SCI1*/
    192194} /* sh_sci_outbyte_polled */
    193195
     
    195197 * Initial version calls polled output driver and blocks
    196198 */
    197 void outbyte(
     199static void outbyte(
    198200  rtems_device_minor_number  minor,
    199201  char ch)
    200202{
    201         sh_sci_outbyte_polled(minor, (unsigned char)ch);
     203  sh_sci_outbyte_polled(minor, (unsigned char)ch);
    202204} /* outbyte */
    203205
    204 bool rdSCI0(unsigned char *ch)
     206static bool rdSCI0(unsigned char *ch)
    205207{
    206208  uint8_t   temp;
     
    226228} /* rdSCI0 */
    227229
    228 bool rdSCI1(unsigned char *ch)
     230static bool rdSCI1(unsigned char *ch)
    229231{
    230232  uint8_t   temp;
     
    250252} /* rdSCI1 */
    251253
    252 
    253254/* initial version pulls byte from selected port */
    254 char sh_sci_inbyte_polled( rtems_device_minor_number  minor )
     255static char sh_sci_inbyte_polled( rtems_device_minor_number  minor )
    255256{
    256257  uint8_t ch = 0;
     
    264265
    265266/* Initial version calls polled input driver */
    266 char inbyte( rtems_device_minor_number  minor )
     267static char inbyte( rtems_device_minor_number  minor )
    267268{
    268269  char ch;
     
    272273} /* inbyte */
    273274
    274 
    275275/*  sh_sci_initialize
    276276 *
     
    284284 *   if all sci[...] register, else calls
    285285 *   rtems_fatal_error_occurred(status)
    286  *
    287  */
    288 
     286 */
    289287rtems_device_driver sh_sci_initialize(
    290288  rtems_device_major_number  major,
     
    295293  rtems_device_minor_number i;
    296294  rtems_driver_name_t driver;
    297 
    298295
    299296  /*
     
    304301   * initialization therefore we check it everytime
    305302   */
    306 
    307   for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ )
    308   {
     303  for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ ) {
    309304    status = rtems_io_lookup_name(
    310305        sci_device[i].name,
    311306        &driver);
    312     if ( status != RTEMS_SUCCESSFUL )
    313     {
     307    if ( status != RTEMS_SUCCESSFUL ) {
    314308        /* OK. We assume it is not registered yet. */
    315309        status = rtems_io_register_name(
    316310            sci_device[i].name,
    317311            major,
    318             sci_device[i].minor );
     312            sci_device[i].minor
     313        );
    319314        if (status != RTEMS_SUCCESSFUL)
    320315            rtems_fatal_error_occurred(status);
     
    327322}
    328323
    329 
    330324/*
    331325 *  Open entry point
    332326 *   Sets up port and pins for selected sci.
    333327 */
    334 
    335328rtems_device_driver sh_sci_open(
    336329  rtems_device_major_number major,
     
    338331  void                    * arg )
    339332{
    340   uint8_t   temp8;
     333  uint8_t    temp8;
    341334  uint16_t   temp16;
    342335
    343   unsigned      a;
     336  unsigned   a;
    344337
    345338 /* check for valid minor number */
    346    if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
    347    {
    348      return RTEMS_INVALID_NUMBER;
    349    }
     339 if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 )) {
     340   return RTEMS_INVALID_NUMBER;
     341 }
    350342
    351343  /* device already opened */
    352   if ( sci_device[minor].opened > 0 )
    353   {
     344  if ( sci_device[minor].opened > 0 ) {
    354345    sci_device[minor].opened++;
    355346    return RTEMS_SUCCESSFUL;
     
    373364
    374365  /* set up SCI registers */
    375       write8(0x00, sci_device[minor].addr + SCI_SCR);    /* Clear SCR */
     366      write8(0x00, sci_device[minor].addr + SCI_SCR);  /* Clear SCR */
    376367                                                   /* set SMR and BRR */
    377368    _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags );
     
    382373
    383374    write8((SCI_RE | SCI_TE),              /* enable async. Tx and Rx */
    384            sci_device[minor].addr + SCI_SCR);
     375     sci_device[minor].addr + SCI_SCR);
    385376
    386377    /* clear error flags */
     
    410401 *  Close entry point
    411402 */
    412 
    413403rtems_device_driver sh_sci_close(
    414404  rtems_device_major_number major,
     
    429419 * read bytes from the serial port. We only have stdin.
    430420 */
    431 
    432421rtems_device_driver sh_sci_read(
    433422  rtems_device_major_number major,
     
    461450 * write bytes to the serial port. Stdout and stderr are the same.
    462451 */
    463 
    464452rtems_device_driver sh_sci_write(
    465453  rtems_device_major_number major,
     
    492480 *  IO Control entry point
    493481 */
    494 
    495482rtems_device_driver sh_sci_control(
    496483  rtems_device_major_number major,
     
    574561const rtems_termios_callbacks* sh_sci_get_termios_handlers( bool poll )
    575562{
    576     return poll ?
    577         &sci_poll_callbacks :
    578         &sci_interrupt_callbacks;
    579 }
     563  return poll ?
     564      &sci_poll_callbacks :
     565      &sci_interrupt_callbacks;
     566}
  • c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c

    r694debe r0626dba  
    11/*
    22 * Termios console serial driver.
    3  *
     3 */
     4
     5/*
    46 * Based on SCI driver by Ralf Corsepius and John M. Mills
    57 *
     
    125127 * The same routine for all interrupt sources of the same type.
    126128 */
    127 rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
     129static rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
    128130{
    129131    int minor;
     
    152154 * The same routine for all interrupt sources of the same type.
    153155 */
    154 rtems_isr sh_sci_tx_isr(rtems_vector_number vector)
     156static rtems_isr sh_sci_tx_isr(rtems_vector_number vector)
    155157{
    156158    int minor;
  • c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c

    r694debe r0626dba  
    7878 *    peripheral module clock in Hz.
    7979 */
    80 uint32_t
     80static uint32_t
    8181sh4uart_get_Pph(void)
    8282{
     
    419419 *     nothing
    420420 */
    421 void
     421static void
    422422sh4uart_handle_error(sh4uart *uart)
    423423{
     
    452452{
    453453  int chn = uart->chn;
    454   int error_occured = 0;
    455454  int parity_error = 0;
    456455  int break_occured = 0;
     
    465464    if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
    466465                 SH7750_SCSSR1_ORER)) != 0) {
    467       error_occured = 1;
    468466      if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
    469467        parity_error = 1;
     
    476474                 SH7750_SCSSR2_BRK)) != 0 ||
    477475            (SCLSR2 & SH7750_SCLSR2_ORER) != 0) {
    478       error_occured = 1;
    479476      if (SCSSR2 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
    480477        parity_error = 1;
  • c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c

    r694debe r0626dba  
    11/*
    22 *  Support for SuperH Simulator in GDB
    3  *
     3 */
     4
     5/*
    46 *  COPYRIGHT (c) 1989-2008.
    57 *  On-Line Applications Research Corporation (OAR).
     
    2325register unsigned long  *stack_ptr __asm__ ("r15");
    2426
     27void __ISR_Handler(uint32_t vector);
     28
    2529/*
    2630 *  This routine provides the RTEMS interrupt management.
    2731 */
    28 
    2932void __ISR_Handler( uint32_t   vector)
    3033{
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