Changeset 05e2e4c in rtems


Ignore:
Timestamp:
Jul 13, 2006, 12:29:06 AM (15 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
60426fed
Parents:
c8f74b47
Message:
  • mpc6xx/mmu/bat.c, mpc6xx/mmu/pte121.c, shared/src/cache.c: Checked inline assembly code; added 'm' operands and paranoia 'memory' clobbers. Also, made sure that no pure input operands are modified by the asm.
Location:
c/src/lib/libcpu/powerpc
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    rc8f74b47 r05e2e4c  
     12006-07-12      Till Straumann <strauman@slac.stanford.edu>
     2
     3        * mpc6xx/mmu/bat.c, mpc6xx/mmu/pte121.c, shared/src/cache.c:
     4        Checked inline assembly code; added 'm' operands and
     5        paranoia 'memory' clobbers. Also, made sure that no
     6        pure input operands are modified by the asm.
     7 
    182006-06-19      Till Straumann <strauman@slac.stanford.edu>
    29
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c

    rc8f74b47 r05e2e4c  
    120120    :
    121121    :"i" (HID0), "r" (val)
     122    :"memory" /* paranoia */
    122123  );
    123124}
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c

    rc8f74b47 r05e2e4c  
    181181static void dumpPte (APte pte);
    182182
     183#ifdef DEBUG
    183184static void
    184185dumpPteg (unsigned long vsid, unsigned long pi, unsigned long hash);
     186#endif
     187
    185188unsigned long
    186189triv121IsRangeMapped (long vsid, unsigned long start, unsigned long end);
     
    502505              rtems_interrupt_disable (flags);
    503506              /* order setting 'v' after writing everything else */
    504               asm volatile ("eieio");
     507              asm volatile ("eieio"::"m"(*pte));
    505508              pte->v = 1;
    506               asm volatile ("sync");
     509              asm volatile ("sync"::"m"(*pte));
    507510              rtems_interrupt_enable (flags);
    508511            } else {
     
    550553{
    551554#ifndef DEBUG_MAIN
    552   unsigned long sdr1 = triv121PgTblSDR1 (pt);
     555  unsigned long          sdr1 = triv121PgTblSDR1 (pt);
     556  register unsigned long tmp0 = 16;     /* initial counter value (#segment regs) */
     557  register unsigned long tmp1 = (KEY_USR | KEY_SUP);
     558  register unsigned long tmp2 = (MSR_EE | MSR_IR | MSR_DR);
    553559#endif
    554560  pt->active = 1;
     
    559565  ohdl = globalExceptHdl;
    560566  globalExceptHdl = myhdl;
    561   __asm__ __volatile__ ("sync");
     567  __asm__ __volatile__ ("sync"::"memory");
    562568#endif
    563569
     
    579585   */
    580586  __asm__ __volatile (
    581     "   mtctr   %0\n"
     587    "   mtctr   %[tmp0]\n"
    582588    /* Get MSR and switch interrupts off - just in case.
    583589     * Also switch the MMU off; the book
     
    587593     * the page table...
    588594     */
    589     "   mfmsr   %0\n"
    590     "   andc    %6, %0, %6\n"
    591     "   mtmsr   %6\n"
     595    "   mfmsr   %[tmp0]\n"
     596    "   andc    %[tmp2], %[tmp0], %[tmp2]\n"
     597    "   mtmsr   %[tmp2]\n"
    592598    "   isync   \n"
    593599    /* set up the segment registers */
    594     "   li              %6, 0\n"
    595     "1: mtsrin  %1, %6\n"
    596     "   addis   %6, %6, 0x1000\n" /* address next SR */
    597     "   addi    %1, %1, 1\n"      /* increment VSID  */
     600    "   li              %[tmp2], 0\n"
     601    "1: mtsrin  %[tmp1], %[tmp2]\n"
     602    "   addis   %[tmp2], %[tmp2], 0x1000\n" /* address next SR */
     603    "   addi    %[tmp1], %[tmp1], 1\n"      /* increment VSID  */
    598604    "   bdnz    1b\n"
    599605    /* Now flush all TLBs, starting with the topmost index */
    600     "   lis             %6, %2@h\n"
    601     "2: addic.  %6, %6, -%3\n"    /* address the next one (decrementing) */
    602     "   tlbie   %6\n"             /* invalidate & repeat */
     606    "   lis             %[tmp2], %[ea_range]@h\n"
     607    "2: addic.  %[tmp2], %[tmp2], -%[pg_sz]\n"    /* address the next one (decrementing) */
     608    "   tlbie   %[tmp2]\n"             /* invalidate & repeat */
    603609    "   bgt             2b\n"
    604610    "   eieio   \n"
     
    606612    "   sync    \n"
    607613    /* set up SDR1 */
    608     "   mtspr   %4, %5\n"
     614    "   mtspr   %[sdr1], %[sdr1val]\n"
    609615    /* restore original MSR  */
    610     "   mtmsr   %0\n"
     616    "   mtmsr   %[tmp0]\n"
    611617    "   isync   \n"
    612       :
    613       :"r" (16), "b" (KEY_USR | KEY_SUP),
    614        "i" (FLUSH_EA_RANGE), "i" (1 << LD_PG_SIZE),
    615        "i" (SDR1), "r" (sdr1), "b" (MSR_EE | MSR_IR | MSR_DR)
    616       :"ctr", "cc"
     618      :[tmp0]"+r&"(tmp0), [tmp1]"+b&"(tmp1), [tmp2]"+b&"(tmp2)
     619      :[ea_range]"i"(FLUSH_EA_RANGE), [pg_sz]"i" (1 << LD_PG_SIZE),
     620       [sdr1]"i"(SDR1), [sdr1val]"r" (sdr1)
     621      :"ctr", "cc", "memory"
    617622  );
    618623
     
    834839                "       eieio           \n\t"
    835840                "       tlbsync         \n\t"
    836                 "       sync            \n\t"::"r" (ea));
     841                "       sync            \n\t"::"r" (ea):"memory");
    837842  rtems_interrupt_enable (flags);
    838843  return pte;
     
    851856                :                                                               \
    852857                :"r"(msr)                                               \
    853                 :"3","lr")
     858                :"3","lr","memory")
    854859
    855860/* The book doesn't mention dssall when changing PTEs
     
    912917  pte->v = 0;
    913918  do_dssall ();
    914   asm volatile ("sync");
     919  asm volatile ("sync":::"memory");
    915920  if (wimg >= 0)
    916921    pte->wimg = wimg;
    917922  if (pp >= 0)
    918923    pte->pp = pp;
    919   asm volatile ("tlbie %0; eieio"::"r" (ea));
     924  asm volatile ("tlbie %0; eieio"::"r" (ea):"memory");
    920925  pte->v = 1;
    921   asm volatile ("tlbsync; sync");
     926  asm volatile ("tlbsync; sync":::"memory");
    922927
    923928  /* restore, i.e., switch MMU and IRQs back on */
  • c/src/lib/libcpu/powerpc/shared/src/cache.c

    rc8f74b47 r05e2e4c  
    9292{
    9393  register const void *__address = _address;
    94   asm volatile ( "dcbf 0,%0" :: "r" (__address) );
     94  asm volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
    9595}
    9696
     
    9999{
    100100  register const void *__address = _address;
    101   asm volatile ( "dcbi 0,%0" :: "r" (__address) );
     101  asm volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
    102102}
    103103
     
    127127{
    128128  register const void *__address = _address;
    129   asm volatile ( "icbi 0,%0" :: "r" (__address) );
     129  asm volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
    130130}
    131131
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