Changeset 040ed0b4 in rtems


Ignore:
Timestamp:
Oct 18, 2014, 8:55:37 AM (5 years ago)
Author:
Chris Nott <chrisn@…>
Branches:
4.11, master
Children:
a7eaaae
Parents:
ea05c438
git-author:
Chris Nott <chrisn@…> (10/18/14 08:55:37)
git-committer:
Sebastian Huber <sebastian.huber@…> (10/23/14 06:31:10)
Message:

bsp/stm32f4: Add header files

Added register definition headers for STM32F4 ADC, EXTI, PWR, SYSCFG,
TIM, OTGFS and updated FLASH and RCC. Fixed PLL_Q for USB 48MHz
operation. Added flash prefetch enable.

Location:
c/src/lib/libbsp/arm/stm32f4
Files:
5 added
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/stm32f4/Makefile.am

    rea05c438 r040ed0b4  
    5050include_bsp_HEADERS += include/stm32f10xxx_rcc.h
    5151include_bsp_HEADERS += include/stm32f10xxx_exti.h
     52include_bsp_HEADERS += include/stm32f4xxxx_adc.h
     53include_bsp_HEADERS += include/stm32f4xxxx_exti.h
    5254include_bsp_HEADERS += include/stm32f4xxxx_gpio.h
    5355include_bsp_HEADERS += include/stm32f4xxxx_rcc.h
     56include_bsp_HEADERS += include/stm32f4xxxx_pwr.h
     57include_bsp_HEADERS += include/stm32f4xxxx_syscfg.h
     58include_bsp_HEADERS += include/stm32f4xxxx_tim.h
    5459include_bsp_HEADERS += include/stm32f4xxxx_flash.h
     60include_bsp_HEADERS += include/stm32f4xxxx_otgfs.h
    5561include_bsp_HEADERS += include/stm32_i2c.h
    5662include_bsp_HEADERS += include/i2c.h
  • c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h

    rea05c438 r040ed0b4  
    3636 */
    3737
     38#define STM32F4_APB1_BASE (STM32F4_BASE + 0x40000000)
     39#define STM32F4_APB2_BASE (STM32F4_BASE + 0x40010000)
     40#define STM32F4_AHB1_BASE (STM32F4_BASE + 0x40020000)
     41#define STM32F4_AHB2_BASE (STM32F4_BASE + 0x50000000)
     42
    3843/**
    3944 * @name STM32f4XXXX GPIO
     
    5257
    5358#include <bsp/stm32f4xxxx_rcc.h>
    54 #define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40023800))
     59#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_AHB1_BASE + 0x3800))
    5560
    5661/** @} */
     
    9499/** @} */
    95100
     101/**
     102 * @name STM32f4XXXX PWR
     103 * @{
     104 */
     105
     106#include <bsp/stm32f4xxxx_pwr.h>
     107#define STM32F4_PWR ((volatile stm32f4_pwr *) (STM32F4_APB1_BASE + 0x7000))
     108
     109/** @} */
     110
     111/**
     112 * @name STM32f4XXXX EXTI
     113 * @{
     114 */
     115
     116#include <bsp/stm32f4xxxx_exti.h>
     117#define STM32F4_EXTI ((volatile stm32f4_exti *) (STM32F4_APB2_BASE + 0x3c00))
     118
     119/** @} */
     120
     121/**
     122 * @name STM32f4XXXX SYSCFG
     123 * @{
     124 */
     125
     126#include <bsp/stm32f4xxxx_syscfg.h>
     127#define STM32F4_SYSCFG ((volatile stm32f4_syscfg *) (STM32F4_APB2_BASE + 0x3800))
     128
     129/** @} */
     130
     131/**
     132 * @name STM32f4XXXX FLASH
     133 * @{
     134 */
     135
     136#include <bsp/stm32f4xxxx_flash.h>
     137#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_AHB1_BASE + 0x3c00))
     138
     139/** @} */
     140
     141/**
     142 * @name STM32f4XXXX TIM
     143 * @{
     144 */
     145
     146#include <bsp/stm32f4xxxx_tim.h>
     147#define STM32F4_TIM1 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0000))
     148#define STM32F4_TIM2 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0000))
     149#define STM32F4_TIM3 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0400))
     150#define STM32F4_TIM4 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0800))
     151#define STM32F4_TIM5 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0c00))
     152#define STM32F4_TIM6 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1000))
     153#define STM32F4_TIM7 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1400))
     154#define STM32F4_TIM8 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0400))
     155#define STM32F4_TIM9 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4000))
     156#define STM32F4_TIM10 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4400))
     157#define STM32F4_TIM11 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4800))
     158#define STM32F4_TIM12 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1800))
     159#define STM32F4_TIM13 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1c00))
     160#define STM32F4_TIM14 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x2000))
     161
     162/** @} */
     163
     164/**
     165 * @name STM32f4XXXX ADC
     166 * @{
     167 */
     168
     169#include <bsp/stm32f4xxxx_adc.h>
     170#define STM32F4_ADC1 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2000))
     171#define STM32F4_ADC2 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2100))
     172#define STM32F4_ADC3 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2200))
     173#define STM32F4_ADC_COMMON ((volatile stm32f4_adc_com *) (STM32F4_APB2_BASE + 0x2300))
     174
     175/** @} */
     176
     177/**
     178 * @name STM32f4XXXX OTGFS
     179 * @{
     180 */
     181
     182#include <bsp/stm32f4xxxx_otgfs.h>
     183#define STM32F4_OTGFS_BASE (STM32F4_AHB2_BASE + 0x0000)
     184#define STM32F4_OTGFS_CORE ((volatile stm32f4_otgfs *) (STM32F4_OTGFS_BASE + 0x000))
     185#define STM32F4_OTGFS_DEV ((volatile stm32f4_otgfs_dregs *) (STM32F4_OTGFS_BASE + 0x800))
     186#define STM32F4_OTGFS_INEP ((volatile stm32f4_otgfs_inepregs *) (STM32F4_OTGFS_BASE + 0x900))
     187#define STM32F4_OTGFS_OUTEP ((volatile stm32f4_otgfs_outepregs *) (STM32F4_OTGFS_BASE + 0xb00))
     188#define STM32F4_OTGFS_PWRCTL ((volatile stm32f4_otgfs_pwrctlregs *) (STM32F4_OTGFS_BASE + 0xe00))
     189
     190#define STM32F4_OTGFS_FIFO_BASE (STM32F4_OTGFS_BASE + USB_FIFO_BASE)
     191
     192/** @} */
     193
    96194#endif /* STM32F4_FAMILY_F4XXXX */
    97195
  • c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h

    • Property mode changed from 100644 to 100755
    rea05c438 r040ed0b4  
    1 /**
    2  * @file
     1/*
     2 * Copyright (c) 2013 Chris Nott.  All rights reserved.
    33 *
    4  * @ingroup stm32f4_flash
    5  *
    6  * @brief STM32F4XXXX FLASH support.
    7  *
    8  * Contains structure desribing registers responsible for the flash memory
    9  * configuration.
    10  */
    11 
    12 /*
    13  * Copyright (c) 2014 Tomasz Gregorek.  All rights reserved.
    14  *
    15  *  <tomasz.gregorek@gmail.com>
     4 *  Virtual Logic
     5 *  21-25 King St.
     6 *  Rockdale NSW 2216
     7 *  Australia
     8 *  <rtems@vl.com.au>
    169 *
    1710 * The license and distribution terms for this file may be
    1811 * found in the file LICENSE in this distribution or at
    19  * http://www.rtems.org/license/LICENSE.
     12 * http://www.rtems.com/license/LICENSE.
    2013 */
    2114
     
    2518#include <bsp/utility.h>
    2619
    27 /**
    28  * @defgroup stm32f10xxx_flash STM32F4XXXX FLASH Support
    29  * @ingroup stm32f4_flash
    30  * @brief STM32F4FXXX FLASH Support
    31  * @{
    32  */
     20struct stm32f4_flash_s {
    3321
    34 typedef struct {
    35   uint32_t acr;
    36   uint32_t keyr;
    37   uint32_t optkeyr;
    38   uint32_t sr;
    39   uint32_t cr;
    40   uint32_t optcr;
    41   uint32_t optcr1;
    42 } stm32f4_flash;
     22  uint32_t acr;   // Access and control register
     23#define STM32F4_FLASH_ACR_DCRST   BSP_BIT32(12) // Data cache reset
     24#define STM32F4_FLASH_ACR_ICRST   BSP_BIT32(11) // Instruction cache reset
     25#define STM32F4_FLASH_ACR_DCEN    BSP_BIT32(10) // Data cache enable
     26#define STM32F4_FLASH_ACR_ICEN    BSP_BIT32(9)  // Instruction cache enable
     27#define STM32F4_FLASH_ACR_PRFTEN  BSP_BIT32(8)  // Prefetch enable
     28#define STM32F4_FLASH_ACR_LATENCY(val)  BSP_FLD32(val, 0, 2)  // Flash access latency
     29#define STM32F4_FLASH_ACR_LATENCY_GET(reg)  BSP_FLD32GET(reg, 0, 2)
     30#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
    4331
    44 /** @} */
     32  uint32_t keyr;  // Key register
     33#define STM32F4_FLASH_KEYR_KEY1 0x45670123
     34#define STM32F4_FLASH_KEYR_KEY2 0xCDEF89AB
    4535
    46 #define FLASH_ACR_LATENCY( val ) BSP_FLD32( val, 0, 3 )
    47 #define FLASH_ACR_LATENCY_MSK BSP_MSK32( 0, 3 )
    48 #define FLASH_ACR_PRFTEN BSP_BIT32( 8 )
    49 #define FLASH_ACR_ICEN BSP_BIT32( 9 )
    50 #define FLASH_ACR_DCEN BSP_BIT32( 10 )
    51 #define FLASH_ACR_ICRST BSP_BIT32( 11 )
    52 #define FLASH_ACR_DCRST BSP_BIT32( 12 )
     36  uint32_t optkeyr; // Option key register
     37#define STM32F4_FLASH_OPTKEYR_OPTKEY1 0x08192A3B
     38#define STM32F4_FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F
     39
     40  uint32_t sr;    // Status register
     41#define STM32F4_FLASH_SR_BSY    BSP_BIT32(16) // Busy
     42#define STM32F4_FLASH_SR_PGSERR BSP_BIT32(7)  // Programming sequence error
     43#define STM32F4_FLASH_SR_PGPERR BSP_BIT32(6)  // Programming parallelism error
     44#define STM32F4_FLASH_SR_PGAERR BSP_BIT32(5)  // Programming alignment error
     45#define STM32F4_FLASH_SR_WRPERR BSP_BIT32(4)  // Write protection error
     46#define STM32F4_FLASH_SR_OPERR  BSP_BIT32(1)  // Operation error
     47#define STM32F4_FLASH_SR_EOP    BSP_BIT32(0)  // End of operation
     48
     49  uint32_t cr;    // Control register
     50#define STM32F4_FLASH_CR_LOCK   BSP_BIT32(31) // Lock
     51#define STM32F4_FLASH_CR_ERRIE  BSP_BIT32(25) // Error interrupt enable
     52#define STM32F4_FLASH_CR_EOPIE  BSP_BIT32(24) // End of operation interrupt enable
     53#define STM32F4_FLASH_CR_STRT   BSP_BIT32(16) // Start
     54#define STM32F4_FLASH_CR_PSIZE(val) BSP_FLD32(val, 8, 9)  // Program size
     55#define STM32F4_FLASH_CR_PSIZE_GET(reg) BSP_FLD32GET(reg, 8, 9)
     56#define STM32F4_FLASH_CR_PSIZE_SET(reg, val)  BSP_FLD32SET(reg, val, 8, 9)
     57#define STM32F4_FLASH_CR_SNB  BSP_FLD32(val, 3, 6)  // Sector number
     58#define STM32F4_FLASH_CR_SNB_GET(reg) BSP_FLD32GET(reg, 3, 6)
     59#define STM32F4_FLASH_CR_SNB_SET(reg, val)  BSP_FLD32SET(reg, val, 3, 6)
     60#define STM32F4_FLASH_CR_MER    BSP_BIT32(2)  // Mass erase
     61#define STM32F4_FLASH_CR_SER    BSP_BIT32(1)  // Sector erase
     62#define STM32F4_FLASH_CR_PG     BSP_BIT32(0)  // Programming
     63
     64  uint32_t optcr;   // Option control register
     65#define STM32F4_FLASH_OPTCR_NWRP(val) BSP_FLD32(val, 16, 27)  // Not write protect
     66#define STM32F4_FLASH_OPTCR_NWRP_GET(reg) BSP_FLD32GET(reg, 16, 27)
     67#define STM32F4_FLASH_OPTCR_NWRP_SET(reg, val)  BSP_FLD32SET(reg, val, 16, 27)
     68#define STM32F4_FLASH_OPTCR_RDP(val)  BSP_FLD32(val, 8, 15) // Read protect
     69#define STM32F4_FLASH_OPTCR_RDP_GET(reg)  BSP_FLD32GET(reg, 8, 15)
     70#define STM32F4_FLASH_OPTCR_RDP_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
     71#define STM32F4_FLASH_OPTCR_USER(val) BSP_FLD32(val, 5, 7)  // User option bytes
     72#define STM32F4_FLASH_OPTCR_USER_GET(reg) BSP_FLD32GET(reg, 5, 7)
     73#define STM32F4_FLASH_OPTCR_USER_SET(reg, val)  BSP_FLD32SET(reg, val, 5, 7)
     74#define STM32F4_FLASH_OPTCR_BOR_LEVEL(val)  BSP_FLD32(val, 2, 3)  // BOR reset level
     75#define STM32F4_FLASH_OPTCR_BOR_LEVEL_GET(reg)  BSP_FLD32GET(reg, 2, 3)
     76#define STM32F4_FLASH_OPTCR_BOR_LEVEL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3)
     77#define STM32F4_FLASH_CR_OPTSTRT  BSP_BIT32(1)  // Option start
     78#define STM32F4_FLASH_CR_OPTLOCK  BSP_BIT32(0)  // Option lock
     79
     80} __attribute__ ((packed));
     81typedef struct stm32f4_flash_s stm32f4_flash;
    5382
    5483#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */
  • c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h

    • Property mode changed from 100644 to 100755
    rea05c438 r040ed0b4  
    3333typedef struct {
    3434  uint32_t cr;
     35#define STM32F4_RCC_CR_PLLI2SRDY  BSP_BIT32(27) // PLLI2S clock ready flag
     36#define STM32F4_RCC_CR_PLLI2SON   BSP_BIT32(26) // PLLI2S enable
     37#define STM32F4_RCC_CR_PLLRDY     BSP_BIT32(25) // Main PLL clock ready flag
     38#define STM32F4_RCC_CR_PLLON      BSP_BIT32(24) // Main PLL enable
     39#define STM32F4_RCC_CR_CSSON      BSP_BIT32(19) // Clock security system enable
     40#define STM32F4_RCC_CR_HSEBYP     BSP_BIT32(18) // HSE clock bypass
     41#define STM32F4_RCC_CR_HSERDY     BSP_BIT32(17) // HSE clock ready flag
     42#define STM32F4_RCC_CR_HSEON      BSP_BIT32(16) // HSE clock enable
     43#define STM32F4_RCC_CR_HSIRDY     BSP_BIT32(1)  // HSI clock ready flag
     44#define STM32F4_RCC_CR_HSION      BSP_BIT32(0)  // HSI clock enable
     45
    3546  uint32_t pllcfgr;
     47#define STM32F4_RCC_PLLCFGR_PLLQ(val) BSP_FLD32(val, 24, 27)
     48#define STM32F4_RCC_PLLCFGR_PLLQ_GET(reg) BSP_FLD32GET(reg, 24, 27)
     49#define STM32F4_RCC_PLLCFGR_PLLQ_SET(reg, val)  BSP_FLD32SET(reg, val, 24, 27)
     50#define STM32F4_RCC_PLLCFGR_SRC   BSP_BIT32(22) // PLL entry clock source
     51#define STM32F4_RCC_PLLCFGR_SRC_HSE STM32F4_RCC_PLLCFGR_SRC
     52#define STM32F4_RCC_PLLCFGR_SRC_HSI 0
     53#define STM32F4_RCC_PLLCFGR_PLLP(val) BSP_FLD32(val, 16, 17)
     54#define STM32F4_RCC_PLLCFGR_PLLP_GET(reg) BSP_FLD32GET(reg, 16, 17)
     55#define STM32F4_RCC_PLLCFGR_PLLP_SET(reg, val)  BSP_FLD32SET(reg, val, 16, 17)
     56#define STM32F4_RCC_PLLCFGR_PLLP_2 STM32F4_RCC_PLLCFGR_PLLP(0)
     57#define STM32F4_RCC_PLLCFGR_PLLP_4 STM32F4_RCC_PLLCFGR_PLLP(1)
     58#define STM32F4_RCC_PLLCFGR_PLLP_6 STM32F4_RCC_PLLCFGR_PLLP(2)
     59#define STM32F4_RCC_PLLCFGR_PLLP_8 STM32F4_RCC_PLLCFGR_PLLP(3)
     60#define STM32F4_RCC_PLLCFGR_PLLN(val) BSP_FLD32(val, 6, 14)
     61#define STM32F4_RCC_PLLCFGR_PLLN_GET(reg) BSP_FLD32GET(reg, 6, 14)
     62#define STM32F4_RCC_PLLCFGR_PLLN_SET(reg, val)  BSP_FLD32SET(reg, val, 6, 14)
     63#define STM32F4_RCC_PLLCFGR_PLLM(val) BSP_FLD32(val, 0, 5)
     64#define STM32F4_RCC_PLLCFGR_PLLM_GET(reg) BSP_FLD32GET(reg, 0, 5)
     65#define STM32F4_RCC_PLLCFGR_PLLM_SET(reg, val)  BSP_FLD32SET(reg, val, 0, 5)
     66
    3667  uint32_t cfgr;
     68#define STM32F4_RCC_CFGR_MCO2(val)  BSP_FLD32(val, 30, 31)  // Microcontroller clock output 2
     69#define STM32F4_RCC_CFGR_MCO2_GET(reg)  BSP_FLD32GET(reg, 30, 31)
     70#define STM32F4_RCC_CFGR_MCO2_SET(reg, val) BSP_FLD32SET(reg, val, 30, 31)
     71#define STM32F4_RCC_CFGR_MCO2_SYSCLK  STM32F4_RCC_CFGR_MCO2(0)
     72#define STM32F4_RCC_CFGR_MCO2_PLLI2S  STM32F4_RCC_CFGR_MCO2(1)
     73#define STM32F4_RCC_CFGR_MCO2_HSE     STM32F4_RCC_CFGR_MCO2(2)
     74#define STM32F4_RCC_CFGR_MCO2_PLL     STM32F4_RCC_CFGR_MCO2(3)
     75#define STM32F4_RCC_CFGR_MCO2_PRE(val)  BSP_FLD32(val, 27, 29)  // MCO2 prescalar
     76#define STM32F4_RCC_CFGR_MCO2_PRE_GET(reg)  BSP_FLD32GET(reg, 27, 29)
     77#define STM32F4_RCC_CFGR_MCO2_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29)
     78#define STM32F4_RCC_CFGR_MCO2_DIV1    STM32F4_RCC_CFGR_MCO2_PRE(0)
     79#define STM32F4_RCC_CFGR_MCO2_DIV2    STM32F4_RCC_CFGR_MCO2_PRE(4)
     80#define STM32F4_RCC_CFGR_MCO2_DIV3    STM32F4_RCC_CFGR_MCO2_PRE(5)
     81#define STM32F4_RCC_CFGR_MCO2_DIV4    STM32F4_RCC_CFGR_MCO2_PRE(6)
     82#define STM32F4_RCC_CFGR_MCO2_DIV5    STM32F4_RCC_CFGR_MCO2_PRE(7)
     83#define STM32F4_RCC_CFGR_MCO1_PRE(val)  BSP_FLD32(val, 24, 26)  // MCO1 prescalar
     84#define STM32F4_RCC_CFGR_MCO1_PRE_GET(reg)  BSP_FLD32GET(reg, 24, 26)
     85#define STM32F4_RCC_CFGR_MCO1_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26)
     86#define STM32F4_RCC_CFGR_MCO1_DIV1    STM32F4_RCC_CFGR_MCO1_PRE(0)
     87#define STM32F4_RCC_CFGR_MCO1_DIV2    STM32F4_RCC_CFGR_MCO1_PRE(4)
     88#define STM32F4_RCC_CFGR_MCO1_DIV3    STM32F4_RCC_CFGR_MCO1_PRE(5)
     89#define STM32F4_RCC_CFGR_MCO1_DIV4    STM32F4_RCC_CFGR_MCO1_PRE(6)
     90#define STM32F4_RCC_CFGR_MCO1_DIV5    STM32F4_RCC_CFGR_MCO1_PRE(7)
     91#define STM32F4_RCC_CFGR_I2SSCR     BSP_BIT32(23) // I2S clock selection
     92#define STM32F4_RCC_CFGR_MCO1(val)  BSP_FLD32(val, 21, 22)  // Microcontroller clock output 1
     93#define STM32F4_RCC_CFGR_MCO1_GET(reg)  BSP_FLD32GET(reg, 21, 22)
     94#define STM32F4_RCC_CFGR_MCO1_SET(reg, val) BSP_FLD32SET(reg, val, 21, 22)
     95#define STM32F4_RCC_CFGR_MCO1_HSI     STM32F4_RCC_CFGR_MCO1(0)
     96#define STM32F4_RCC_CFGR_MCO1_LSE     STM32F4_RCC_CFGR_MCO1(1)
     97#define STM32F4_RCC_CFGR_MCO1_HSE     STM32F4_RCC_CFGR_MCO1(2)
     98#define STM32F4_RCC_CFGR_MCO1_PLL     STM32F4_RCC_CFGR_MCO1(3)
     99#define STM32F4_RCC_CFGR_RTCPRE(val)  BSP_FLD32(val, 16, 20)  // HSE division factor for RTC clock
     100#define STM32F4_RCC_CFGR_RTCPRE_GET(reg)  BSP_FLD32GET(reg, 16, 20)
     101#define STM32F4_RCC_CFGR_RTCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20)
     102#define STM32F4_RCC_CFGR_PPRE2(val) BSP_FLD32(val, 13, 15)  // APB high-speed prescalar (APB2)
     103#define STM32F4_RCC_CFGR_PPRE2_GET(reg) BSP_FLD32GET(reg, 13, 15)
     104#define STM32F4_RCC_CFGR_PPRE2_SET(reg, val)  BSP_FLD32SET(reg, val, 13, 15)
     105#define STM32F4_RCC_CFGR_PPRE2_DIV1   STM32F4_RCC_CFGR_PPRE2(0)
     106#define STM32F4_RCC_CFGR_PPRE2_DIV2   STM32F4_RCC_CFGR_PPRE2(4)
     107#define STM32F4_RCC_CFGR_PPRE2_DIV4   STM32F4_RCC_CFGR_PPRE2(5)
     108#define STM32F4_RCC_CFGR_PPRE2_DIV8   STM32F4_RCC_CFGR_PPRE2(6)
     109#define STM32F4_RCC_CFGR_PPRE2_DIV16  STM32F4_RCC_CFGR_PPRE2(7)
     110#define STM32F4_RCC_CFGR_PPRE1(val) BSP_FLD32(val, 10, 12)  // APB low-speed prescalar (APB1)
     111#define STM32F4_RCC_CFGR_PPRE1_GET(reg) BSP_FLD32GET(reg, 10, 12)
     112#define STM32F4_RCC_CFGR_PPRE1_SET(reg, val)  BSP_FLD32SET(reg, val, 10, 12)
     113#define STM32F4_RCC_CFGR_PPRE1_DIV1   STM32F4_RCC_CFGR_PPRE1(0)
     114#define STM32F4_RCC_CFGR_PPRE1_DIV2   STM32F4_RCC_CFGR_PPRE1(4)
     115#define STM32F4_RCC_CFGR_PPRE1_DIV4   STM32F4_RCC_CFGR_PPRE1(5)
     116#define STM32F4_RCC_CFGR_PPRE1_DIV8   STM32F4_RCC_CFGR_PPRE1(6)
     117#define STM32F4_RCC_CFGR_PPRE1_DIV16  STM32F4_RCC_CFGR_PPRE1(7)
     118#define STM32F4_RCC_CFGR_HPRE(val)  BSP_FLD32(val, 4, 15) // AHB prescalar
     119#define STM32F4_RCC_CFGR_HPRE_GET(reg)  BSP_FLD32GET(reg, 4, 7)
     120#define STM32F4_RCC_CFGR_HPRE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
     121#define STM32F4_RCC_CFGR_HPRE_DIV1    STM32F4_RCC_CFGR_HPRE(0)
     122#define STM32F4_RCC_CFGR_HPRE_DIV2    STM32F4_RCC_CFGR_HPRE(8)
     123#define STM32F4_RCC_CFGR_HPRE_DIV4    STM32F4_RCC_CFGR_HPRE(9)
     124#define STM32F4_RCC_CFGR_HPRE_DIV8    STM32F4_RCC_CFGR_HPRE(10)
     125#define STM32F4_RCC_CFGR_HPRE_DIV16   STM32F4_RCC_CFGR_HPRE(11)
     126#define STM32F4_RCC_CFGR_HPRE_DIV64   STM32F4_RCC_CFGR_HPRE(12)
     127#define STM32F4_RCC_CFGR_HPRE_DIV128  STM32F4_RCC_CFGR_HPRE(13)
     128#define STM32F4_RCC_CFGR_HPRE_DIV256  STM32F4_RCC_CFGR_HPRE(14)
     129#define STM32F4_RCC_CFGR_HPRE_DIV512  STM32F4_RCC_CFGR_HPRE(15)
     130#define STM32F4_RCC_CFGR_SWS(val) BSP_FLD32(val, 2, 3)  // System clock switch status
     131#define STM32F4_RCC_CFGR_SWS_GET(reg) BSP_FLD32GET(reg, 2, 3)
     132#define STM32F4_RCC_CFGR_SWS_SET(reg, val)  BSP_FLD32SET(reg, val, 2, 3)
     133#define STM32F4_RCC_CFGR_SWS_HSI  STM32F4_RCC_CFGR_SWS(0)
     134#define STM32F4_RCC_CFGR_SWS_HSE  STM32F4_RCC_CFGR_SWS(1)
     135#define STM32F4_RCC_CFGR_SWS_PLL  STM32F4_RCC_CFGR_SWS(2)
     136#define STM32F4_RCC_CFGR_SW(val)  BSP_FLD32(val, 0, 1)  // System clock switch
     137#define STM32F4_RCC_CFGR_SW_GET(reg)  BSP_FLD32GET(reg, 0, 1)
     138#define STM32F4_RCC_CFGR_SW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
     139#define STM32F4_RCC_CFGR_SW_HSI STM32F4_RCC_CFGR_SW(0)
     140#define STM32F4_RCC_CFGR_SW_HSE STM32F4_RCC_CFGR_SW(1)
     141#define STM32F4_RCC_CFGR_SW_PLL STM32F4_RCC_CFGR_SW(2)
     142
    37143  uint32_t cir;
    38   uint32_t ahbrstr[ 3 ];
     144
     145  uint32_t ahbrstr [3];
     146
    39147  uint32_t reserved_1c;
    40   uint32_t apbrstr[ 2 ];
    41   uint32_t reserved_28[ 2 ];
    42   uint32_t ahbenr[ 3 ];
     148
     149  uint32_t apbrstr [2];
     150
     151  uint32_t reserved_28 [2];
     152
     153  uint32_t ahbenr [3];
     154
    43155  uint32_t reserved_3c;
    44   uint32_t apbenr[ 2 ];
    45   uint32_t reserved_48[ 2 ];
    46   uint32_t ahblpenr[ 3 ];
     156
     157  uint32_t apbenr [2];
     158
     159  uint32_t reserved_48 [2];
     160
     161  uint32_t ahblpenr [3];
     162
    47163  uint32_t reserved_5c;
    48   uint32_t apblpenr[ 2 ];
    49   uint32_t reserved_68[ 2 ];
     164
     165  uint32_t apblpenr [2];
     166
     167  uint32_t reserved_68 [2];
     168
    50169  uint32_t bdcr;
     170
    51171  uint32_t csr;
    52   uint32_t reserved_78[ 2 ];
     172
     173  uint32_t reserved_78 [2];
     174
    53175  uint32_t sscgr;
     176
    54177  uint32_t plli2scfgr;
     178
    55179} stm32f4_rcc;
    56180
  • c/src/lib/libbsp/arm/stm32f4/preinstall.am

    rea05c438 r040ed0b4  
    114114PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h
    115115
     116$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h: include/stm32f4xxxx_adc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     117        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h
     118PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h
     119
     120$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h: include/stm32f4xxxx_exti.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     121        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h
     122PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h
     123
    116124$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h: include/stm32f4xxxx_gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    117125        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h
     
    122130PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h
    123131
     132$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h: include/stm32f4xxxx_pwr.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     133        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h
     134PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h
     135
     136$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h: include/stm32f4xxxx_syscfg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     137        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h
     138PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h
     139
     140$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h: include/stm32f4xxxx_tim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     141        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h
     142PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h
     143
    124144$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h: include/stm32f4xxxx_flash.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    125145        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h
    126146PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h
     147
     148$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h: include/stm32f4xxxx_otgfs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     149        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h
     150PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h
    127151
    128152$(PROJECT_INCLUDE)/bsp/stm32_i2c.h: include/stm32_i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
  • c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c

    rea05c438 r040ed0b4  
    175175   * best if results in the 48MHz for the USB
    176176   */
    177   pll_q = ( (long) ( src_clk * pll_n + src_clk * pll_n / 2 ) ) / pll_m / 48;
     177  pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48;
    178178
    179179  if ( pll_q < 2 ) {
     
    258258   * TODO implement some math to use flash on as low latancy as possible
    259259   */
    260   flash->acr = FLASH_ACR_LATENCY( 5 ) | /* latency */
    261                FLASH_ACR_ICEN |       /* instruction cache */
    262                FLASH_ACR_DCEN;        /* data cache */
     260  flash->acr = STM32F4_FLASH_ACR_LATENCY( 5 ) | /* latency */
     261               STM32F4_FLASH_ACR_ICEN |       /* instruction cache */
     262               STM32F4_FLASH_ACR_DCEN |        /* data cache */
     263               STM32F4_FLASH_ACR_PRFTEN;
    263264
    264265  /* turn on PLL */
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