Changeset 03c8223 in rtems


Ignore:
Timestamp:
Jul 31, 1997, 6:45:32 PM (24 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
db91520
Parents:
c3fec1c
Message:

Added more info.

Location:
doc/supplements/powerpc
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • doc/supplements/powerpc/bsp.t

    rc3fec1c r03c8223  
    2626An RTEMS Board Support Package (BSP) must be designed
    2727to support a particular processor and target board combination.
    28 This chapter presents a discussion of SPARC specific BSP issues.
     28This chapter presents a discussion of PowerPC specific BSP issues.
    2929For more information on developing a BSP, refer to the chapter
    3030titled Board Support Packages in the RTEMS
    … …  
    3737
    3838An RTEMS based application is initiated or
    39 re-initiated when the SPARC processor is reset.  When the SPARC
     39re-initiated when the PowerPC processor is reset.  When the PowerPC
    4040is reset, the processor performs the following actions:
    4141
    4242@itemize @bullet
    43 @item the enable trap (ET) of the psr is set to 0 to disable
    44 traps,
     43@item TBD
    4544
    46 @item the supervisor bit (S) of the psr is set to 1 to enter
    47 supervisor mode, and
     45@item TBD
    4846
    49 @item the PC is set 0 and the nPC is set to 4.
     47@item TBD
    5048@end itemize
    5149
    52 The processor then begins to execute the code at
    53 location 0.  It is important to note that all fields in the psr
     50The processor then begins to execute the code at location 0x00100. 
     51By using the SRR1 bit corresponding to MSR[RI] the softwere may
     52distinguish between power-on reset and other types of system resets.
     53
     54It is important to note that all fields in the psr
    5455are not explicitly set by the above steps and all other
    5556registers retain their value from the previous execution mode.
    … …  
    8081
    8182In addition to the requirements described in the
    82 Board Support Packages chapter of the @value{RTEMS-LANGUAGE}
     83Board Support Packages chapter of the @value{LANGUAGE}
    8384Applications User's Manual for the reset code
    8485which is executed before the call to

  • doc/supplements/powerpc/bsp.texi

    rc3fec1c r03c8223  
    2626An RTEMS Board Support Package (BSP) must be designed
    2727to support a particular processor and target board combination.
    28 This chapter presents a discussion of SPARC specific BSP issues.
     28This chapter presents a discussion of PowerPC specific BSP issues.
    2929For more information on developing a BSP, refer to the chapter
    3030titled Board Support Packages in the RTEMS
    … …  
    3737
    3838An RTEMS based application is initiated or
    39 re-initiated when the SPARC processor is reset.  When the SPARC
     39re-initiated when the PowerPC processor is reset.  When the PowerPC
    4040is reset, the processor performs the following actions:
    4141
    4242@itemize @bullet
    43 @item the enable trap (ET) of the psr is set to 0 to disable
    44 traps,
     43@item TBD
    4544
    46 @item the supervisor bit (S) of the psr is set to 1 to enter
    47 supervisor mode, and
     45@item TBD
    4846
    49 @item the PC is set 0 and the nPC is set to 4.
     47@item TBD
    5048@end itemize
    5149
    52 The processor then begins to execute the code at
    53 location 0.  It is important to note that all fields in the psr
     50The processor then begins to execute the code at location 0x00100. 
     51By using the SRR1 bit corresponding to MSR[RI] the softwere may
     52distinguish between power-on reset and other types of system resets.
     53
     54It is important to note that all fields in the psr
    5455are not explicitly set by the above steps and all other
    5556registers retain their value from the previous execution mode.
    … …  
    8081
    8182In addition to the requirements described in the
    82 Board Support Packages chapter of the @value{RTEMS-LANGUAGE}
     83Board Support Packages chapter of the @value{LANGUAGE}
    8384Applications User's Manual for the reset code
    8485which is executed before the call to

  • doc/supplements/powerpc/cpumodel.t

    rc3fec1c r03c8223  
    5757* CPU Model Dependent Features Critical Interrupts::
    5858* CPU Model Dependent Features MSR Values::
    59 * CPU Model Dependent Features FPU Status Control Register Values::
    6059* CPU Model Dependent Features Use Multiword Load/Store Instructions::
    6160* CPU Model Dependent Features Instruction Cache Size::
    6261* CPU Model Dependent Features Data Cache Size::
     62* CPU Model Dependent Features Debug Model::
     63* CPU Model Dependent Features Low Power Model::
    6364@end menu
    6465@end ifinfo
    … …  
    100101@subsection Floating Point Unit
    101102
    102 The macro PPC_HAS_FPU is set to 1 to indicate that
    103 this CPU model has a hardware floating point unit and 0
    104 otherwise.
     103The macro PPC_HAS_FPU is set to 1 to indicate that this CPU model
     104has a hardware floating point unit and 0 otherwise.
    105105
    106106@ifinfo
    … …  
    109109@subsection Alignment
    110110
    111 The macro PPC_ALIGNMENT is set to
     111The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
     112requirement for data types on a byte boundary.  This value is used
     113to derive the alignment restrictions for memory allocated from
     114regions and partitions.
    112115
    113116@ifinfo
    … …  
    116119@subsection Cache Alignment
    117120
    118 The macro PPC_CACHE_ALIGNMENT is set to
    119 
    120 Similarly, the macro PPC_CACHE_ALIGN_POWER is set to the
     121The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache.  It is
     122used to align the entry point of critical routines so that as much code
     123as possible can be retrieved with the initial read into cache.  This
     124is done for the interrupt handler as well as the context switch routines.
     125
     126In addition, the "shortcut" data structure used by the PowerPC implementation
     127to ease access to data elements frequently accessed by RTEMS routines
     128implemented in assembly language is aligned using this value.
    121129
    122130@ifinfo
    … …  
    125133@subsection Maximum Interrupts
    126134
    127 The macro PPC_INTERRUPT_MAX is set to
     135The macro PPC_INTERRUPT_MAX is set to the number of exception sources
     136supported by this PowerPC model.
    128137
    129138@ifinfo
    … …  
    132141@subsection Has Double Precision Floating Point
    133142
    134 The macro PPC_HAS_DOUBLE is set to
     143The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model
     144has support for double precision floating point numbers.  This is
     145important because the floating point registers need only be four bytes
     146wide (not eight) if double precision is not supported.
    135147
    136148@ifinfo
    … …  
    139151@subsection Critical Interrupts
    140152
    141 The macro PPC_HAS_RFCI is set to
    142 
    143 @ifinfo
    144 @node CPU Model Dependent Features MSR Values, CPU Model Dependent Features FPU Status Control Register Values, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags
     153The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model
     154has the Critical Interrupt capability as defined by the IBM 403 models.
     155
     156@ifinfo
     157@node CPU Model Dependent Features MSR Values, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags
    145158@end ifinfo
    146159@subsection MSR Values
    147160
    148 The macro PPC_MSR_DISABLE_MASK is set to
    149 
    150161The macro PPC_MSR_INITIAL is set to
    151162
    152 The macro PPC_MSR_0 is set to
    153 
    154 The macro PPC_MSR_1 is set to
    155 
    156 The macro PPC_MSR_2 is set to
    157 
    158 The macro PPC_MSR_3 is set to
    159 
    160 @ifinfo
    161 @node CPU Model Dependent Features FPU Status Control Register Values, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features MSR Values, CPU Model Dependent Features CPU Model Feature Flags
    162 @end ifinfo
    163 @subsection FPU Status Control Register Values
    164 
    165 The macro PPC_INIT_FPSCR is set to
    166 
    167 @ifinfo
    168 @node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features FPU Status Control Register Values, CPU Model Dependent Features CPU Model Feature Flags
     163@ifinfo
     164@node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features MSR Values, CPU Model Dependent Features CPU Model Feature Flags
    169165@end ifinfo
    170166@subsection Use Multiword Load/Store Instructions
    171167
    172 The macro PPC_USE_MULTIPLE is set to
     168The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
     169store instructions should be used to perform context switch operations.
     170The relative efficiency of multiword load and store instructions versus
     171an equivalent set of single word load and store instructions varies based
     172upon the PowerPC model.
    173173
    174174@ifinfo
    … …  
    177177@subsection Instruction Cache Size
    178178
    179 The macro PPC_I_CACHE is set to
    180 
    181 @ifinfo
    182 @node CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features CPU Model Implementation Notes, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features CPU Model Feature Flags
     179The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
     180
     181@ifinfo
     182@node CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features Debug Model, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features CPU Model Feature Flags
    183183@end ifinfo
    184184@subsection Data Cache Size
    185185
    186 The macro PPC_D_CACHE is set to
    187 
    188 @ifinfo
    189 @node CPU Model Dependent Features CPU Model Implementation Notes, Calling Conventions, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features
     186The macro PPC_D_CACHE is set to the size in bytes of the data cache.
     187
     188@ifinfo
     189@node CPU Model Dependent Features Debug Model, CPU Model Dependent Features Low Power Model, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features CPU Model Feature Flags
     190@end ifinfo
     191@subsection Debug Model
     192
     193The macro PPC_DEBUG_MODEL
     194
     195@table @b
     196
     197@item @code{PPC_DEBUG_MODEL_STANDARD}
     198indicates XXX
     199
     200@item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY}
     201indicates XXX
     202
     203@item @code{PPC_DEBUG_MODEL_IBM4xx}
     204indicates XXX
     205
     206@end table
     207
     208@ifinfo
     209@node CPU Model Dependent Features Low Power Model, CPU Model Dependent Features CPU Model Implementation Notes, CPU Model Dependent Features Debug Model, CPU Model Dependent Features CPU Model Feature Flags
     210@end ifinfo
     211@subsection Low Power Model
     212
     213The macro PPC_LOW_POWER_MODE
     214
     215@table @b
     216
     217@item @code{PPC_LOW_POWER_MODE_NONE}
     218indicates XXX
     219
     220@item @code{PPC_LOW_POWER_MODE_STANDARD}
     221indicates XXX
     222
     223@end table
     224
     225
     226@ifinfo
     227@node CPU Model Dependent Features CPU Model Implementation Notes, Calling Conventions, CPU Model Dependent Features Low Power Model, CPU Model Dependent Features
    190228@end ifinfo
    191229@section CPU Model Implementation Notes

  • doc/supplements/powerpc/cpumodel.texi

    rc3fec1c r03c8223  
    5757* CPU Model Dependent Features Critical Interrupts::
    5858* CPU Model Dependent Features MSR Values::
    59 * CPU Model Dependent Features FPU Status Control Register Values::
    6059* CPU Model Dependent Features Use Multiword Load/Store Instructions::
    6160* CPU Model Dependent Features Instruction Cache Size::
    6261* CPU Model Dependent Features Data Cache Size::
     62* CPU Model Dependent Features Debug Model::
     63* CPU Model Dependent Features Low Power Model::
    6364@end menu
    6465@end ifinfo
    … …  
    100101@subsection Floating Point Unit
    101102
    102 The macro PPC_HAS_FPU is set to 1 to indicate that
    103 this CPU model has a hardware floating point unit and 0
    104 otherwise.
     103The macro PPC_HAS_FPU is set to 1 to indicate that this CPU model
     104has a hardware floating point unit and 0 otherwise.
    105105
    106106@ifinfo
    … …  
    109109@subsection Alignment
    110110
    111 The macro PPC_ALIGNMENT is set to
     111The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
     112requirement for data types on a byte boundary.  This value is used
     113to derive the alignment restrictions for memory allocated from
     114regions and partitions.
    112115
    113116@ifinfo
    … …  
    116119@subsection Cache Alignment
    117120
    118 The macro PPC_CACHE_ALIGNMENT is set to
    119 
    120 Similarly, the macro PPC_CACHE_ALIGN_POWER is set to the
     121The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache.  It is
     122used to align the entry point of critical routines so that as much code
     123as possible can be retrieved with the initial read into cache.  This
     124is done for the interrupt handler as well as the context switch routines.
     125
     126In addition, the "shortcut" data structure used by the PowerPC implementation
     127to ease access to data elements frequently accessed by RTEMS routines
     128implemented in assembly language is aligned using this value.
    121129
    122130@ifinfo
    … …  
    125133@subsection Maximum Interrupts
    126134
    127 The macro PPC_INTERRUPT_MAX is set to
     135The macro PPC_INTERRUPT_MAX is set to the number of exception sources
     136supported by this PowerPC model.
    128137
    129138@ifinfo
    … …  
    132141@subsection Has Double Precision Floating Point
    133142
    134 The macro PPC_HAS_DOUBLE is set to
     143The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model
     144has support for double precision floating point numbers.  This is
     145important because the floating point registers need only be four bytes
     146wide (not eight) if double precision is not supported.
    135147
    136148@ifinfo
    … …  
    139151@subsection Critical Interrupts
    140152
    141 The macro PPC_HAS_RFCI is set to
    142 
    143 @ifinfo
    144 @node CPU Model Dependent Features MSR Values, CPU Model Dependent Features FPU Status Control Register Values, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags
     153The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model
     154has the Critical Interrupt capability as defined by the IBM 403 models.
     155
     156@ifinfo
     157@node CPU Model Dependent Features MSR Values, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags
    145158@end ifinfo
    146159@subsection MSR Values
    147160
    148 The macro PPC_MSR_DISABLE_MASK is set to
    149 
    150161The macro PPC_MSR_INITIAL is set to
    151162
    152 The macro PPC_MSR_0 is set to
    153 
    154 The macro PPC_MSR_1 is set to
    155 
    156 The macro PPC_MSR_2 is set to
    157 
    158 The macro PPC_MSR_3 is set to
    159 
    160 @ifinfo
    161 @node CPU Model Dependent Features FPU Status Control Register Values, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features MSR Values, CPU Model Dependent Features CPU Model Feature Flags
    162 @end ifinfo
    163 @subsection FPU Status Control Register Values
    164 
    165 The macro PPC_INIT_FPSCR is set to
    166 
    167 @ifinfo
    168 @node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features FPU Status Control Register Values, CPU Model Dependent Features CPU Model Feature Flags
     163@ifinfo
     164@node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features MSR Values, CPU Model Dependent Features CPU Model Feature Flags
    169165@end ifinfo
    170166@subsection Use Multiword Load/Store Instructions
    171167
    172 The macro PPC_USE_MULTIPLE is set to
     168The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
     169store instructions should be used to perform context switch operations.
     170The relative efficiency of multiword load and store instructions versus
     171an equivalent set of single word load and store instructions varies based
     172upon the PowerPC model.
    173173
    174174@ifinfo
    … …  
    177177@subsection Instruction Cache Size
    178178
    179 The macro PPC_I_CACHE is set to
    180 
    181 @ifinfo
    182 @node CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features CPU Model Implementation Notes, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features CPU Model Feature Flags
     179The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
     180
     181@ifinfo
     182@node CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features Debug Model, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features CPU Model Feature Flags
    183183@end ifinfo
    184184@subsection Data Cache Size
    185185
    186 The macro PPC_D_CACHE is set to
    187 
    188 @ifinfo
    189 @node CPU Model Dependent Features CPU Model Implementation Notes, Calling Conventions, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features
     186The macro PPC_D_CACHE is set to the size in bytes of the data cache.
     187
     188@ifinfo
     189@node CPU Model Dependent Features Debug Model, CPU Model Dependent Features Low Power Model, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features CPU Model Feature Flags
     190@end ifinfo
     191@subsection Debug Model
     192
     193The macro PPC_DEBUG_MODEL
     194
     195@table @b
     196
     197@item @code{PPC_DEBUG_MODEL_STANDARD}
     198indicates XXX
     199
     200@item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY}
     201indicates XXX
     202
     203@item @code{PPC_DEBUG_MODEL_IBM4xx}
     204indicates XXX
     205
     206@end table
     207
     208@ifinfo
     209@node CPU Model Dependent Features Low Power Model, CPU Model Dependent Features CPU Model Implementation Notes, CPU Model Dependent Features Debug Model, CPU Model Dependent Features CPU Model Feature Flags
     210@end ifinfo
     211@subsection Low Power Model
     212
     213The macro PPC_LOW_POWER_MODE
     214
     215@table @b
     216
     217@item @code{PPC_LOW_POWER_MODE_NONE}
     218indicates XXX
     219
     220@item @code{PPC_LOW_POWER_MODE_STANDARD}
     221indicates XXX
     222
     223@end table
     224
     225
     226@ifinfo
     227@node CPU Model Dependent Features CPU Model Implementation Notes, Calling Conventions, CPU Model Dependent Features Low Power Model, CPU Model Dependent Features
    190228@end ifinfo
    191229@section CPU Model Implementation Notes

  • doc/supplements/powerpc/intr.t

    rc3fec1c r03c8223  
    1414@menu
    1515* Interrupt Processing Introduction::
    16 * Interrupt Processing Synchronous Versus Asynchronous Traps::
     16* Interrupt Processing Synchronous Versus Asynchronous Exceptions::
    1717* Interrupt Processing Vectoring of Interrupt Handler::
    18 * Interrupt Processing Traps and Register Windows::
    1918* Interrupt Processing Interrupt Levels::
    2019* Interrupt Processing Disabling of Interrupts by RTEMS::
    … …  
    2423
    2524@ifinfo
    26 @node Interrupt Processing Introduction, Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing, Interrupt Processing
     25@node Interrupt Processing Introduction, Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing, Interrupt Processing
    2726@end ifinfo
    2827@section Introduction
    … …  
    3938details of interrupt processing, it is important to understand
    4039how the RTEMS interrupt manager is mapped onto the processor's
    41 unique architecture. Discussed in this chapter are the SPARC's
     40unique architecture. Discussed in this chapter are the PPC's
    4241interrupt response and control mechanisms as they pertain to
    4342RTEMS.
    4443
    4544RTEMS and associated documentation uses the terms
    46 interrupt and vector.  In the SPARC architecture, these terms
    47 correspond to traps and trap type, respectively.  The terms will
     45interrupt and vector.  In the PPC architecture, these terms
     46correspond to exception and exception handler, respectively.  The terms will
    4847be used interchangeably in this manual.
    4948
    5049@ifinfo
    51 @node Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Introduction, Interrupt Processing
     50@node Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Introduction, Interrupt Processing
    5251@end ifinfo
    53 @section Synchronous Versus Asynchronous Traps
     52@section Synchronous Versus Asynchronous Exceptions
    5453
    55 The SPARC architecture includes two classes of traps:
    56 synchronous and asynchronous.  Asynchronous traps occur when an
    57 external event interrupts the processor.  These traps are not
    58 associated with any instruction executed by the processor and
    59 logically occur between instructions.  The instruction currently
    60 in the execute stage of the processor is allowed to complete
    61 although subsequent instructions are annulled.  The return
    62 address reported by the processor for asynchronous traps is the
    63 pair of instructions following the current instruction.
     54In the PPC architecture exceptions can be either precise or
     55imprecise and either synchronous or asynchronous.  Asynchronous
     56exceptions occur when an external event interrupts the processor.
     57Synchronous exceptions are caused by the actions of an
     58instruction. During an exception SRR0 is used to calculate where
     59instruction processing should resume.  All instructions prior to
     60the resume instruction will have completed execution.  SRR1 is used to
     61store the machine status.
    6462
    65 Synchronous traps are caused by the actions of an
    66 instruction.  The trap stimulus in this case either occurs
    67 internally to the processor or is from an external signal that
    68 was provoked by the instruction.  These traps are taken
    69 immediately and the instruction that caused the trap is aborted
    70 before any state changes occur in the processor itself.   The
    71 return address reported by the processor for synchronous traps
    72 is the instruction which caused the trap and the following
    73 instruction.
     63There are two asynchronous nonmaskable, highest-priority exceptions
     64system reset and machine check.  There are two asynchrononous maskable
     65low-priority exceptions external interrupt and decrementer.  Nonmaskable
     66execptions are never delayed, therefore if two nonmaskable, asynchronous
     67exceptions occur in immediate succession, the state information saved by
     68the first exception may be overwritten when the subsequent exception occurs.
     69
     70The PowerPC arcitecure defines one imprecise exception, the imprecise
     71floating point enabled exception.  All other synchronous exceptions are
     72precise.  The synchronization occuring during asynchronous precise
     73exceptions conforms to the requirements for context synchronization.
    7474
    7575@ifinfo
    76 @node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Traps and Register Windows, Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing
     76@node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Levels, Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing
    7777@end ifinfo
    7878@section Vectoring of Interrupt Handler
    7979
    80 Upon receipt of an interrupt the SPARC automatically
     80Upon determining that an exception can be taken the PPC automatically
    8181performs the following actions:
    8282
    8383@itemize @bullet
    84 @item disables traps (sets the ET bit of the psr to 0),
     84@item an instruction address is loaded into SRR0
    8585
    86 @item the S bit of the psr is copied into the Previous
    87 Supervisor Mode (PS) bit of the psr,
     86@item bits 33-36 and 42-47 of SRR1 are loaded with information
     87specific to the exception.
    8888
    89 @item the cwp is decremented by one (modulo the number of
    90 register windows) to activate a trap window,
     89@item bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding
     90bits from the MSR.
    9191
    92 @item the PC and nPC are loaded into local register 1 and 2
    93 (l0 and l1),
     92@item the MSR is set based upon the exception type.
    9493
    95 @item the trap type (tt) field of the Trap Base Register (TBR)
    96 is set to the appropriate value, and
     94@item instruction fetch and execution resumes, using the new MSR value, at a location specific to the execption type.
    9795
    98 @item if the trap is not a reset, then the PC is written with
    99 the contents of the TBR and the nPC is written with TBR + 4.  If
    100 the trap is a reset, then the PC is set to zero and the nPC is
    101 set to 4.
    10296@end itemize
    10397
    104 Trap processing on the SPARC has two features which
    105 are noticeably different than interrupt processing on other
    106 architectures.  First, the value of psr register in effect
    107 immediately before the trap occurred is not explicitly saved.
    108 Instead only reversible alterations are made to it.  Second, the
    109 Processor Interrupt Level (pil) is not set to correspond to that
    110 of the interrupt being processed.  When a trap occurs, ALL
    111 subsequent traps are disabled.  In order to safely invoke a
    112 subroutine during trap handling, traps must be enabled to allow
    113 for the possibility of register window overflow and underflow
    114 traps.
    11598
    11699If the interrupt handler was installed as an RTEMS
    … …  
    123106
    124107@item insures that a register window is available for
    125 subsequent traps,
     108subsequent exceptions,
    126109
    127110@item if this is the outermost (i.e. non-nested) interrupt,
    … …  
    129112to the interrupt stack,
    130113
    131 @item enables traps,
     114@item enables exceptions,
    132115
    133116@item invokes the vectors to a user interrupt service routine (ISR).
    134117@end itemize
    135118
    136 Asynchronous interrupts are ignored while traps are
    137 disabled.  Synchronous traps which occur while traps are
     119Asynchronous interrupts are ignored while exceptions are
     120disabled.  Synchronous interrupts which occur while are
    138121disabled result in the CPU being forced into an error mode.
    139122
    … …  
    143126
    144127@ifinfo
    145 @node Interrupt Processing Traps and Register Windows, Interrupt Processing Interrupt Levels, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing
    146 @end ifinfo
    147 @section Traps and Register Windows
    148 
    149 One of the register windows must be reserved at all
    150 times for trap processing.  This is critical to the proper
    151 operation of the trap mechanism in the SPARC architecture.  It
    152 is the responsibility of the trap handler to insure that there
    153 is a register window available for a subsequent trap before
    154 re-enabling traps.  It is likely that any high level language
    155 routines invoked by the trap handler (such as a user-provided
    156 RTEMS interrupt handler) will allocate a new register window.
    157 The save operation could result in a window overflow trap.  This
    158 trap cannot be correctly processed unless (1) traps are enabled
    159 and (2) a register window is reserved for traps.  Thus, the
    160 RTEMS interrupt handler insures that a register window is
    161 available for subsequent traps before enabling traps and
    162 invoking the user's interrupt handler.
    163 
    164 @ifinfo
    165 @node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Traps and Register Windows, Interrupt Processing
     128@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing
    166129@end ifinfo
    167130@section Interrupt Levels
    168131
    169 Sixteen levels (0-15) of interrupt priorities are
    170 supported by the SPARC architecture with level fifteen (15)
     132TBD levels (0-TBD) of interrupt priorities are
     133supported by the PowerPC architecture with level TBD (TBD)
    171134being the highest priority.  Level zero (0) indicates that
    172135interrupts are fully enabled.  Interrupt requests for interrupts
    … …  
    174137level are ignored.
    175138
    176 Although RTEMS supports 256 interrupt levels, the
    177 SPARC only supports sixteen.  RTEMS interrupt levels 0 through
    178 15 directly correspond to SPARC processor interrupt levels.  All
    179 other RTEMS interrupt levels are undefined and their behavior is
     139TBD
     140All other RTEMS interrupt levels are undefined and their behavior is
    180141unpredictable.
    181142
    … …  
    187148During the execution of directive calls, critical
    188149sections of code may be executed.  When these sections are
    189 encountered, RTEMS disables interrupts to level seven (15)
     150encountered, RTEMS disables interrupts to level TBD (TBD)
    190151before the execution of this section and restores them to the
    191152previous level upon completion of the section.  RTEMS has been
    192153optimized to insure that interrupts are disabled for less than
    193 RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
    194 Mhz PowerPC 603e with zero wait states.
    195 These numbers will vary based the number of wait states and
    196 processor speed present on the target board.
     154RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a
     155RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz PowerPC 603e with zero
     156wait states.  These numbers will vary based the number of wait
     157states and processor speed present on the target board.
    197158[NOTE:  The maximum period with interrupts disabled is hand calculated.  This
    198159calculation was last performed for Release
    … …  
    201162[NOTE: It is thought that the length of time at which
    202163the processor interrupt level is elevated to fifteen by RTEMS is
    203 not anywhere near as long as the length of time ALL traps are
     164not anywhere near as long as the length of time ALL exceptions are
    204165disabled as part of the "flush all register windows" operation.]
    205166
    … …  
    216177@section Interrupt Stack
    217178
    218 The SPARC architecture does not provide for a
    219 dedicated interrupt stack.  Thus by default, trap handlers would
     179The PowerPC architecture does not provide for a
     180dedicated interrupt stack.  Thus by default, exception handlers would
    220181execute on the stack of the RTEMS task which they interrupted.
    221182This artificially inflates the stack requirements for each task
    … …  
    223184account for the worst case interrupt stack requirements in
    224185addition to it's own worst case usage.  RTEMS addresses this
    225 problem on the SPARC by providing a dedicated interrupt stack
     186problem on the PowerPC by providing a dedicated interrupt stack
    226187managed by software.
    227188
    … …  
    233194the interrupt stack before invoking the installed handler.
    234195
     196
     197

  • doc/supplements/powerpc/intr_NOTIMES.t

    rc3fec1c r03c8223  
    1414@menu
    1515* Interrupt Processing Introduction::
    16 * Interrupt Processing Synchronous Versus Asynchronous Traps::
     16* Interrupt Processing Synchronous Versus Asynchronous Exceptions::
    1717* Interrupt Processing Vectoring of Interrupt Handler::
    18 * Interrupt Processing Traps and Register Windows::
    1918* Interrupt Processing Interrupt Levels::
    2019* Interrupt Processing Disabling of Interrupts by RTEMS::
    … …  
    2423
    2524@ifinfo
    26 @node Interrupt Processing Introduction, Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing, Interrupt Processing
     25@node Interrupt Processing Introduction, Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing, Interrupt Processing
    2726@end ifinfo
    2827@section Introduction
    … …  
    3938details of interrupt processing, it is important to understand
    4039how the RTEMS interrupt manager is mapped onto the processor's
    41 unique architecture. Discussed in this chapter are the SPARC's
     40unique architecture. Discussed in this chapter are the PPC's
    4241interrupt response and control mechanisms as they pertain to
    4342RTEMS.
    4443
    4544RTEMS and associated documentation uses the terms
    46 interrupt and vector.  In the SPARC architecture, these terms
    47 correspond to traps and trap type, respectively.  The terms will
     45interrupt and vector.  In the PPC architecture, these terms
     46correspond to exception and exception handler, respectively.  The terms will
    4847be used interchangeably in this manual.
    4948
    5049@ifinfo
    51 @node Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Introduction, Interrupt Processing
     50@node Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Introduction, Interrupt Processing
    5251@end ifinfo
    53 @section Synchronous Versus Asynchronous Traps
     52@section Synchronous Versus Asynchronous Exceptions
    5453
    55 The SPARC architecture includes two classes of traps:
    56 synchronous and asynchronous.  Asynchronous traps occur when an
    57 external event interrupts the processor.  These traps are not
    58 associated with any instruction executed by the processor and
    59 logically occur between instructions.  The instruction currently
    60 in the execute stage of the processor is allowed to complete
    61 although subsequent instructions are annulled.  The return
    62 address reported by the processor for asynchronous traps is the
    63 pair of instructions following the current instruction.
     54In the PPC architecture exceptions can be either precise or
     55imprecise and either synchronous or asynchronous.  Asynchronous
     56exceptions occur when an external event interrupts the processor.
     57Synchronous exceptions are caused by the actions of an
     58instruction. During an exception SRR0 is used to calculate where
     59instruction processing should resume.  All instructions prior to
     60the resume instruction will have completed execution.  SRR1 is used to
     61store the machine status.
    6462
    65 Synchronous traps are caused by the actions of an
    66 instruction.  The trap stimulus in this case either occurs
    67 internally to the processor or is from an external signal that
    68 was provoked by the instruction.  These traps are taken
    69 immediately and the instruction that caused the trap is aborted
    70 before any state changes occur in the processor itself.   The
    71 return address reported by the processor for synchronous traps
    72 is the instruction which caused the trap and the following
    73 instruction.
     63There are two asynchronous nonmaskable, highest-priority exceptions
     64system reset and machine check.  There are two asynchrononous maskable
     65low-priority exceptions external interrupt and decrementer.  Nonmaskable
     66execptions are never delayed, therefore if two nonmaskable, asynchronous
     67exceptions occur in immediate succession, the state information saved by
     68the first exception may be overwritten when the subsequent exception occurs.
     69
     70The PowerPC arcitecure defines one imprecise exception, the imprecise
     71floating point enabled exception.  All other synchronous exceptions are
     72precise.  The synchronization occuring during asynchronous precise
     73exceptions conforms to the requirements for context synchronization.
    7474
    7575@ifinfo
    76 @node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Traps and Register Windows, Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing
     76@node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Levels, Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing
    7777@end ifinfo
    7878@section Vectoring of Interrupt Handler
    7979
    80 Upon receipt of an interrupt the SPARC automatically
     80Upon determining that an exception can be taken the PPC automatically
    8181performs the following actions:
    8282
    8383@itemize @bullet
    84 @item disables traps (sets the ET bit of the psr to 0),
     84@item an instruction address is loaded into SRR0
    8585
    86 @item the S bit of the psr is copied into the Previous
    87 Supervisor Mode (PS) bit of the psr,
     86@item bits 33-36 and 42-47 of SRR1 are loaded with information
     87specific to the exception.
    8888
    89 @item the cwp is decremented by one (modulo the number of
    90 register windows) to activate a trap window,
     89@item bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding
     90bits from the MSR.
    9191
    92 @item the PC and nPC are loaded into local register 1 and 2
    93 (l0 and l1),
     92@item the MSR is set based upon the exception type.
    9493
    95 @item the trap type (tt) field of the Trap Base Register (TBR)
    96 is set to the appropriate value, and
     94@item instruction fetch and execution resumes, using the new MSR value, at a location specific to the execption type.
    9795
    98 @item if the trap is not a reset, then the PC is written with
    99 the contents of the TBR and the nPC is written with TBR + 4.  If
    100 the trap is a reset, then the PC is set to zero and the nPC is
    101 set to 4.
    10296@end itemize
    10397
    104 Trap processing on the SPARC has two features which
    105 are noticeably different than interrupt processing on other
    106 architectures.  First, the value of psr register in effect
    107 immediately before the trap occurred is not explicitly saved.
    108 Instead only reversible alterations are made to it.  Second, the
    109 Processor Interrupt Level (pil) is not set to correspond to that
    110 of the interrupt being processed.  When a trap occurs, ALL
    111 subsequent traps are disabled.  In order to safely invoke a
    112 subroutine during trap handling, traps must be enabled to allow
    113 for the possibility of register window overflow and underflow
    114 traps.
    11598
    11699If the interrupt handler was installed as an RTEMS
    … …  
    123106
    124107@item insures that a register window is available for
    125 subsequent traps,
     108subsequent exceptions,
    126109
    127110@item if this is the outermost (i.e. non-nested) interrupt,
    … …  
    129112to the interrupt stack,
    130113
    131 @item enables traps,
     114@item enables exceptions,
    132115
    133116@item invokes the vectors to a user interrupt service routine (ISR).
    134117@end itemize
    135118
    136 Asynchronous interrupts are ignored while traps are
    137 disabled.  Synchronous traps which occur while traps are
     119Asynchronous interrupts are ignored while exceptions are
     120disabled.  Synchronous interrupts which occur while are
    138121disabled result in the CPU being forced into an error mode.
    139122
    … …  
    143126
    144127@ifinfo
    145 @node Interrupt Processing Traps and Register Windows, Interrupt Processing Interrupt Levels, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing
    146 @end ifinfo
    147 @section Traps and Register Windows
    148 
    149 One of the register windows must be reserved at all
    150 times for trap processing.  This is critical to the proper
    151 operation of the trap mechanism in the SPARC architecture.  It
    152 is the responsibility of the trap handler to insure that there
    153 is a register window available for a subsequent trap before
    154 re-enabling traps.  It is likely that any high level language
    155 routines invoked by the trap handler (such as a user-provided
    156 RTEMS interrupt handler) will allocate a new register window.
    157 The save operation could result in a window overflow trap.  This
    158 trap cannot be correctly processed unless (1) traps are enabled
    159 and (2) a register window is reserved for traps.  Thus, the
    160 RTEMS interrupt handler insures that a register window is
    161 available for subsequent traps before enabling traps and
    162 invoking the user's interrupt handler.
    163 
    164 @ifinfo
    165 @node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Traps and Register Windows, Interrupt Processing
     128@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing
    166129@end ifinfo
    167130@section Interrupt Levels
    168131
    169 Sixteen levels (0-15) of interrupt priorities are
    170 supported by the SPARC architecture with level fifteen (15)
     132TBD levels (0-TBD) of interrupt priorities are
     133supported by the PowerPC architecture with level TBD (TBD)
    171134being the highest priority.  Level zero (0) indicates that
    172135interrupts are fully enabled.  Interrupt requests for interrupts
    … …  
    174137level are ignored.
    175138
    176 Although RTEMS supports 256 interrupt levels, the
    177 SPARC only supports sixteen.  RTEMS interrupt levels 0 through
    178 15 directly correspond to SPARC processor interrupt levels.  All
    179 other RTEMS interrupt levels are undefined and their behavior is
     139TBD
     140All other RTEMS interrupt levels are undefined and their behavior is
    180141unpredictable.
    181142
    … …  
    187148During the execution of directive calls, critical
    188149sections of code may be executed.  When these sections are
    189 encountered, RTEMS disables interrupts to level seven (15)
     150encountered, RTEMS disables interrupts to level TBD (TBD)
    190151before the execution of this section and restores them to the
    191152previous level upon completion of the section.  RTEMS has been
    192153optimized to insure that interrupts are disabled for less than
    193 RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
    194 Mhz PowerPC 603e with zero wait states.
    195 These numbers will vary based the number of wait states and
    196 processor speed present on the target board.
     154RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a
     155RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz PowerPC 603e with zero
     156wait states.  These numbers will vary based the number of wait
     157states and processor speed present on the target board.
    197158[NOTE:  The maximum period with interrupts disabled is hand calculated.  This
    198159calculation was last performed for Release
    … …  
    201162[NOTE: It is thought that the length of time at which
    202163the processor interrupt level is elevated to fifteen by RTEMS is
    203 not anywhere near as long as the length of time ALL traps are
     164not anywhere near as long as the length of time ALL exceptions are
    204165disabled as part of the "flush all register windows" operation.]
    205166
    … …  
    216177@section Interrupt Stack
    217178
    218 The SPARC architecture does not provide for a
    219 dedicated interrupt stack.  Thus by default, trap handlers would
     179The PowerPC architecture does not provide for a
     180dedicated interrupt stack.  Thus by default, exception handlers would
    220181execute on the stack of the RTEMS task which they interrupted.
    221182This artificially inflates the stack requirements for each task
    … …  
    223184account for the worst case interrupt stack requirements in
    224185addition to it's own worst case usage.  RTEMS addresses this
    225 problem on the SPARC by providing a dedicated interrupt stack
     186problem on the PowerPC by providing a dedicated interrupt stack
    226187managed by software.
    227188
    … …  
    233194the interrupt stack before invoking the installed handler.
    234195
     196
     197
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