Changeset 023f1dd9 in rtems


Ignore:
Timestamp:
Nov 30, 2009, 5:27:08 AM (9 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, master
Children:
6452809
Parents:
359e537
Message:

Whitespace removal.

Location:
c/src/lib/libcpu/m68k
Files:
16 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/m68k/mcf5206/include/mcf5206e.h

    r359e537 r023f1dd9  
    583583                                             event */
    584584#define MCF5206E_TMR_OM          (0x0020) /* Output Mode - Toggle output */
    585 #define MCF5206E_TMR_ORI         (0x0010) /* Output Reference Interrupt 
     585#define MCF5206E_TMR_ORI         (0x0010) /* Output Reference Interrupt
    586586                                             Enable */
    587587#define MCF5206E_TMR_FRR         (0x0008) /* Free Run/Restart */
  • c/src/lib/libcpu/m68k/mcf5206/include/mcfuart.h

    r359e537 r023f1dd9  
    2828#endif
    2929
    30 /* 
     30/*
    3131 * The following structure is a descriptor of single UART channel.
    3232 * It contains the initialization information about channel and
     
    3838                                                0 if polled I/O */
    3939   void               *tty;              /* termios channel descriptor */
    40    
     40
    4141   volatile const uint8_t  *tx_buf;      /* Transmit buffer from termios */
    4242   volatile uint32_t        tx_buf_len;  /* Transmit buffer length */
    4343   volatile uint32_t        tx_ptr;      /* Index of next char to transmit*/
    4444   rtems_isr_entry          old_handler; /* Saved interrupt handler */
    45    
     45
    4646   tcflag_t                 c_iflag;    /* termios input mode flags */
    4747   bool                     parerr_mark_flag; /* Parity error processing
  • c/src/lib/libcpu/m68k/mcf5206/timer/timerisr.S

    r359e537 r023f1dd9  
    2828 *
    2929 *  http://www.rtems.com/license/LICENSE.
    30  * 
     30 *
    3131 *  $Id$
    3232 */
  • c/src/lib/libcpu/m68k/mcf5223x/cache/cachepd.c

    r359e537 r023f1dd9  
    66 *  found in the file LICENSE in this distribution or at
    77 *  http://www.rtems.com/license/LICENSE.
    8  * 
     8 *
    99 *  $Id$
    1010 */
  • c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c

    r359e537 r023f1dd9  
    77 *
    88 *  http://www.rtems.com/license/LICENSE.
    9  * 
     9 *
    1010 *  $Id$
    1111 */
     
    1313#include <rtems.h>
    1414#include <mcf5235/mcf5235.h>
    15  
     15
    1616/*
    1717 *  Default value for the cacr is set by the BSP
  • c/src/lib/libcpu/m68k/mcf5235/include/mcf5235.h

    r359e537 r023f1dd9  
    159159 * Functions provided by mcf5xxx.s
    160160 */
    161  
     161
    162162int     asm_set_ipl (uint32);
    163163void    mcf5xxx_wr_cacr (uint32);
     
    863863#define MCF5235_CAN_MBUF2_DATAL(x)          (*(vuint32  *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
    864864#define MCF5235_CAN_MBUF2_DATAH(x)          (*(vuint32  *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
    865                                                                                                                                                                  
    866                                                                                                                                                                  
    867 /* Bit definitions and macros for MCF5235_CAN_CANMCR */                                                           
    868 #define MCF5235_CAN_CANMCR_MAXMB(x)            (((x)&0x0000000F)<<0)                             
    869 #define MCF5235_CAN_CANMCR_SUPV                (0x00800000)                                                       
    870 #define MCF5235_CAN_CANMCR_FRZACK              (0x01000000)                                                       
    871 #define MCF5235_CAN_CANMCR_SOFTRST             (0x02000000)                                                       
    872 #define MCF5235_CAN_CANMCR_HALT                (0x10000000)                                                       
    873 #define MCF5235_CAN_CANMCR_FRZ                 (0x40000000)                                                       
    874 #define MCF5235_CAN_CANMCR_MDIS                (0x80000000)                                                       
     865
     866
     867/* Bit definitions and macros for MCF5235_CAN_CANMCR */
     868#define MCF5235_CAN_CANMCR_MAXMB(x)            (((x)&0x0000000F)<<0)
     869#define MCF5235_CAN_CANMCR_SUPV                (0x00800000)
     870#define MCF5235_CAN_CANMCR_FRZACK              (0x01000000)
     871#define MCF5235_CAN_CANMCR_SOFTRST             (0x02000000)
     872#define MCF5235_CAN_CANMCR_HALT                (0x10000000)
     873#define MCF5235_CAN_CANMCR_FRZ                 (0x40000000)
     874#define MCF5235_CAN_CANMCR_MDIS                (0x80000000)
    875875#define MCF5235_CAN_CANCTRL_PROPSEG(x)         (((x)&0x00000007)<<0)
    876876#define MCF5235_CAN_CANCTRL_LOM                (0x00000008)
     
    17381738/************************************************************
    17391739*
    1740 *       Clock 
     1740*       Clock
    17411741*************************************************************/
    17421742/* Register read/write macros */
  • c/src/lib/libcpu/m68k/mcf5272/clock/ckinit.c

    r359e537 r023f1dd9  
    22 *  Clock Driver for MCF5272 CPU
    33 *
    4  *  This driver initailizes timer1 on the MCF5272 as the 
    5  *  main system clock 
     4 *  This driver initailizes timer1 on the MCF5272 as the
     5 *  main system clock
    66 *
    77 *  Copyright 2004 Cogent Computer Systems
     
    4141 * These are set by clock driver during its init
    4242 */
    43  
     43
    4444rtems_device_major_number rtems_clock_major = ~0;
    4545rtems_device_minor_number rtems_clock_minor;
     
    5353 * PARAMETERS:
    5454 *     vector - timer interrupt vector number
    55  
     55
    5656 * RETURNS:
    5757 *     none
     
    9292        icr |= (MCF5272_ICR1_TMR1_IPL(0) | MCF5272_ICR1_TMR1_PI);
    9393        g_intctrl_regs->icr1 = icr;
    94        
     94
    9595        /* reset timer1 */
    9696        g_timer_regs->tmr1 = MCF5272_TMR_CLK_STOP;
    97        
     97
    9898        /* clear pending */
    9999        g_timer_regs->ter1 = MCF5272_TER_REF | MCF5272_TER_CAP;
     
    118118  Clock_driver_ticks = 0;
    119119  if (rtems_configuration_get_ticks_per_timeslice()) {
    120      
     120
    121121      /* Register the interrupt handler */
    122122      set_vector(clock_isr, BSP_INTVEC_TMR1, 1);
    123      
     123
    124124      /* Reset timer 1 */
    125125      g_timer_regs->tmr1 = MCF5272_TMR_RST;
     
    128128      g_timer_regs->tcn1 = 0;  /* reset counter */
    129129      g_timer_regs->ter1 = MCF5272_TER_REF | MCF5272_TER_CAP;
    130      
     130
    131131      /* Set Timer 1 prescaler so that it counts in microseconds */
    132132      g_timer_regs->tmr1 = (
     
    138138           MCF5272_TMR_RST));
    139139
    140       /* Set the timer timeout value from the BSP config */     
     140      /* Set the timer timeout value from the BSP config */
    141141      g_timer_regs->trr1 = rtems_configuration_get_microseconds_per_tick() - 1;
    142142
    143143      /* Feed system frequency to the timer */
    144144      g_timer_regs->tmr1 |= MCF5272_TMR_CLK_MSTR;
    145          
     145
    146146      /* Configure timer1 interrupts */
    147147      icr = g_intctrl_regs->icr1;
     
    175175{
    176176    Install_clock (Clock_isr);
    177  
     177
    178178    /* Make major/minor avail to others such as shared memory driver */
    179179    rtems_clock_major = major;
    180180    rtems_clock_minor = minor;
    181  
     181
    182182    return RTEMS_SUCCESSFUL;
    183183}
  • c/src/lib/libcpu/m68k/mcf5272/include/mcf5272.h

    r359e537 r023f1dd9  
    282282    volatile uint16_t pbdat;
    283283
    284     volatile uint16_t pcddr; 
     284    volatile uint16_t pcddr;
    285285    volatile uint16_t _res4;
    286286
     
    322322typedef struct {
    323323    volatile uint32_t dcmr;
    324    
     324
    325325    volatile uint16_t _res0;
    326326    volatile uint16_t dcir;
     
    587587    volatile uint16_t _res3;
    588588    volatile uint16_t rfmmr;
    589     volatile uint8_t  _res4[3]; 
     589    volatile uint8_t  _res4[3];
    590590    volatile uint8_t  far;
    591591    volatile uint32_t asr;
    592592    volatile uint32_t drr1;
    593593    volatile uint32_t drr2;
    594     volatile uint16_t _res5; 
     594    volatile uint16_t _res5;
    595595    volatile uint16_t specr;
    596596    volatile uint16_t _res6;
  • c/src/lib/libcpu/m68k/mcf5272/timer/timer.c

    r359e537 r023f1dd9  
    1919 *
    2020 *  http://www.rtems.com/license/LICENSE.
    21  * 
     21 *
    2222 *  timer.c,v 1.1 2001/10/26 19:32:40 joel Exp
    2323 */
     
    2727#include <mcf5272/mcf5272.h>
    2828
    29 #define TRR2_VAL 65530 
     29#define TRR2_VAL 65530
    3030
    3131uint32_t Timer_interrupts;
     
    5252    /* Catch timer2 interrupts */
    5353    set_vector(timerisr, BSP_INTVEC_TMR2, 0);
    54    
     54
    5555    /* Reset Timer */
    5656    g_timer_regs->tmr2 = MCF5272_TMR_RST;
     
    117117     */
    118118    clicks = g_timer_regs->tcn2;
    119  
     119
    120120    /* Stop Timer... */
    121121    g_timer_regs->tmr2 = MCF5272_TMR_CLK_STOP | MCF5272_TMR_RST;
    122122
    123123    /*
    124      *  Total is calculated by taking into account the number of timer 
     124     *  Total is calculated by taking into account the number of timer
    125125     *  overflow interrupts since the timer was initialized and clicks
    126126     *  since the last interrupts.
  • c/src/lib/libcpu/m68k/mcf5272/timer/timerisr.S

    r359e537 r023f1dd9  
    2828 *
    2929 *  http://www.rtems.com/license/LICENSE.
    30  * 
     30 *
    3131 *  timerisr.S,v 1.1 2001/10/26 19:32:40 joel Exp
    3232 */
  • c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c

    r359e537 r023f1dd9  
    4848  asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
    4949  adr += 1;
    50   asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); 
     50  asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
    5151}
    5252
     
    5454{
    5555  register unsigned long set, adr;
    56  
     56
    5757  for(set = 0; set < 256; ++set) {
    5858    adr = (set << 4);
     
    6363    asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
    6464    adr += 1;
    65     asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); 
     65    asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
    6666  }
    6767}
     
    137137{
    138138  _CPU_cache_invalidate_1_instruction_line(addr);
    139 } 
     139}
  • c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_dma.h

    r359e537 r023f1dd9  
    295295);
    296296
    297 /* 
    298  * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA 
    299  * registers, relocating and creating the appropriate task structures, and 
     297/*
     298 * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
     299 * registers, relocating and creating the appropriate task structures, and
    300300 * setting up some global settings
    301301 */
    302302int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
    303303
    304 /* 
     304/*
    305305 * MCD_dmaStatus() returns the status of the DMA on the requested channel.
    306306 */
    307307int MCD_dmaStatus (int channel);
    308308
    309 /* 
     309/*
    310310 * MCD_XferProgrQuery() returns progress of DMA on requested channel
    311311 */
    312312int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
    313313
    314 /* 
     314/*
    315315 * MCD_killDma() halts the DMA on the requested channel, without any
    316316 * intention of resuming the DMA.
     
    318318int MCD_killDma (int channel);
    319319
    320 /* 
     320/*
    321321 * MCD_continDma() continues a DMA which as stopped due to encountering an
    322322 * unready buffer descriptor.
     
    324324int MCD_continDma (int channel);
    325325
    326 /* 
     326/*
    327327 * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
    328  * running on that channel). 
     328 * running on that channel).
    329329 */
    330330int MCD_pauseDma (int channel);
    331331
    332 /* 
     332/*
    333333 * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
    334334 * running on that channel).
     
    336336int MCD_resumeDma (int channel);
    337337
    338 /* 
     338/*
    339339 * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
    340340 */
    341341int MCD_csumQuery (int channel, u32 *csum);
    342342
    343 /* 
     343/*
    344344 * MCD_getCodeSize provides the packed size required by the microcoded task
    345345 * and structures.
  • c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_dmaApi.c

    r359e537 r023f1dd9  
    247247        }
    248248#ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
    249                          where they are since DMA might write to them */       
     249                         where they are since DMA might write to them */
    250250        MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
    251 #else /* DMA does not touch them so they can be wherever and we don't need to 
     251#else /* DMA does not touch them so they can be wherever and we don't need to
    252252         waste SRAM on them */
    253253        MCD_relocBuffDesc = MCD_singleBufDescs;
     
    380380    if((channel < 0) || (channel >= NCHANNELS))
    381381        return(MCD_CHANNEL_INVALID);
    382        
    383     /* tbd - need to determine the proper response to a bad funcDesc when not 
     382
     383    /* tbd - need to determine the proper response to a bad funcDesc when not
    384384       including EU functions, for now, assign a benign funcDesc, but maybe
    385385       should return an error */
     
    387387    funcDesc = MCD_FUNC_NOEU1;
    388388#endif
    389        
     389
    390390#ifdef MCD_DEBUG
    391391printf("startDma:Setting up params\n");
     
    563563 *  MCD_XferProgrQuery() upon completing or after aborting a DMA, or
    564564 *  while the DMA is in progress, this function returns the first
    565  *  DMA-destination address not (or not yet) used in the DMA. When 
     565 *  DMA-destination address not (or not yet) used in the DMA. When
    566566 *  encountering a non-ready buffer descriptor, the information for
    567567 *  the last completed descriptor is returned.
     
    809809 * bits 1 and 2, respectively, have any effect.
    810810 *
    811  * NOTE: It's extremely important to not pause more than one DMA channel 
     811 * NOTE: It's extremely important to not pause more than one DMA channel
    812812 *  at a time.
    813813 ********************************************************************/
  • c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_tasks.c

    r359e537 r023f1dd9  
    19831983    0x00000000,
    19841984    0x00000000,
    1985 #endif   
     1985#endif
    19861986    (u32)MCD_ENetRcv_TDT,
    19871987    (u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009c],
  • c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_tasksInit.c

    r359e537 r023f1dd9  
    1919 * Task 0
    2020 */
    21  
     21
    2222void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
    2323{
     
    5656 * Task 1
    5757 */
    58  
     58
    5959void  MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
    6060{
     
    8686 * Task 2
    8787 */
    88  
     88
    8989void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
    9090{
     
    126126 * Task 3
    127127 */
    128  
     128
    129129void  MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
    130130{
     
    160160 * Task 4
    161161 */
    162  
     162
    163163void  MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
    164164{
     
    190190 * Task 5
    191191 */
    192  
     192
    193193void  MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
    194194{
  • c/src/lib/libcpu/m68k/mcf548x/mcdma/mcdma_glue.c

    r359e537 r023f1dd9  
    217217      rtems_panic ("Can't attach MFC548x MCDma interrupt handler\n");
    218218    }
    219     MCF548X_INTC_ICRn(MCDMA_IRQ_VECTOR - 64) =   
     219    MCF548X_INTC_ICRn(MCDMA_IRQ_VECTOR - 64) =
    220220      MCF548X_INTC_ICRn_IL(MCDMA_IRQ_LEVEL) |
    221221      MCF548X_INTC_ICRn_IP(MCDMA_IRQ_PRIORITY);
    222    
     222
    223223    MCF548X_INTC_IMRH &= ~(1 << (MCDMA_IRQ_VECTOR % 32));
    224224  }
Note: See TracChangeset for help on using the changeset viewer.