Changeset 023f1dd9 in rtems
- Timestamp:
- 11/30/09 05:27:08 (14 years ago)
- Branches:
- 4.10, 4.11, 5, master
- Children:
- 6452809
- Parents:
- 359e537
- Location:
- c/src/lib/libcpu/m68k
- Files:
-
- 16 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/m68k/mcf5206/include/mcf5206e.h
r359e537 r023f1dd9 583 583 event */ 584 584 #define MCF5206E_TMR_OM (0x0020) /* Output Mode - Toggle output */ 585 #define MCF5206E_TMR_ORI (0x0010) /* Output Reference Interrupt 585 #define MCF5206E_TMR_ORI (0x0010) /* Output Reference Interrupt 586 586 Enable */ 587 587 #define MCF5206E_TMR_FRR (0x0008) /* Free Run/Restart */ -
c/src/lib/libcpu/m68k/mcf5206/include/mcfuart.h
r359e537 r023f1dd9 28 28 #endif 29 29 30 /* 30 /* 31 31 * The following structure is a descriptor of single UART channel. 32 32 * It contains the initialization information about channel and … … 38 38 0 if polled I/O */ 39 39 void *tty; /* termios channel descriptor */ 40 40 41 41 volatile const uint8_t *tx_buf; /* Transmit buffer from termios */ 42 42 volatile uint32_t tx_buf_len; /* Transmit buffer length */ 43 43 volatile uint32_t tx_ptr; /* Index of next char to transmit*/ 44 44 rtems_isr_entry old_handler; /* Saved interrupt handler */ 45 45 46 46 tcflag_t c_iflag; /* termios input mode flags */ 47 47 bool parerr_mark_flag; /* Parity error processing -
c/src/lib/libcpu/m68k/mcf5206/timer/timerisr.S
r359e537 r023f1dd9 28 28 * 29 29 * http://www.rtems.com/license/LICENSE. 30 * 30 * 31 31 * $Id$ 32 32 */ -
c/src/lib/libcpu/m68k/mcf5223x/cache/cachepd.c
r359e537 r023f1dd9 6 6 * found in the file LICENSE in this distribution or at 7 7 * http://www.rtems.com/license/LICENSE. 8 * 8 * 9 9 * $Id$ 10 10 */ -
c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c
r359e537 r023f1dd9 7 7 * 8 8 * http://www.rtems.com/license/LICENSE. 9 * 9 * 10 10 * $Id$ 11 11 */ … … 13 13 #include <rtems.h> 14 14 #include <mcf5235/mcf5235.h> 15 15 16 16 /* 17 17 * Default value for the cacr is set by the BSP -
c/src/lib/libcpu/m68k/mcf5235/include/mcf5235.h
r359e537 r023f1dd9 159 159 * Functions provided by mcf5xxx.s 160 160 */ 161 161 162 162 int asm_set_ipl (uint32); 163 163 void mcf5xxx_wr_cacr (uint32); … … 863 863 #define MCF5235_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) 864 864 #define MCF5235_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) 865 866 867 /* Bit definitions and macros for MCF5235_CAN_CANMCR */ 868 #define MCF5235_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) 869 #define MCF5235_CAN_CANMCR_SUPV (0x00800000) 870 #define MCF5235_CAN_CANMCR_FRZACK (0x01000000) 871 #define MCF5235_CAN_CANMCR_SOFTRST (0x02000000) 872 #define MCF5235_CAN_CANMCR_HALT (0x10000000) 873 #define MCF5235_CAN_CANMCR_FRZ (0x40000000) 874 #define MCF5235_CAN_CANMCR_MDIS (0x80000000) 865 866 867 /* Bit definitions and macros for MCF5235_CAN_CANMCR */ 868 #define MCF5235_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) 869 #define MCF5235_CAN_CANMCR_SUPV (0x00800000) 870 #define MCF5235_CAN_CANMCR_FRZACK (0x01000000) 871 #define MCF5235_CAN_CANMCR_SOFTRST (0x02000000) 872 #define MCF5235_CAN_CANMCR_HALT (0x10000000) 873 #define MCF5235_CAN_CANMCR_FRZ (0x40000000) 874 #define MCF5235_CAN_CANMCR_MDIS (0x80000000) 875 875 #define MCF5235_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) 876 876 #define MCF5235_CAN_CANCTRL_LOM (0x00000008) … … 1738 1738 /************************************************************ 1739 1739 * 1740 * Clock 1740 * Clock 1741 1741 *************************************************************/ 1742 1742 /* Register read/write macros */ -
c/src/lib/libcpu/m68k/mcf5272/clock/ckinit.c
r359e537 r023f1dd9 2 2 * Clock Driver for MCF5272 CPU 3 3 * 4 * This driver initailizes timer1 on the MCF5272 as the 5 * main system clock 4 * This driver initailizes timer1 on the MCF5272 as the 5 * main system clock 6 6 * 7 7 * Copyright 2004 Cogent Computer Systems … … 41 41 * These are set by clock driver during its init 42 42 */ 43 43 44 44 rtems_device_major_number rtems_clock_major = ~0; 45 45 rtems_device_minor_number rtems_clock_minor; … … 53 53 * PARAMETERS: 54 54 * vector - timer interrupt vector number 55 55 56 56 * RETURNS: 57 57 * none … … 92 92 icr |= (MCF5272_ICR1_TMR1_IPL(0) | MCF5272_ICR1_TMR1_PI); 93 93 g_intctrl_regs->icr1 = icr; 94 94 95 95 /* reset timer1 */ 96 96 g_timer_regs->tmr1 = MCF5272_TMR_CLK_STOP; 97 97 98 98 /* clear pending */ 99 99 g_timer_regs->ter1 = MCF5272_TER_REF | MCF5272_TER_CAP; … … 118 118 Clock_driver_ticks = 0; 119 119 if (rtems_configuration_get_ticks_per_timeslice()) { 120 120 121 121 /* Register the interrupt handler */ 122 122 set_vector(clock_isr, BSP_INTVEC_TMR1, 1); 123 123 124 124 /* Reset timer 1 */ 125 125 g_timer_regs->tmr1 = MCF5272_TMR_RST; … … 128 128 g_timer_regs->tcn1 = 0; /* reset counter */ 129 129 g_timer_regs->ter1 = MCF5272_TER_REF | MCF5272_TER_CAP; 130 130 131 131 /* Set Timer 1 prescaler so that it counts in microseconds */ 132 132 g_timer_regs->tmr1 = ( … … 138 138 MCF5272_TMR_RST)); 139 139 140 /* Set the timer timeout value from the BSP config */ 140 /* Set the timer timeout value from the BSP config */ 141 141 g_timer_regs->trr1 = rtems_configuration_get_microseconds_per_tick() - 1; 142 142 143 143 /* Feed system frequency to the timer */ 144 144 g_timer_regs->tmr1 |= MCF5272_TMR_CLK_MSTR; 145 145 146 146 /* Configure timer1 interrupts */ 147 147 icr = g_intctrl_regs->icr1; … … 175 175 { 176 176 Install_clock (Clock_isr); 177 177 178 178 /* Make major/minor avail to others such as shared memory driver */ 179 179 rtems_clock_major = major; 180 180 rtems_clock_minor = minor; 181 181 182 182 return RTEMS_SUCCESSFUL; 183 183 } -
c/src/lib/libcpu/m68k/mcf5272/include/mcf5272.h
r359e537 r023f1dd9 282 282 volatile uint16_t pbdat; 283 283 284 volatile uint16_t pcddr; 284 volatile uint16_t pcddr; 285 285 volatile uint16_t _res4; 286 286 … … 322 322 typedef struct { 323 323 volatile uint32_t dcmr; 324 324 325 325 volatile uint16_t _res0; 326 326 volatile uint16_t dcir; … … 587 587 volatile uint16_t _res3; 588 588 volatile uint16_t rfmmr; 589 volatile uint8_t _res4[3]; 589 volatile uint8_t _res4[3]; 590 590 volatile uint8_t far; 591 591 volatile uint32_t asr; 592 592 volatile uint32_t drr1; 593 593 volatile uint32_t drr2; 594 volatile uint16_t _res5; 594 volatile uint16_t _res5; 595 595 volatile uint16_t specr; 596 596 volatile uint16_t _res6; -
c/src/lib/libcpu/m68k/mcf5272/timer/timer.c
r359e537 r023f1dd9 19 19 * 20 20 * http://www.rtems.com/license/LICENSE. 21 * 21 * 22 22 * timer.c,v 1.1 2001/10/26 19:32:40 joel Exp 23 23 */ … … 27 27 #include <mcf5272/mcf5272.h> 28 28 29 #define TRR2_VAL 65530 29 #define TRR2_VAL 65530 30 30 31 31 uint32_t Timer_interrupts; … … 52 52 /* Catch timer2 interrupts */ 53 53 set_vector(timerisr, BSP_INTVEC_TMR2, 0); 54 54 55 55 /* Reset Timer */ 56 56 g_timer_regs->tmr2 = MCF5272_TMR_RST; … … 117 117 */ 118 118 clicks = g_timer_regs->tcn2; 119 119 120 120 /* Stop Timer... */ 121 121 g_timer_regs->tmr2 = MCF5272_TMR_CLK_STOP | MCF5272_TMR_RST; 122 122 123 123 /* 124 * Total is calculated by taking into account the number of timer 124 * Total is calculated by taking into account the number of timer 125 125 * overflow interrupts since the timer was initialized and clicks 126 126 * since the last interrupts. -
c/src/lib/libcpu/m68k/mcf5272/timer/timerisr.S
r359e537 r023f1dd9 28 28 * 29 29 * http://www.rtems.com/license/LICENSE. 30 * 30 * 31 31 * timerisr.S,v 1.1 2001/10/26 19:32:40 joel Exp 32 32 */ -
c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c
r359e537 r023f1dd9 48 48 asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); 49 49 adr += 1; 50 asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); 50 asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); 51 51 } 52 52 … … 54 54 { 55 55 register unsigned long set, adr; 56 56 57 57 for(set = 0; set < 256; ++set) { 58 58 adr = (set << 4); … … 63 63 asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); 64 64 adr += 1; 65 asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); 65 asm volatile ("cpushl %%bc,(%0)" :: "a" (adr)); 66 66 } 67 67 } … … 137 137 { 138 138 _CPU_cache_invalidate_1_instruction_line(addr); 139 } 139 } -
c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_dma.h
r359e537 r023f1dd9 295 295 ); 296 296 297 /* 298 * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA 299 * registers, relocating and creating the appropriate task structures, and 297 /* 298 * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA 299 * registers, relocating and creating the appropriate task structures, and 300 300 * setting up some global settings 301 301 */ 302 302 int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); 303 303 304 /* 304 /* 305 305 * MCD_dmaStatus() returns the status of the DMA on the requested channel. 306 306 */ 307 307 int MCD_dmaStatus (int channel); 308 308 309 /* 309 /* 310 310 * MCD_XferProgrQuery() returns progress of DMA on requested channel 311 311 */ 312 312 int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep); 313 313 314 /* 314 /* 315 315 * MCD_killDma() halts the DMA on the requested channel, without any 316 316 * intention of resuming the DMA. … … 318 318 int MCD_killDma (int channel); 319 319 320 /* 320 /* 321 321 * MCD_continDma() continues a DMA which as stopped due to encountering an 322 322 * unready buffer descriptor. … … 324 324 int MCD_continDma (int channel); 325 325 326 /* 326 /* 327 327 * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is 328 * running on that channel). 328 * running on that channel). 329 329 */ 330 330 int MCD_pauseDma (int channel); 331 331 332 /* 332 /* 333 333 * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is 334 334 * running on that channel). … … 336 336 int MCD_resumeDma (int channel); 337 337 338 /* 338 /* 339 339 * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA 340 340 */ 341 341 int MCD_csumQuery (int channel, u32 *csum); 342 342 343 /* 343 /* 344 344 * MCD_getCodeSize provides the packed size required by the microcoded task 345 345 * and structures. -
c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_dmaApi.c
r359e537 r023f1dd9 247 247 } 248 248 #ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls 249 where they are since DMA might write to them */ 249 where they are since DMA might write to them */ 250 250 MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4); 251 #else /* DMA does not touch them so they can be wherever and we don't need to 251 #else /* DMA does not touch them so they can be wherever and we don't need to 252 252 waste SRAM on them */ 253 253 MCD_relocBuffDesc = MCD_singleBufDescs; … … 380 380 if((channel < 0) || (channel >= NCHANNELS)) 381 381 return(MCD_CHANNEL_INVALID); 382 383 /* tbd - need to determine the proper response to a bad funcDesc when not 382 383 /* tbd - need to determine the proper response to a bad funcDesc when not 384 384 including EU functions, for now, assign a benign funcDesc, but maybe 385 385 should return an error */ … … 387 387 funcDesc = MCD_FUNC_NOEU1; 388 388 #endif 389 389 390 390 #ifdef MCD_DEBUG 391 391 printf("startDma:Setting up params\n"); … … 563 563 * MCD_XferProgrQuery() upon completing or after aborting a DMA, or 564 564 * while the DMA is in progress, this function returns the first 565 * DMA-destination address not (or not yet) used in the DMA. When 565 * DMA-destination address not (or not yet) used in the DMA. When 566 566 * encountering a non-ready buffer descriptor, the information for 567 567 * the last completed descriptor is returned. … … 809 809 * bits 1 and 2, respectively, have any effect. 810 810 * 811 * NOTE: It's extremely important to not pause more than one DMA channel 811 * NOTE: It's extremely important to not pause more than one DMA channel 812 812 * at a time. 813 813 ********************************************************************/ -
c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_tasks.c
r359e537 r023f1dd9 1983 1983 0x00000000, 1984 1984 0x00000000, 1985 #endif 1985 #endif 1986 1986 (u32)MCD_ENetRcv_TDT, 1987 1987 (u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009c], -
c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_tasksInit.c
r359e537 r023f1dd9 19 19 * Task 0 20 20 */ 21 21 22 22 void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel) 23 23 { … … 56 56 * Task 1 57 57 */ 58 58 59 59 void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) 60 60 { … … 86 86 * Task 2 87 87 */ 88 88 89 89 void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel) 90 90 { … … 126 126 * Task 3 127 127 */ 128 128 129 129 void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) 130 130 { … … 160 160 * Task 4 161 161 */ 162 162 163 163 void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel) 164 164 { … … 190 190 * Task 5 191 191 */ 192 192 193 193 void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel) 194 194 { -
c/src/lib/libcpu/m68k/mcf548x/mcdma/mcdma_glue.c
r359e537 r023f1dd9 217 217 rtems_panic ("Can't attach MFC548x MCDma interrupt handler\n"); 218 218 } 219 MCF548X_INTC_ICRn(MCDMA_IRQ_VECTOR - 64) = 219 MCF548X_INTC_ICRn(MCDMA_IRQ_VECTOR - 64) = 220 220 MCF548X_INTC_ICRn_IL(MCDMA_IRQ_LEVEL) | 221 221 MCF548X_INTC_ICRn_IP(MCDMA_IRQ_PRIORITY); 222 222 223 223 MCF548X_INTC_IMRH &= ~(1 << (MCDMA_IRQ_VECTOR % 32)); 224 224 }
Note: See TracChangeset
for help on using the changeset viewer.