Changeset 023bd1d in rtems
- Timestamp:
- 09/04/18 13:34:42 (6 years ago)
- Branches:
- 5, master
- Children:
- 156b77a
- Parents:
- 35eab84
- git-author:
- Joel Sherrill <joel@…> (09/04/18 13:34:42)
- git-committer:
- Joel Sherrill <joel@…> (10/18/18 17:05:40)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
bsps/or1k/shared/cache/cache.c
r35eab84 r023bd1d 98 98 /* Implement RTEMS cache manager functions */ 99 99 100 static void _CPU_cache_flush_1_data_line(const void *d_addr)101 {102 ISR_Level level;103 104 _ISR_Local_disable (level);105 106 _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);107 108 //__asm__ volatile("l.csync");109 110 _ISR_Local_enable(level);111 }112 113 static void _CPU_cache_invalidate_1_data_line(const void *d_addr)114 {115 ISR_Level level;116 117 _ISR_Local_disable (level);118 119 _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);120 121 _ISR_Local_enable(level);122 }123 124 100 static void _CPU_cache_freeze_data(void) 125 101 { … … 130 106 { 131 107 /* Do nothing */ 132 }133 134 static void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)135 {136 ISR_Level level;137 138 _ISR_Local_disable (level);139 140 _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);141 142 _ISR_Local_enable(level);143 108 } 144 109
Note: See TracChangeset
for help on using the changeset viewer.