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rom_reset.S @ ddf6706

Last change on this file since ddf6706 was b987a75, checked in by Jarielle Catbagan <jcatbagan93@…>, on 06/19/15 at 21:32:43
Removed execution mode file attribute from all ASCII text files
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File size: 9.9 KB

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1	.file "rom_reset.S"
2
3	/*
4	* General notice:
5	* This code is part of a boot-monitor package developed as a generic base
6	* platform for embedded system designs. As such, it is likely to be
7	* distributed to various projects beyond the control of the original
8	* author. Please notify the author of any enhancements made or bugs found
9	* so that all may benefit from the changes. In addition, notification back
10	* to the author will allow the new user to pick up changes that may have
11	* been made by other users after this version of the code was distributed.
12	*
13	* Author: Ed Sutter
14	* email: esutter@lucent.com
15	* phone: 908-582-2351
16	*
17	*
18	* Modified for the CSB740 - OMAP3530 Single Board
19	*
20	* rom_reset.s:
21	*/
22
23	#include "warmstart.h"
24	#include "omap3530.h"
25	#include "config.h"
26
27	/*
28	* Have a separate stack for each processor mode.
29	*/
30
31	/* define sizes for each mode's stack */
32	.equ FiqStackSz, 4096
33	.equ IrqStackSz, 4096
34	.equ AbtStackSz, 4096
35	.equ UndStackSz, 4096
36	.equ SysStackSz, 4096
37
38	/* declare the stacks */
39	.extern MonStack
40	.global FiqStack
41	.global IrqStack
42	.global AbtStack
43	.global UndStack
44	.global SysStack
45	.global raise
46	.global cache_init
47
48	/* allocate the stacks */
49	.comm FiqStack, FiqStackSz /* for the FIQ mode */
50	.comm IrqStack, IrqStackSz /* for the IRQ mode */
51	.comm AbtStack, AbtStackSz /* for the Abort mode */
52	.comm UndStack, UndStackSz /* for the Undef mode */
53	.comm SysStack, SysStackSz /* for the System mode */
54	/* User mode has the same stack as system mode. */
55
56	/*********************************************************************/
57
58	.extern start
59
60	.global reset
61	.global coldstart
62	.global lukewarmstart
63	.global warmstart
64
65	.text
66
67	/*
68	* Exception table at address 0
69	*/
70	reset:
71	b coldstart
72	b undefined_instruction
73	b software_interrupt
74	b abort_prefetch
75	b abort_data
76	b not_assigned
77	b interrupt_request
78	b fast_interrupt_request
79
80	#include "etheraddr.S"
81	#include "moncomptr.S"
82	#include "alttfsdevtbl.S"
83
84	coldstart:
85	ldr pc, =coldstart_1 // jump to actual ROM location
86	nop
87
88	coldstart_1:
89	/* Make sure interrupts are off, and we're in supervisor mode...
90	*/
91	mrs r0,cpsr // Retreive current program status register
92	bic r0,r0,#0x1f // Clear all mode bits.
93	orr r0,r0,#0xd3 // Set mode to supervisor, IRQ FIQ disabled.
94	msr cpsr,r0
95
96	// bl cache_init
97
98	//----------------------------------------------------------
99	// Start of Cogent Setup for CSB740 OMAP3530
100	//----------------------------------------------------------
101
102	init_pbias:
103	ldr r2, =0x00000000 // set bias for sdio1
104	ldr r1, =0x48002520
105	str r2, [r1]
106
107	bl delay_200
108
109	ldr r2, =0x00000606 // set bias for sdio1
110	ldr r1, =0x48002520
111	str r2, [r1]
112
113	bl delay_200
114	init_clocks:
115	ldr r2, =0x00000037 // Enable DPLL1 in lock mode
116	ldr r1, =0x48004904
117	str r2, [r1]
118
119	bl delay_200
120
121	ldr r2, =0x000A7115 // Set DPLL1 (MPU) M = 625, (N +1)= 21 + 1, MPU_CLK = ~545MHz
122	ldr r1, =0x48004940
123	str r2, [r1]
124
125	bl delay_200
126
127	ldr r2, =0x099F1700 // Set DPLL3 (CORE) M = 415, (N +1)= 23 + 1, CORE_CLK = ~332MHz
128	ldr r1, =0x48004D40
129	str r2, [r1]
130
131	bl delay_200
132
133	//ldr r2, =0x00000080 // Enable SYS_CLKOUT2 for debug purposes
134	//ldr r1, =0x48004D70
135	//str r2, [r1]
136
137	//bl delay_200
138
139	ldr r2, =0x43fffe00 // Turn on all available module clocks
140	ldr r1, =0x48004a00
141	str r2, [r1]
142
143	bl delay_200
144
145	ldr r2, =0x7ffffedb // Turn on all available peripheral clocks
146	ldr r1, =0x48004a10
147	str r2, [r1]
148
149	bl delay_200
150
151	ldr r2, =0x00006000 // enable auto clock for UART1 and UART2
152	ldr r1, =0x48004a30
153	str r2, [r1]
154
155	bl delay_200
156
157	ldr r2, =0x00000028 // enable WDT2 and GPIO 1 functional clock
158	ldr r1, =0x48004c00
159	str r2, [r1]
160
161	bl delay_200
162
163	ldr r2, =0x0000002c // enable WDT2, GPIO 1 interface and 32Ksync (for Linux) clock
164	ldr r1, =0x48004c10
165	str r2, [r1]
166
167	bl delay_200
168
169	ldr r2, =0x0003E000 // enable GPIO 2-6 functional clocks
170	ldr r1, =0x48005000
171	str r2, [r1]
172
173	bl delay_200
174
175	ldr r2, =0x0003E000 // enable GPIO 2-6 interface clocks
176	ldr r1, =0x48005010
177	str r2, [r1]
178
179	bl delay_200
180
181	ldr r2, =0x00000003 // enable DSS1_ALWON_FCLK
182	ldr r1, =0x48004e00
183	str r2, [r1]
184
185	bl delay_200
186
187	ldr r2, =0x00000001 // enable DSS interface clock
188	ldr r1, =0x48004e10
189	str r2, [r1]
190
191	bl delay_200
192
193	ldr r2, =0x0000100A // Set CLKSEL_DSS1 to divide by 1
194	ldr r1, =0x48004e40
195	str r2, [r1]
196
197	bl delay_200
198
199	init_ddr:
200	ldr r2, =0x0000001A // reset DDR
201	ldr r1, =0x6D000010
202	str r2, [r1]
203
204	ldr r1, =0x6D000014 // SDRC_SYSSTATUS
205	wait_reset:
206	ldr r2, [r1]
207	tst r2, #1 // test RESETDONE
208	beq wait_reset
209
210	ldr r2, =0x00000018 // release DDR reset
211	ldr r1, =0x6D000010
212	str r2, [r1]
213
214	bl delay_200
215
216	ldr r2, =0x00000100 // 32-bit SDRAM on data lane [31:0] - CS0
217	ldr r1, =0x6D000044
218	str r2, [r1]
219
220	bl delay_200
221
222	ldr r2, =0x02584099 // SDRC_MCFG0 register
223	ldr r1, =0x6D000080
224	str r2, [r1]
225
226	bl delay_200
227
228	ldr r2, =0x00054601 // SDRC_RFR_CTRL0 register
229	ldr r1, =0x6D0000a4
230	str r2, [r1]
231
232	bl delay_200
233
234	ldr r2, =0xA29DB4C6 // SDRC_ACTIM_CTRLA0 register
235	ldr r1, =0x6D00009c
236	str r2, [r1]
237
238	bl delay_200
239
240	ldr r2, =0x00012214 // SDRC_ACTIM_CTRLB0 register
241	ldr r1, =0x6D0000A0
242	str r2, [r1]
243
244	bl delay_200
245
246	ldr r2, =0x00000081 // Disble Power Down of CKE due to 1 CKE on combo part
247	ldr r1, =0x6D000070
248	str r2, [r1]
249
250	bl delay_200
251
252	ldr r2, =0x00000000 // NOP command
253	ldr r1, =0x6D0000A8
254	str r2, [r1]
255
256	bl delay_200
257
258	ldr r2, =0x00000001 // Precharge command
259	ldr r1, =0x6D0000A8
260	str r2, [r1]
261
262	bl delay_200
263
264	ldr r2, =0x00000002 // Auto-refresh command
265	ldr r1, =0x6D0000A8
266	str r2, [r1]
267
268	bl delay_200
269
270	ldr r2, =0x00000002 // Auto-refresh command
271	ldr r1, =0x6D0000A8
272	str r2, [r1]
273
274	bl delay_200
275
276	ldr r2, =0x00000032 // SDRC MR0 register Burst length=4
277	ldr r1, =0x6D000084
278	str r2, [r1]
279
280	bl delay_200
281
282	ldr r2, =0x0000000A // SDRC DLLA control register
283	ldr r1, =0x6D000060
284	str r2, [r1]
285
286	bl delay_200
287
288	/********************************************************************/
289
290	midstart:
291	ldr r0, =INITIALIZE
292
293	/* fall-through to 'lukewarmstart' */
294
295	/********************************************************************/
296
297	lukewarmstart:
298	/* Save the argument to r11 */
299	mov r11, r0
300
301	/*
302	* * DO NOT TOUCH R11 *
303	*/
304
305	/*
306	* Set-up the stack-pointers for all operating modes
307	*/
308
309	/* FIQ mode */
310	mrs r0, cpsr /* move CPSR to r0 */
311	bic r0, r0, #0x1f /* clear all mode bits */
312	orr r0, r0, #0x11 /* set FIQ mode bits */
313	msr CPSR_c, r0 /* move back to CPSR */
314	ldr sp, =(FiqStack + FiqStackSz - 4) /* initialize the stack ptr */
315	/* IRQ mode */
316	mrs r0, cpsr /* move CPSR to r0 */
317	bic r0, r0, #0x1f /* clear all mode bits */
318	orr r0, r0, #0x12 /* set IRQ mode bits */
319	msr CPSR_c, r0 /* move back to CPSR */
320	ldr sp, =(IrqStack + IrqStackSz - 4) /* initialize the stack ptr */
321	/* Abort mode */
322	mrs r0, cpsr /* move CPSR to r0 */
323	bic r0, r0, #0x1f /* clear all mode bits */
324	orr r0, r0, #0x17 /* set Abort mode bits */
325	msr CPSR_c, r0 /* move back to CPSR */
326	ldr sp, =(AbtStack + AbtStackSz - 4) /* initialize the stack ptr */
327	/* Undef mode */
328	mrs r0, cpsr /* move CPSR to r0 */
329	bic r0, r0, #0x1f /* clear all mode bits */
330	orr r0, r0, #0x1b /* set Undef mode bits */
331	msr CPSR_c, r0 /* move back to CPSR */
332	ldr sp, =(UndStack + UndStackSz - 4) /* initialize the stack ptr */
333	/* System mode */
334	mrs r0, cpsr /* move CPSR to r0 */
335	bic r0, r0, #0x1f /* clear all mode bits */
336	orr r0, r0, #0x1f /* set System mode bits */
337	msr CPSR_c, r0 /* move back to CPSR */
338	ldr sp, =(SysStack + SysStackSz - 4) /* initialize the stack ptr */
339	/* 'warmstart' will take us back to SVC mode
340	stack for SVC mode will also be setup in warmstart */
341
342	mov r0, r11 /* get argument back from r11 */
343	b warmstart
344
345
346	/********************************************************************/
347
348	warmstart:
349	/* Save the argument to r11 */
350	mov r11, r0
351
352	/*
353	* * DO NOT TOUCH R11 *
354	*/
355
356
357	/* Change (back) to SVC mode */
358	mrs r0, cpsr /* move CPSR to r0 */
359	bic r0, r0, #0x1f /* clear all mode bits */
360	orr r0, r0, #0x13 /* set System mode bits */
361	msr CPSR_c, r0 /* move back to CPSR */
362	/* Reset the stack pointer for the SVC mode (our current mode) */
363	ldr sp, =(MonStack + MONSTACKSIZE - 4)
364
365	/*
366	* Restore argument which was saved to r11 and jump to
367	* the C function start().
368	*/
369
370	mov r0, r11
371	jump_to_c:
372	bl start
373
374	/* the C code should never return */
375	b reset
376
377	.align 4
378
379
380	/*********************************************************************
381	* simple delay loop
382	*/
383	delay_200:
384	ldr r3, =200 /* loop count */
385	delay_loop:
386	subs r3,r3,#1
387	bne delay_loop
388	nop
389
390	mov pc, lr
391
392	raise: mov pc, lr /* to make linker happy */
393
394	/*********************************************************************
395	* Cache initialization:
396	* Turn everything down and invalidate...
397	*/
398	cache_init:
399	/* Make sure caches are turned down...
400	*/
401	mrc p15, 0, r3, cr1, cr0, 0 // turn off I/D-cache
402	bic r3, r3, #4096 // I
403	bic r3, r3, #4 // D
404	mcr p15, 0, r3, cr1, cr0, 0
405
406	mov r0, #0
407	// mcr p15, 0, r0, cr7, cr7, 0 // arm_cache_invalidate
408	mcr p15, 0, r0, cr7, cr6, 0 // arm_dcache_invalidate
409	mcr p15, 0, r0, cr7, cr5, 0 // arm_icache_invalidate
410
411	mrc p15, 0, r0, cr1, cr0, 1 // l2cache_disable
412	bic r0, r0, #2
413	mcr p15, 0, r0, cr1, cr0, 1
414
415	mov r0, #1
416	mrc p15, 1, r0, cr0, cr0, 1 // emu_ext_boot_l2_inv
417	mov pc, lr
418

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