| 1 | //========================================================================== |
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| 2 | // |
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| 3 | // omap3530.h |
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| 4 | // |
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| 5 | // Author(s): Luis Torrico, Cogent Computer Systems, Inc. |
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| 6 | // Contributors: |
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| 7 | // Date: 05/02/2008 |
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| 8 | // Description: This file contains register base addresses and offsets |
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| 9 | // and access macros for the OMAP3530 on-chip peripherals |
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| 10 | // Peripherals not used by UMON have not been tested (and |
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| 11 | // may not be defined). Use these defines with caution!! |
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| 12 | // |
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| 13 | |
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| 14 | #include "bits.h" |
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| 15 | |
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| 16 | /* |
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| 17 | * 3530 specific Section |
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| 18 | */ |
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| 19 | |
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| 20 | /* Stuff on L3 Interconnect */ |
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| 21 | #define SMX_APE_BASE 0x68000000 |
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| 22 | |
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| 23 | /* L3 Firewall */ |
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| 24 | #define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) |
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| 25 | #define A_READPERM0 (SMX_APE_BASE + 0x05050) |
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| 26 | #define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) |
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| 27 | |
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| 28 | /* GPMC */ |
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| 29 | #define OMAP35XX_GPMC_BASE 0x6E000000 |
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| 30 | |
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| 31 | /* SMS */ |
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| 32 | #define OMAP35XX_SMS_BASE 0x6C000000 |
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| 33 | |
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| 34 | /* SDRC */ |
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| 35 | #define OMAP35XX_SDRC_BASE 0x6D000000 |
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| 36 | |
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| 37 | /* |
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| 38 | * L4 Peripherals - L4 Wakeup and L4 Core now |
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| 39 | */ |
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| 40 | #define OMAP35XX_CORE_L4_IO_BASE 0x48000000 |
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| 41 | |
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| 42 | #define OMAP35XX_WAKEUP_L4_IO_BASE 0x48300000 |
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| 43 | |
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| 44 | #define OMAP35XX_L4_PER 0x49000000 |
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| 45 | |
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| 46 | #define OMAP35XX_L4_IO_BASE OMAP35XX_CORE_L4_IO_BASE |
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| 47 | |
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| 48 | /* TAP information dont know for 3430*/ |
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| 49 | #define OMAP35XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ |
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| 50 | |
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| 51 | /* base address for indirect vectors (internal boot mode) */ |
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| 52 | #define SRAM_OFFSET0 0x40000000 |
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| 53 | #define SRAM_OFFSET1 0x00200000 |
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| 54 | #define SRAM_OFFSET2 0x0000F800 |
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| 55 | #define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) |
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| 56 | |
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| 57 | #define LOW_LEVEL_SRAM_STACK 0x4020FFFC |
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| 58 | |
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| 59 | /*-------------------------------------------------------------------------------------*/ |
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| 60 | /* UART */ |
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| 61 | /*-------------------------------------------------------------------------------------*/ |
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| 62 | #define OMAP35XX_UART1 (OMAP35XX_L4_IO_BASE+0x6A000) |
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| 63 | #define OMAP35XX_UART2 (OMAP35XX_L4_IO_BASE+0x6C000) |
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| 64 | #define OMAP35XX_UART3 (OMAP35XX_L4_PER+0x20000) |
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| 65 | #define UART1_REG(_x_) *(vulong *)(OMAP35XX_UART1 + _x_) |
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| 66 | #define UART2_REG(_x_) *(vulong *)(OMAP35XX_UART2 + _x_) |
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| 67 | #define UART3_REG(_x_) *(vulong *)(OMAP35XX_UART3 + _x_) |
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| 68 | |
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| 69 | /* UART Register offsets */ |
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| 70 | #define UART_RHR 0x00 // Receive Holding Register (read only) |
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| 71 | #define UART_THR 0x00 // Transmit Holding Register (write only) |
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| 72 | #define UART_DLL 0x00 // Baud divisor lower byte (read/write) |
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| 73 | #define UART_DLH 0x04 // Baud divisor higher byte (read/write) |
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| 74 | #define UART_IER 0x04 // Interrupt Enable Register (read/write) |
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| 75 | #define UART_IIR 0x08 // Interrupt Identification Register (read only) |
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| 76 | #define UART_FCR 0x08 // FIFO Control Register (write only) |
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| 77 | #define UART_EFR 0x08 // Enhanced Feature Register |
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| 78 | #define UART_LCR 0x0C // Line Control Register (read/write) |
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| 79 | #define UART_MCR 0x10 // Modem Control Register (read/write) |
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| 80 | #define UART_LSR 0x14 // Line Status Register (read only) |
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| 81 | #define UART_MSR 0x18 // Modem Status Register (read only) |
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| 82 | #define UART_TCR 0x18 // |
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| 83 | #define UART_TLR 0x1C // |
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| 84 | #define UART_SPR 0x1C // Scratch Pad Register (read/write) |
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| 85 | #define UART_MDR1 0x20 // Mode Definition Register 1 |
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| 86 | #define UART_MDR2 0x24 // Mode Definition Register 2 |
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| 87 | //#define UART_SFLSR 0x28 // Status FIFO Line Status Register (IrDA modes only) |
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| 88 | //#define UART_TXFLL 0x28 // Transmit Frame Length Register Low (IrDA modes only) |
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| 89 | //#define UART_RESUME 0x2C // Resume Register (IR-IrDA and IR-CIR modes only) |
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| 90 | //#define UART_TXFLH 0x2C // Transmit Frame Length Register High (IrDA modes only) |
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| 91 | //#define UART_RXFLL 0x30 // Receive Frame Length Register Low (IrDA modes only) |
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| 92 | //#define UART_SFREGL 0x30 // Status FIFO Register Low (IrDA modes only) |
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| 93 | //#define UART_RXFLH 0x34 // Receive Frame Length Register High (IrDA modes only) |
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| 94 | //#define UART_SFREGH 0x34 // Status FIFO Register High (IrDA modes only) |
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| 95 | //#define UART_BLR 0x38 // BOF Control Register (IrDA modes only) |
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| 96 | //#define UART_UASR 0x38 // UART Autobauding Status Register (UART autobauding mode only) |
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| 97 | //#define UART_ACREG 0x3C // Auxiliary Control Register (IrDA-CIR modes only) |
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| 98 | #define UART_SCR 0x40 // Supplementary Control Register |
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| 99 | #define UART_SSR 0x44 // Supplementary Status Register |
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| 100 | //#define UART_EBLR 0x48 // BOF Length Register (IR-IrDA and IR-CIR modes only) |
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| 101 | #define UART_SYSC 0x54 // System Configuration Register |
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| 102 | #define UART_SYSS 0x58 // System Status Register |
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| 103 | #define UART_WER 0x5C // Wake-up Enable Register |
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| 104 | #define UART_CFPS 0x60 // Carrier Frequency Prescaler Register |
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| 105 | |
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| 106 | /*-------------------------------------------------------------------------------------*/ |
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| 107 | /* SPI - Serial Peripheral Interface */ |
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| 108 | /*-------------------------------------------------------------------------------------*/ |
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| 109 | #define SPI1_BASE_ADD (OMAP35XX_L4_IO_BASE+0x98000) // routed to I/O sites on CSB703 |
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| 110 | #define SPI2_BASE_ADD (OMAP35XX_L4_IO_BASE+0x9A000) |
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| 111 | #define SPI3_BASE_ADD (OMAP35XX_L4_IO_BASE+0xB8000) // routed to AD7843 touch controller on CSB703 |
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| 112 | #define SPI4_BASE_ADD (OMAP35XX_L4_IO_BASE+0xBA000) |
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| 113 | #define SPI1_REG(_x_) *(vulong *)(SPI1_BASE_ADD + _x_) |
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| 114 | #define SPI2_REG(_x_) *(vulong *)(SPI2_BASE_ADD + _x_) |
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| 115 | #define SPI3_REG(_x_) *(vulong *)(SPI3_BASE_ADD + _x_) |
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| 116 | #define SPI4_REG(_x_) *(vulong *)(SPI4_BASE_ADD + _x_) |
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| 117 | |
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| 118 | // SPI Register Defines |
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| 119 | #define SPI_SYSCONFIG 0x10 // System Configuration Register |
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| 120 | #define SPI_SYSSTATUS 0x14 // System Status Register |
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| 121 | #define SPI_IRQSTATUS 0x18 // Interrupt Status Register |
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| 122 | #define SPI_IRQENABLE 0x1C // Interrupt Enable/Disable Register |
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| 123 | #define SPI_WAKEUPENABLE 0x20 // WakeUp Enable/Disable Register |
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| 124 | #define SPI_SYST 0x24 // System Test Register |
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| 125 | #define SPI_MODULCTRL 0x28 // Serial Port Interface Configuration Register |
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| 126 | #define SPI_CH0_CONF 0x2C // Channel 0 Configuration Register |
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| 127 | #define SPI_CH1_CONF 0x40 // Channel 1 Configuration Register |
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| 128 | #define SPI_CH2_CONF 0x54 // Channel 2 Configuration Register |
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| 129 | #define SPI_CH3_CONF 0x68 // Channel 3 Configuration Register |
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| 130 | #define SPI_CH0_STAT 0x30 // Channel 0 Status Register |
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| 131 | #define SPI_CH1_STAT 0x44 // Channel 1 Status Register |
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| 132 | #define SPI_CH2_STAT 0x58 // Channel 2 Status Register |
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| 133 | #define SPI_CH3_STAT 0x6C // Channel 3 Status Register |
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| 134 | #define SPI_CH0_CTRL 0x34 // Channel 0 Control Register |
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| 135 | #define SPI_CH1_CTRL 0x48 // Channel 1 ControlRegister |
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| 136 | #define SPI_CH2_CTRL 0x5C // Channel 2 ControlRegister |
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| 137 | #define SPI_CH3_CTRL 0x70 // Channel 3 ControlRegister |
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| 138 | #define SPI_TXD0 0x38 // Channel 0 Transmit Data Register |
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| 139 | #define SPI_TXD1 0x4C // Channel 1 Transmit Data Register |
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| 140 | #define SPI_TXD2 0x60 // Channel 2 Transmit Data Register |
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| 141 | #define SPI_TXD3 0x74 // Channel 3 Transmit Data Register |
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| 142 | #define SPI_RXD0 0x3C // Channel 0 Receive Data Register |
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| 143 | #define SPI_RXD1 0x50 // Channel 1 Receive Data Register |
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| 144 | #define SPI_RXD2 0x64 // Channel 2 Receive Data Register |
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| 145 | #define SPI_RXD3 0x78 // Channel 3 Receive Data Register |
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| 146 | #define SPI_XFERLEVEL 0x7C // FIFO Transfer Levels Register |
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| 147 | |
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| 148 | // SPI Channel x Configuration Bit Defines |
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| 149 | #define SPI_CH_CONF_CLKG BIT29 // 1 = One clock cycle granularity |
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| 150 | #define SPI_CH_CONF_FFER BIT28 // 1 = FIFO buffer is used to Receive data |
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| 151 | #define SPI_CH_CONF_FFEW BIT27 // 1 = FIFO buffer is used to Transmit data |
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| 152 | #define SPI_CH_CONF_TCS_0_5 (0x00 << 25) // 0.5 clock cycles between CS toggling and first (or last) edge of SPI clock |
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| 153 | #define SPI_CH_CONF_TCS_1_5 (0x01 << 25) // 1.5 clock cycles between CS toggling and first (or last) edge of SPI clock |
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| 154 | #define SPI_CH_CONF_TCS_2_5 (0x02 << 25) // 2.5 clock cycles between CS toggling and first (or last) edge of SPI clock |
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| 155 | #define SPI_CH_CONF_TCS_3_5 (0x03 << 25) // 3.5 clock cycles between CS toggling and first (or last) edge of SPI clock |
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| 156 | #define SPI_CH_CONF_SB_POL BIT24 // 1 = Start bit polarity is held to 1 during SPI transfer |
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| 157 | #define SPI_CH_CONF_SBE BIT23 // 1 = Start bit added before SPI transfer, 0 = default length specified by WL |
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| 158 | #define SPI_CH_CONF_SPIENSLV_0 (0x00 << 21) // Slave select detection enabled on CS0 |
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| 159 | #define SPI_CH_CONF_SPIENSLV_1 (0x01 << 21) // Slave select detection enabled on CS1 |
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| 160 | #define SPI_CH_CONF_SPIENSLV_2 (0x02 << 21) // Slave select detection enabled on CS2 |
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| 161 | #define SPI_CH_CONF_SPIENSLV_3 (0x03 << 21) // Slave select detection enabled on CS3 |
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| 162 | #define SPI_CH_CONF_FORCE BIT20 // 1 = CSx high when EPOL is 0 and low when EPOL is 1 |
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| 163 | #define SPI_CH_CONF_TURBO BIT19 // 1 = Turbo is activated |
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| 164 | #define SPI_CH_CONF_IS BIT18 // 1 = spim_simo selected for reception, 0 = spim_somi selected for reception |
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| 165 | #define SPI_CH_CONF_DPE1 BIT17 // 1 = no transmission on spim_simo, 0 = spim_simo selected for transmission |
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| 166 | #define SPI_CH_CONF_DPE0 BIT16 // 1 = no transmission on spim_somi, 0 = spim_somi selected for transmission |
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| 167 | #define SPI_CH_CONF_DMAR BIT15 // 1 = DMA read request enabled |
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| 168 | #define SPI_CH_CONF_DMAW BIT14 // 1 = DMA write request enabled |
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| 169 | #define SPI_CH_CONF_TRM_TR (0x00 << 12) // Transmit and receive mode |
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| 170 | #define SPI_CH_CONF_TRM_RO (0x01 << 12) // Receive-only mode |
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| 171 | #define SPI_CH_CONF_TRM_TO (0x02 << 12) // Transmit-only mode |
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| 172 | #define SPI_CH_CONF_WL(_x_) ((_x_ & 0x1f) << 7) // SPI word length, 0x7 = 8-bit |
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| 173 | #define SPI_CH_CONF_EPOL BIT6 // 1 = SPIM_CSx is low during active state, 0 = high during active state |
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| 174 | #define SPI_CH_CONF_CLKD(_x_) ((_x_ & 0xf) << 2) // Frequency divider for spim_clk |
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| 175 | #define SPI_CH_CONF_POL BIT1 // 1 = spim_clk is low during active state, 0 = high during active state |
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| 176 | #define SPI_CH_CONF_PHA BIT0 // 1 = data latched on even-numbered edges, 0 = data latched on odd-numbered edges |
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| 177 | |
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| 178 | // SPI Interrupt Status Register Bit Defines |
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| 179 | #define SPI_RX3_FULL BIT14 // |
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| 180 | #define SPI_TX3_EMPTY BIT12 // |
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| 181 | #define SPI_RX2_FULL BIT10 // |
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| 182 | #define SPI_TX2_EMPTY BIT8 // |
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| 183 | #define SPI_RX1_FULL BIT14 // |
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| 184 | #define SPI_TX1_EMPTY BIT6 // |
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| 185 | #define SPI_RX0_FULL BIT2 // |
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| 186 | #define SPI_TX0_EMPTY BIT0 // |
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| 187 | |
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| 188 | // SPI Channel Status Register Bit Defines |
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| 189 | #define SPI_RXF_FULL BIT6 // |
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| 190 | #define SPI_RXF_EMPTY BIT5 // |
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| 191 | #define SPI_TXF_FULL BIT4 // |
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| 192 | #define SPI_TXF_EMPTY BIT3 // |
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| 193 | #define SPI_CH_EOT BIT2 // |
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| 194 | #define SPI_CH_TX0_EMPTY BIT1 // |
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| 195 | #define SPI_CH_RX0_FULL BIT0 // |
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| 196 | |
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| 197 | /*-------------------------------------------------------------------------------------*/ |
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| 198 | /* General Purpose Timers */ |
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| 199 | /*-------------------------------------------------------------------------------------*/ |
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| 200 | #define OMAP35XX_GPT1 0x48318000 |
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| 201 | #define OMAP35XX_GPT2 0x49032000 |
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| 202 | #define OMAP35XX_GPT3 0x49034000 |
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| 203 | #define OMAP35XX_GPT4 0x49036000 |
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| 204 | #define OMAP35XX_GPT5 0x49038000 |
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| 205 | #define OMAP35XX_GPT6 0x4903A000 |
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| 206 | #define OMAP35XX_GPT7 0x4903C000 |
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| 207 | #define OMAP35XX_GPT8 0x4903E000 |
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| 208 | #define OMAP35XX_GPT9 0x49040000 |
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| 209 | #define OMAP35XX_GPT10 0x48086000 |
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| 210 | #define OMAP35XX_GPT11 0x48088000 |
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| 211 | #define OMAP35XX_GPT12 0x48304000 |
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| 212 | |
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| 213 | /*-------------------------------------------------------------------------------------*/ |
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| 214 | /* General Purpose I/O */ |
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| 215 | /*-------------------------------------------------------------------------------------*/ |
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| 216 | #define GPIO1_BASE_ADD 0x48310000 |
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| 217 | #define GPIO2_BASE_ADD 0x49050000 |
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| 218 | #define GPIO3_BASE_ADD 0x49052000 |
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| 219 | #define GPIO4_BASE_ADD 0x49054000 |
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| 220 | #define GPIO5_BASE_ADD 0x49056000 |
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| 221 | #define GPIO6_BASE_ADD 0x49058000 |
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| 222 | #define GPIO1_REG(_x_) *(vulong *)(GPIO1_BASE_ADD + _x_) |
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| 223 | #define GPIO2_REG(_x_) *(vulong *)(GPIO2_BASE_ADD + _x_) |
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| 224 | #define GPIO3_REG(_x_) *(vulong *)(GPIO3_BASE_ADD + _x_) |
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| 225 | #define GPIO4_REG(_x_) *(vulong *)(GPIO4_BASE_ADD + _x_) |
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| 226 | #define GPIO5_REG(_x_) *(vulong *)(GPIO5_BASE_ADD + _x_) |
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| 227 | #define GPIO6_REG(_x_) *(vulong *)(GPIO6_BASE_ADD + _x_) |
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| 228 | |
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| 229 | /* GPIO Register offsets */ |
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| 230 | #define GPIO_SYSCONFIG 0x10 // |
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| 231 | #define GPIO_SYSSTATUS 0x14 // |
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| 232 | #define GPIO_CTRL 0x30 // |
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| 233 | #define GPIO_OE 0x34 // |
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| 234 | #define GPIO_DATAIN 0x38 // |
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| 235 | #define GPIO_DATAOUT 0x3C // |
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| 236 | #define GPIO_CLEARDATAOUT 0x90 // |
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| 237 | #define GPIO_SETDATAOUT 0x94 // |
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| 238 | |
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| 239 | /*-------------------------------------------------------------------------------------*/ |
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| 240 | /* WatchDog Timers (1 secure, 3 GP) */ |
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| 241 | /*-------------------------------------------------------------------------------------*/ |
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| 242 | #define WD1_BASE_ADD 0x4830C000 |
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| 243 | #define WD2_BASE_ADD 0x48314000 |
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| 244 | #define WD3_BASE_ADD 0x49030000 |
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| 245 | #define WD1_REG(_x_) *(vulong *)(WD1_BASE_ADD + _x_) |
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| 246 | #define WD2_REG(_x_) *(vulong *)(WD2_BASE_ADD + _x_) |
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| 247 | #define WD3_REG(_x_) *(vulong *)(WD3_BASE_ADD + _x_) |
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| 248 | |
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| 249 | /* WatchDog Timer Register offsets */ |
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| 250 | #define WD_CONFIG 0x10 // System Configuration Register |
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| 251 | #define WD_STATUS 0x14 // System Configuration Register |
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| 252 | #define WD_WISR 0x18 // System Configuration Register |
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| 253 | #define WD_WIER 0x1C // System Configuration Register |
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| 254 | #define WD_WCLR 0x24 // System Configuration Register |
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| 255 | #define WD_WCRR 0x28 // System Configuration Register |
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| 256 | #define WD_WLDR 0x2C // System Configuration Register |
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| 257 | #define WD_WTGR 0x30 // System Configuration Register |
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| 258 | #define WD_WWPS 0x34 // System Configuration Register |
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| 259 | #define WD_WSPR 0x48 // System Configuration Register |
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| 260 | |
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| 261 | /*-------------------------------------------------------------------------------------*/ |
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| 262 | /* 32KTIMER */ |
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| 263 | /*-------------------------------------------------------------------------------------*/ |
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| 264 | #define SYNC_32KTIMER_BASE (0x48320000) |
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| 265 | #define S32K_CR (SYNC_32KTIMER_BASE+0x10) |
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| 266 | |
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| 267 | /*-------------------------------------------------------------------------------------*/ |
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| 268 | /* System Control Module */ |
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| 269 | /*-------------------------------------------------------------------------------------*/ |
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| 270 | /* Module Name Base Address Size */ |
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| 271 | /* |
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| 272 | INTERFACE 0x48002000 36 bytes |
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| 273 | PADCONFS 0x48002030 564 bytes |
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| 274 | GENERAL 0x48002270 767 bytes |
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| 275 | MEM_WKUP 0x48002600 1K byte |
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| 276 | PADCONFS_WKU 0x48002A00 80 bytes |
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| 277 | GENERAL_WKUP 0x48002A60 31 bytes |
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| 278 | */ |
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| 279 | /*-------------------------------------------------------------------------------------*/ |
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| 280 | #define OMAP35XX_CTRL_BASE (OMAP35XX_L4_IO_BASE+0x2000) |
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| 281 | #define SCM_REG(_x_) *(vulong *)(OMAP35XX_CTRL_BASE + _x_) |
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| 282 | |
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| 283 | /* Pad Configuration Registers */ |
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| 284 | /* Note: Cogent is only defining the PADCONFS registers that are used in Micromonitor */ |
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| 285 | #define PADCONFS_GPMC_NCS3 0xB4 // NCS3[15:0], NCS4[31:16] |
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| 286 | #define PADCONFS_GPMC_NCS5 0xB8 // NCS5[15:0], EXP_INTX[31:16] |
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| 287 | #define PADCONFS_GPMC_NCS7 0xBC // LCD_BKL_X[15:0], LCLK[31:16] |
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| 288 | #define PADCONFS_GPMC_NADV_ALE 0xC0 // NADV_ALE[15:0], NOE[31:16] |
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| 289 | #define PADCONFS_GPMC_NWE 0xC4 // NWE[15:0], NBE0_CLE[31:16] |
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| 290 | #define PADCONFS_DSS_PCLK 0xD4 // LCD_PCLK_X[15:0], LCD_HS_X[31:16] |
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| 291 | #define PADCONFS_DSS_VSYNC 0xD8 // LCD_VS_X[15:0], LCD_OE_X[31:16] |
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| 292 | #define PADCONFS_DSS_DATA0 0xDC // LCD_B0_X[15:0], LCD_B1_X[31:16] |
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| 293 | #define PADCONFS_DSS_DATA2 0xE0 // LCD_B2_X[15:0], LCD_B3_X[31:16] |
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| 294 | #define PADCONFS_DSS_DATA4 0xE4 // LCD_B4_X[15:0], LCD_B5_X[31:16] |
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| 295 | #define PADCONFS_DSS_DATA6 0xE8 // LCD_G0_X[15:0], LCD_G1_X[31:16] |
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| 296 | #define PADCONFS_DSS_DATA8 0xEC // LCD_G2_X[15:0], LCD_G3_X[31:16] |
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| 297 | #define PADCONFS_DSS_DATA10 0xF0 // LCD_G4_X[15:0], LCD_G5_X[31:16] |
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| 298 | #define PADCONFS_DSS_DATA12 0xF4 // LCD_R0_X[15:0], LCD_R1_X[31:16] |
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| 299 | #define PADCONFS_DSS_DATA14 0xF8 // LCD_R2_X[15:0], LCD_R3_X[31:16] |
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| 300 | #define PADCONFS_DSS_DATA16 0xFC // LCD_R4_X[15:0], LCD_R5_X[31:16] |
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| 301 | #define PADCONFS_DSS_DATA18 0x100 // SPI1_CLK_X[15:0], SPI1_MOSI_X[31:16] |
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| 302 | #define PADCONFS_DSS_DATA20 0x104 // SPI1_MISO_X[15:0], *SPI1_CS0_X[31:16] |
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| 303 | #define PADCONFS_DSS_DATA22 0x108 // GPIO7_X[15:0], NC[31:16] |
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| 304 | #define PADCONFS_MMC1_DAT4 0x150 // *I2C_INT_X[15:0], *PIRQ_X[31:16] |
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| 305 | #define PADCONFS_MMC1_DAT6 0x154 // GPIO0_X[15:0], GPIO1_X[31:16] |
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| 306 | #define PADCONFS_MCBSP3_CLKX 0x170 // D_TXD[15:0], D_RXD[31:16] |
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| 307 | #define PADCONFS_SYS_NIRQ 0x1E0 // FIQ[15:0], SYS_CLK2[31:16] |
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| 308 | #define PADCONFS_SYS_OFF_MODE 0xA18 // OFF_MODE_X[15:0], USB_CLK[31:16] |
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| 309 | #define PADCONFS_GPMC_WAIT2 0xD0 // NA[15:0], E_INTX[31:16] |
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| 310 | #define PADCONFS_MMC1_CLK 0x144 // MMC1_CLK[15:0], MMC1_CMD[31:16] |
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| 311 | #define PADCONFS_MMC1_DAT0 0x148 // MMC1_DAT0[15:0], MMC1_DAT1[31:16] |
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| 312 | #define PADCONFS_MMC1_DAT2 0x14C // MMC1_DAT2[15:0], MMC1_DAT3[31:16] |
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| 313 | |
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| 314 | |
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| 315 | #define CM_REV_REG 0x48004800 |
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| 316 | #define PRM_REV_REG 0x48306804 |
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| 317 | #define CM_REV_MAJ() ((*(volatile unsigned long *)CM_REV_REG & 0xf0)>>4) |
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| 318 | #define CM_REV_MIN() (*(volatile unsigned long *)CM_REV_REG & 0x0f) |
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| 319 | #define PRM_REV_MAJ() ((*(volatile unsigned long *)PRM_REV_REG & 0xf0)>>4) |
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| 320 | #define PRM_REV_MIN() (*(volatile unsigned long *)PRM_REV_REG & 0x0f) |
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| 321 | |
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| 322 | /* MMC registers... |
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| 323 | */ |
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| 324 | #define CM_FCLKEN1_CORE 0x48004a00 |
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| 325 | #define CM_ICLKEN1_CORE 0x48004a10 |
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| 326 | #define CM_IDLEST1_CORE 0x48004a20 |
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| 327 | #define CM_AUTOIDLE1_CORE 0x48004a30 |
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| 328 | #define PM_WKEN1_CORE 0x48306aa0 |
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| 329 | #define PM_MPUGRPSEL1_CORE 0x48306aa4 |
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| 330 | #define PM_IVA2GRPSEL1_CORE 0x48306aa8 |
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| 331 | #define PM_WKST1_CORE 0x48306ab0 |
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| 332 | #define CONTROL_DEVCONF0 0x48002274 |
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| 333 | #define MMC1_BASE_ADD 0x4809c000 |
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| 334 | #define MMC2_BASE_ADD 0x480ad000 |
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| 335 | #define MMC3_BASE_ADD 0x480b4000 |
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| 336 | #define MMC1_REG(_x_) *(vulong *)(MMC1_BASE_ADD + _x_) |
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| 337 | #define MMC2_REG(_x_) *(vulong *)(MMC2_BASE_ADD + _x_) |
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| 338 | #define MMC3_REG(_x_) *(vulong *)(MMC3_BASE_ADD + _x_) |
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| 339 | #define MMCHS_SYSCONFIG 0x10 |
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| 340 | #define MMCHS_SYSSTATUS 0x14 |
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| 341 | #define MMCHS_CSRE 0x24 |
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| 342 | #define MMCHS_SYSTEST 0x28 |
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| 343 | #define MMCHS_CON 0x2C |
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| 344 | #define MMCHS_PWCNT 0x30 |
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| 345 | #define MMCHS_BLK 0x104 |
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| 346 | #define MMCHS_ARG 0x108 |
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| 347 | #define MMCHS_CMD 0x10C |
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| 348 | #define MMCHS_RSP10 0x110 |
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| 349 | #define MMCHS_RSP32 0x114 |
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| 350 | #define MMCHS_RSP54 0x118 |
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| 351 | #define MMCHS_RSP76 0x11C |
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| 352 | #define MMCHS_DATA 0x120 |
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| 353 | #define MMCHS_PSTATE 0x124 |
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| 354 | #define MMCHS_HCTL 0x128 |
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| 355 | #define MMCHS_SYSCTL 0x12C |
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| 356 | #define MMCHS_STAT 0x130 |
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| 357 | #define MMCHS_IE 0x134 |
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| 358 | #define MMCHS_ISE 0x138 |
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| 359 | #define MMCHS_AC12 0x13C |
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| 360 | #define MMCHS_CAPA 0x140 |
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| 361 | #define MMCHS_CUR_CAPA 0x148 |
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| 362 | #define MMCHS_REV 0x1FC |
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| 363 | |
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| 364 | /* Miscellaneous MMC register bits... |
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| 365 | * (only specified the ones I use) |
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| 366 | */ |
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| 367 | #define EN_MMC1 (1 << 24) |
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| 368 | #define ST_MMC1 (1 << 24) |
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| 369 | #define AUTO_MMC1 (1 << 24) |
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| 370 | #define GRPSEL_MMC1 (1 << 24) |
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| 371 | #define VS18 0x04000000 |
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| 372 | #define VS30 0x02000000 |
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| 373 | #define VS33 0x01000000 |
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| 374 | #define MMCINIT 0x00000002 |
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| 375 | #define ODE 0x00000001 |
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| 376 | #define SVDS 0x00000e00 |
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| 377 | #define SVDS18 (5 << 9) |
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| 378 | #define SVDS30 (6 << 9) |
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| 379 | #define SVDS33 (7 << 9) |
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| 380 | #define SDBP 0x00000100 |
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| 381 | #define ICE 0x00000001 |
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| 382 | #define ICS 0x00000002 |
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| 383 | #define CEN 0x00000004 |
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| 384 | #define CLKD(v) ((v & 0x3ff) << 6) |
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| 385 | #define CLKDMSK (0x3ff << 6) |
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| 386 | #define CLKACTIVITYMSK (3 << 8) |
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| 387 | #define CLKACTIVITY(n) ((n & 3) << 8) |
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| 388 | #define SIDLEMODEMSK (3 << 3) |
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| 389 | #define SIDLEMODE(n) ((n & 3) << 3) |
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| 390 | #define ENWAKEUP (1 << 2) |
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| 391 | #define IWE (1 << 24) |
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| 392 | #define AUTOIDLE 1 |
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| 393 | #define CLKEXTFREE (1 << 16) |
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| 394 | #define SRESET 0x00000002 |
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| 395 | #define CC 0x00000001 |
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| 396 | #define RESETDONE 0x00000001 |
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| 397 | #define IE_ALL 0x317f8337 |
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| 398 | #define CDP (1 << 7) |
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| 399 | #define CMD(v) ((v & 0x3f) << 24) |
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| 400 | #define CMDMSK (0x3f << 24) |
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| 401 | #define CMDI 0x00000001 |
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| 402 | #define DEBOUNCE (3 << 16) |
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| 403 | #define CCRC (1 << 17) |
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| 404 | #define DCRC (1 << 21) |
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| 405 | #define CERR (1 << 28) |
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| 406 | #define CTO (1 << 16) |
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| 407 | #define DP (1 << 21) |
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| 408 | #define RSPTYPE_NONE 0x00000000 |
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| 409 | #define RSPTYPE_136 0x00010000 |
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| 410 | #define RSPTYPE_48 0x00020000 |
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| 411 | #define RSPTYPE_48BSY 0x00030000 |
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| 412 | #define RSPTYPE 0x00030000 |
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| 413 | #define SRD (1 << 26) |
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| 414 | #define SRC (1 << 25) |
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| 415 | #define SRA (1 << 24) |
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| 416 | #define DTOMSK (0xf<<16) |
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| 417 | #define DTO(a) ((a&0xf) << 16) |
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| 418 | #define NBLK(a) ((a&0xffff) << 16) |
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| 419 | #define BLEN(a) (a&0x7ff) |
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| 420 | #define MMCSDIO1ADPCLKISEL (1 << 24) |
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| 421 | |
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| 422 | /* PBIAS... |
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| 423 | */ |
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| 424 | #define CONTROL_PBIAS_LITE 0x48002520 |
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| 425 | #define PBIAS_LITE_VMMC1_3V (0x0101) |
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| 426 | #define MMC_PWR_STABLE (0x0202) |
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| 427 | #define PBIAS_LITE_VMMC1_52MHZ (0x0404) |
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| 428 | #define PBIAS_LITE_MMC1_ERROR (0x0808) |
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| 429 | #define PBIAS_LITE_MMC1_HIGH (0x8080) |
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| 430 | |
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| 431 | /* Control status... |
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| 432 | */ |
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| 433 | #define CONTROL_STATUS 0x480022f0 |
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| 434 | #define SYSBOOT 0x3f |
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| 435 | #define DEVICETYPE (0x3 << 8) |
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| 436 | |
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| 437 | /* 16 bit access CONTROL */ |
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| 438 | #define MUX_VAL(OFFSET,VALUE)\ |
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| 439 | *(unsigned short *) (OMAP35XX_CTRL_BASE + (OFFSET)) = VALUE; |
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| 440 | |
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| 441 | #define CP(x) (CONTROL_PADCONF_##x) |
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| 442 | |
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| 443 | #define CONTROL_PADCONF_DSS_DATA18 0x0100 |
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| 444 | #define CONTROL_PADCONF_DSS_DATA19 0x0102 |
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| 445 | #define CONTROL_PADCONF_DSS_DATA20 0x0104 |
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| 446 | #define CONTROL_PADCONF_DSS_DATA21 0x0106 |
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| 447 | |
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| 448 | #define CONTROL_PADCONF_MMC1_CLK 0x0144 |
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| 449 | #define CONTROL_PADCONF_MMC1_CMD 0x0146 |
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| 450 | #define CONTROL_PADCONF_MMC1_DAT0 0x0148 |
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| 451 | #define CONTROL_PADCONF_MMC1_DAT1 0x014A |
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| 452 | #define CONTROL_PADCONF_MMC1_DAT2 0x014C |
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| 453 | #define CONTROL_PADCONF_MMC1_DAT3 0x014E |
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| 454 | |
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| 455 | #define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 |
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| 456 | #define CONTROL_PADCONF_HSUSB0_STP 0x01A4 |
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| 457 | #define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 |
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| 458 | #define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 |
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| 459 | #define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA |
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| 460 | #define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC |
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| 461 | #define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE |
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| 462 | #define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 |
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| 463 | #define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 |
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| 464 | #define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 |
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| 465 | #define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 |
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| 466 | #define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 |
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| 467 | #define CONTROL_PADCONF_I2C1_SCL 0x01BA |
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| 468 | #define CONTROL_PADCONF_I2C1_SDA 0x01BC |
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| 469 | #define CONTROL_PADCONF_McBSP3_DX 0x016C |
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| 470 | |
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| 471 | /* bits used in control reg's above |
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| 472 | * IEN - Input Enable |
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| 473 | * IDIS - Input Disable |
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| 474 | * PTD - Pull type Down |
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| 475 | * PTU - Pull type Up |
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| 476 | * DIS - Pull type selection is inactive |
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| 477 | * EN - Pull type selection is active |
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| 478 | * M0 - Mode 0 |
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| 479 | */ |
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| 480 | |
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| 481 | #define IEN (1 << 8) |
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| 482 | |
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| 483 | #define IDIS (0 << 8) |
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| 484 | #define PTU (1 << 4) |
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| 485 | #define PTD (0 << 4) |
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| 486 | #define EN (1 << 3) |
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| 487 | #define DIS (0 << 3) |
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| 488 | |
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| 489 | #define M0 0 /* modes */ |
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| 490 | #define M1 1 |
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| 491 | #define M2 2 |
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| 492 | #define M3 3 |
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| 493 | #define M4 4 |
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| 494 | #define M5 5 |
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| 495 | #define M6 6 |
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| 496 | #define M7 7 |
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| 497 | |
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