source: umon/ports/beagleboneblack/rom_reset.S @ 8a80d54

Last change on this file since 8a80d54 was 8a80d54, checked in by Jarielle Catbagan <jcatbagan93@…>, on Jul 16, 2015 at 11:26:44 AM

BBB: rom_reset.S: Initialize the SP at the top of SRAM prior to invoking pll_init and ddr_init

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1    .file "rom_reset.S"
2
3/*
4 * General notice:
5 * This code is part of a boot-monitor package developed as a generic base
6 * platform for embedded system designs.  As such, it is likely to be
7 * distributed to various projects beyond the control of the original
8 * author.  Please notify the author of any enhancements made or bugs found
9 * so that all may benefit from the changes.  In addition, notification back
10 * to the author will allow the new user to pick up changes that may have
11 * been made by other users after this version of the code was distributed.
12 *
13 * Author:  Ed Sutter
14 * email:   esutter@lucent.com
15 * phone:   908-582-2351
16 *
17 *
18 * Modified for the CSB740 - OMAP3530 Single Board
19 *
20 * rom_reset.s:
21  */
22
23#include "warmstart.h"
24#include "am335x.h"
25#include "config.h"
26
27    /*
28     * Have a separate stack for each processor mode.
29     */
30
31    /* define sizes for each mode's stack */
32    .equ FiqStackSz, 4096
33    .equ IrqStackSz, 4096
34    .equ AbtStackSz, 4096
35    .equ UndStackSz, 4096
36    .equ SysStackSz, 4096
37
38    /* declare the stacks */
39    .extern MonStack
40    .global FiqStack
41    .global IrqStack
42    .global AbtStack
43    .global UndStack
44    .global SysStack       
45    .global raise
46    .global cache_init
47   
48    /* allocate the stacks */
49    .comm   FiqStack, FiqStackSz    /* for the FIQ mode */
50    .comm   IrqStack, IrqStackSz    /* for the IRQ mode */
51    .comm   AbtStack, AbtStackSz    /* for the Abort mode */
52    .comm   UndStack, UndStackSz    /* for the Undef mode */
53    .comm   SysStack, SysStackSz    /* for the System mode */
54    /* User mode has the same stack as system mode. */
55
56/*********************************************************************/
57   
58    .extern start
59    .extern pll_init
60    .extern ddr_init
61
62    .global reset
63    .global coldstart
64    .global lukewarmstart
65    .global warmstart
66
67    .text
68       
69    /*
70     * Exception table at address 0
71     */
72reset: 
73    b coldstart
74    b undefined_instruction
75    b software_interrupt
76    b abort_prefetch
77    b abort_data
78    b not_assigned
79    b interrupt_request
80    b fast_interrupt_request
81
82#include "etheraddr.S"
83#include "moncomptr.S"
84#include "alttfsdevtbl.S"
85
86coldstart:
87        ldr     pc, =coldstart_1                // jump to actual ROM location
88        nop
89
90coldstart_1:
91        /* Make sure interrupts are off, and we're in supervisor mode...
92         */
93        mrs     r0,cpsr                         // Retreive current program status register
94        bic     r0,r0,#0x1f                     // Clear all mode bits.
95        orr     r0,r0,#0xd3                     // Set mode to supervisor, IRQ FIQ disabled.
96        msr     cpsr,r0
97
98//      bl cache_init
99
100/********************************************************************/
101
102midstart:
103    ldr r0, =INITIALIZE
104   
105    /* fall-through to 'lukewarmstart' */
106
107/********************************************************************/
108   
109lukewarmstart: 
110    /* Save the argument to r11 */
111    mov r11, r0
112
113    /*
114     * *** DO NOT TOUCH R11 ***
115     */
116
117    /*
118     * Set-up the stack-pointers for all operating modes
119     */
120
121    /* FIQ mode */
122    mrs r0, cpsr                /* move CPSR to r0 */
123    bic r0, r0, #0x1f           /* clear all mode bits */
124    orr r0, r0, #0x11           /* set FIQ mode bits */
125    msr CPSR_c, r0              /* move back to CPSR */
126    ldr sp, =(FiqStack + FiqStackSz - 4)    /* initialize the stack ptr */
127    /* IRQ mode */
128    mrs r0, cpsr                /* move CPSR to r0 */
129    bic r0, r0, #0x1f           /* clear all mode bits */
130    orr r0, r0, #0x12           /* set IRQ mode bits */
131    msr CPSR_c, r0              /* move back to CPSR */
132    ldr sp, =(IrqStack + IrqStackSz - 4)    /* initialize the stack ptr */
133    /* Abort mode */
134    mrs r0, cpsr                /* move CPSR to r0 */
135    bic r0, r0, #0x1f           /* clear all mode bits */
136    orr r0, r0, #0x17           /* set Abort mode bits */
137    msr CPSR_c, r0              /* move back to CPSR */
138    ldr sp, =(AbtStack + AbtStackSz - 4)    /* initialize the stack ptr */
139    /* Undef mode */
140    mrs r0, cpsr                /* move CPSR to r0 */
141    bic r0, r0, #0x1f           /* clear all mode bits */
142    orr r0, r0, #0x1b           /* set Undef mode bits */
143    msr CPSR_c, r0              /* move back to CPSR */
144    ldr sp, =(UndStack + UndStackSz - 4)    /* initialize the stack ptr */
145    /* System mode */
146    mrs r0, cpsr                /* move CPSR to r0 */
147    bic r0, r0, #0x1f           /* clear all mode bits */
148    orr r0, r0, #0x1f           /* set System mode bits */
149    msr CPSR_c, r0              /* move back to CPSR */
150    ldr sp, =(SysStack + SysStackSz - 4)    /* initialize the stack ptr */
151    /* 'warmstart' will take us back to SVC mode
152       stack for SVC mode will also be setup in warmstart */
153
154    mov r0, r11     /* get argument back from r11 */
155    b   warmstart
156
157   
158/********************************************************************/
159   
160warmstart:
161    /* Save the argument to r11 */
162    mov r11, r0
163
164    /*
165     * *** DO NOT TOUCH R11 ***
166     */
167
168
169    /* Change (back) to SVC mode */
170    mrs r0, cpsr                /* move CPSR to r0 */
171    bic r0, r0, #0x1f           /* clear all mode bits */
172    orr r0, r0, #0x13           /* set System mode bits */
173    msr CPSR_c, r0              /* move back to CPSR */
174
175    /* Initialize the SP at the top of SRAM outside of the uMon code
176     * space so that the following two C functions can be invoked
177     * properly to take care of PLL and DDR3 initialization.
178     */
179    movw sp, #0x5e00
180    movt sp, #0x4030
181
182    /* Initialize the MPU, Core, DDR, and Per PLLs.  Furthermore,
183     * initialize the external DDR3 memory as well.
184     */
185dev_init:
186    bl pll_init
187    bl ddr_init
188
189    /* Reset the stack pointer for the SVC mode (our current mode) */
190    ldr sp, =(MonStack + MONSTACKSIZE - 4)
191
192    /*
193     * Restore argument which was saved to r11 and jump to
194     * the C function start().
195     */
196   
197    mov r0, r11
198jump_to_c:
199    bl start
200
201    /* the C code should never return */
202    b reset
203
204.align 4
205
206
207/*********************************************************************
208 * simple delay loop
209 */
210delay_200:
211        ldr             r3, =200                        /* loop count */
212delay_loop:
213        subs    r3,r3,#1
214        bne             delay_loop
215        nop
216
217        mov             pc, lr
218
219raise:  mov             pc, lr  /* to make linker happy */
220
221/*********************************************************************
222 * Cache initialization:
223 * Turn everything down and invalidate...
224 */
225cache_init:
226        /* Make sure caches are turned down...
227         */
228        mrc     p15, 0, r3, cr1, cr0, 0         // turn off I/D-cache
229        bic     r3, r3, #4096                           // I
230        bic     r3, r3, #4                                      // D
231        mcr     p15, 0, r3, cr1, cr0, 0
232       
233        mov     r0, #0
234//      mcr     p15, 0, r0, cr7, cr7, 0  // arm_cache_invalidate
235        mcr     p15, 0, r0, cr7, cr6, 0  // arm_dcache_invalidate
236        mcr     p15, 0, r0, cr7, cr5, 0  // arm_icache_invalidate
237
238        mrc     p15, 0, r0, cr1, cr0, 1  // l2cache_disable
239        bic     r0, r0, #2
240        mcr     p15, 0, r0, cr1, cr0, 1
241
242        mov     r0, #1
243        mrc     p15, 1, r0, cr0, cr0, 1  // emu_ext_boot_l2_inv
244        mov             pc, lr
245
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