source: umon/ports/beagleboneblack/rom_reset.S @ 63834b9

Last change on this file since 63834b9 was 63834b9, checked in by Jarielle Catbagan <jcatbagan93@…>, on Aug 21, 2015 at 5:05:59 PM

BBB: Add proper attributions to the files modified

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1    .file "rom_reset.S"
2
3/*
4 * General notice:
5 * This code is part of a boot-monitor package developed as a generic base
6 * platform for embedded system designs.  As such, it is likely to be
7 * distributed to various projects beyond the control of the original
8 * author.  Please notify the author of any enhancements made or bugs found
9 * so that all may benefit from the changes.  In addition, notification back
10 * to the author will allow the new user to pick up changes that may have
11 * been made by other users after this version of the code was distributed.
12 *
13 * Author:  Ed Sutter
14 * email:   esutter@lucent.com
15 * phone:   908-582-2351
16 *
17 *
18 * Adapted by Jarielle Catbagan for the Beaglebone Black
19 * email: jcatbagan93@gmail.com
20 */
21
22#include "warmstart.h"
23#include "am335x.h"
24#include "config.h"
25
26    /*
27     * Have a separate stack for each processor mode.
28     */
29
30    /* define sizes for each mode's stack */
31    .equ FiqStackSz, 4096
32    .equ IrqStackSz, 4096
33    .equ AbtStackSz, 4096
34    .equ UndStackSz, 4096
35    .equ SysStackSz, 4096
36
37    /* declare the stacks */
38    .extern MonStack
39    .global FiqStack
40    .global IrqStack
41    .global AbtStack
42    .global UndStack
43    .global SysStack       
44    .global raise
45    .global cache_init
46   
47    /* allocate the stacks */
48    .comm   FiqStack, FiqStackSz    /* for the FIQ mode */
49    .comm   IrqStack, IrqStackSz    /* for the IRQ mode */
50    .comm   AbtStack, AbtStackSz    /* for the Abort mode */
51    .comm   UndStack, UndStackSz    /* for the Undef mode */
52    .comm   SysStack, SysStackSz    /* for the System mode */
53    /* User mode has the same stack as system mode. */
54
55/*********************************************************************/
56   
57    .extern start
58    .extern pll_init
59    .extern ddr_init
60
61    .global reset
62    .global coldstart
63    .global lukewarmstart
64    .global warmstart
65
66    .text
67       
68    /*
69     * Exception table at address 0
70     */
71reset: 
72    b coldstart
73    b undefined_instruction
74    b software_interrupt
75    b abort_prefetch
76    b abort_data
77    b not_assigned
78    b interrupt_request
79    b fast_interrupt_request
80
81#include "etheraddr.S"
82#include "moncomptr.S"
83#include "alttfsdevtbl.S"
84
85coldstart:
86        ldr     pc, =coldstart_1                // jump to actual ROM location
87        nop
88
89coldstart_1:
90        /* Make sure interrupts are off, and we're in supervisor mode...
91         */
92        mrs     r0,cpsr                         // Retreive current program status register
93        bic     r0,r0,#0x1f                     // Clear all mode bits.
94        orr     r0,r0,#0xd3                     // Set mode to supervisor, IRQ FIQ disabled.
95        msr     cpsr,r0
96
97//      bl cache_init
98
99/********************************************************************/
100
101midstart:
102    ldr r0, =INITIALIZE
103   
104    /* fall-through to 'lukewarmstart' */
105
106/********************************************************************/
107   
108lukewarmstart: 
109    /* Save the argument to r11 */
110    mov r11, r0
111
112    /*
113     * *** DO NOT TOUCH R11 ***
114     */
115
116    /*
117     * Set-up the stack-pointers for all operating modes
118     */
119
120    /* FIQ mode */
121    mrs r0, cpsr                /* move CPSR to r0 */
122    bic r0, r0, #0x1f           /* clear all mode bits */
123    orr r0, r0, #0x11           /* set FIQ mode bits */
124    msr CPSR_c, r0              /* move back to CPSR */
125    ldr sp, =(FiqStack + FiqStackSz - 4)    /* initialize the stack ptr */
126    /* IRQ mode */
127    mrs r0, cpsr                /* move CPSR to r0 */
128    bic r0, r0, #0x1f           /* clear all mode bits */
129    orr r0, r0, #0x12           /* set IRQ mode bits */
130    msr CPSR_c, r0              /* move back to CPSR */
131    ldr sp, =(IrqStack + IrqStackSz - 4)    /* initialize the stack ptr */
132    /* Abort mode */
133    mrs r0, cpsr                /* move CPSR to r0 */
134    bic r0, r0, #0x1f           /* clear all mode bits */
135    orr r0, r0, #0x17           /* set Abort mode bits */
136    msr CPSR_c, r0              /* move back to CPSR */
137    ldr sp, =(AbtStack + AbtStackSz - 4)    /* initialize the stack ptr */
138    /* Undef mode */
139    mrs r0, cpsr                /* move CPSR to r0 */
140    bic r0, r0, #0x1f           /* clear all mode bits */
141    orr r0, r0, #0x1b           /* set Undef mode bits */
142    msr CPSR_c, r0              /* move back to CPSR */
143    ldr sp, =(UndStack + UndStackSz - 4)    /* initialize the stack ptr */
144    /* System mode */
145    mrs r0, cpsr                /* move CPSR to r0 */
146    bic r0, r0, #0x1f           /* clear all mode bits */
147    orr r0, r0, #0x1f           /* set System mode bits */
148    msr CPSR_c, r0              /* move back to CPSR */
149    ldr sp, =(SysStack + SysStackSz - 4)    /* initialize the stack ptr */
150    /* 'warmstart' will take us back to SVC mode
151       stack for SVC mode will also be setup in warmstart */
152
153    mov r0, r11     /* get argument back from r11 */
154    b   warmstart
155
156   
157/********************************************************************/
158   
159warmstart:
160    /* Save the argument to r11 */
161    mov r11, r0
162
163    /*
164     * *** DO NOT TOUCH R11 ***
165     */
166
167
168    /* Change (back) to SVC mode */
169    mrs r0, cpsr                /* move CPSR to r0 */
170    bic r0, r0, #0x1f           /* clear all mode bits */
171    orr r0, r0, #0x13           /* set System mode bits */
172    msr CPSR_c, r0              /* move back to CPSR */
173
174    /* Initialize the SP at the top of SRAM outside of the uMon code
175     * space so that the following two C functions can be invoked
176     * properly to take care of PLL and DDR3 initialization.
177     */
178    movw sp, #0x5e00
179    movt sp, #0x4030
180
181    /* Initialize the MPU, Core, DDR, and Per PLLs.  Furthermore,
182     * initialize the external DDR3 memory as well.
183     */
184dev_init:
185    bl pll_init
186    bl ddr_init
187
188    /* Reset the stack pointer for the SVC mode (our current mode) */
189    ldr sp, =(MonStack + MONSTACKSIZE - 4)
190
191    /*
192     * Restore argument which was saved to r11 and jump to
193     * the C function start().
194     */
195   
196    mov r0, r11
197jump_to_c:
198    bl start
199
200    /* the C code should never return */
201    b reset
202
203.align 4
204
205
206/*********************************************************************
207 * simple delay loop
208 */
209delay_200:
210        ldr             r3, =200                        /* loop count */
211delay_loop:
212        subs    r3,r3,#1
213        bne             delay_loop
214        nop
215
216        mov             pc, lr
217
218raise:  mov             pc, lr  /* to make linker happy */
219
220/*********************************************************************
221 * Cache initialization:
222 * Turn everything down and invalidate...
223 */
224cache_init:
225        /* Make sure caches are turned down...
226         */
227        mrc     p15, 0, r3, cr1, cr0, 0         // turn off I/D-cache
228        bic     r3, r3, #4096                           // I
229        bic     r3, r3, #4                                      // D
230        mcr     p15, 0, r3, cr1, cr0, 0
231       
232        mov     r0, #0
233//      mcr     p15, 0, r0, cr7, cr7, 0  // arm_cache_invalidate
234        mcr     p15, 0, r0, cr7, cr6, 0  // arm_dcache_invalidate
235        mcr     p15, 0, r0, cr7, cr5, 0  // arm_icache_invalidate
236
237        mrc     p15, 0, r0, cr1, cr0, 1  // l2cache_disable
238        bic     r0, r0, #2
239        mcr     p15, 0, r0, cr1, cr0, 1
240
241        mov     r0, #1
242        mrc     p15, 1, r0, cr0, cr0, 1  // emu_ext_boot_l2_inv
243        mov             pc, lr
244
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