source: umon/ports/beagleboneblack/rom_reset.S @ 35608bb

Last change on this file since 35608bb was 35608bb, checked in by Jarielle Catbagan <jcatbagan93@…>, on 06/20/15 at 02:58:01

Replaced omap3530.h with am335x.h in BBB port

am335x.h contains register base addresses and offsets specific to the AM335x found
on the BBB. The inclusion of this file replaces omap3530.h found in rom_reset.S
and ram_reset.S.
  • Property mode set to 100644
File size: 6.3 KB
Line 
1    .file "rom_reset.S"
2
3/*
4 * General notice:
5 * This code is part of a boot-monitor package developed as a generic base
6 * platform for embedded system designs.  As such, it is likely to be
7 * distributed to various projects beyond the control of the original
8 * author.  Please notify the author of any enhancements made or bugs found
9 * so that all may benefit from the changes.  In addition, notification back
10 * to the author will allow the new user to pick up changes that may have
11 * been made by other users after this version of the code was distributed.
12 *
13 * Author:  Ed Sutter
14 * email:   esutter@lucent.com
15 * phone:   908-582-2351
16 *
17 *
18 * Modified for the CSB740 - OMAP3530 Single Board
19 *
20 * rom_reset.s:
21  */
22
23#include "warmstart.h"
24#include "am335x.h"
25#include "config.h"
26
27    /*
28     * Have a separate stack for each processor mode.
29     */
30
31    /* define sizes for each mode's stack */
32    .equ FiqStackSz, 4096
33    .equ IrqStackSz, 4096
34    .equ AbtStackSz, 4096
35    .equ UndStackSz, 4096
36    .equ SysStackSz, 4096
37
38    /* declare the stacks */
39    .extern MonStack
40    .global FiqStack
41    .global IrqStack
42    .global AbtStack
43    .global UndStack
44    .global SysStack       
45    .global raise
46    .global cache_init
47   
48    /* allocate the stacks */
49    .comm   FiqStack, FiqStackSz    /* for the FIQ mode */
50    .comm   IrqStack, IrqStackSz    /* for the IRQ mode */
51    .comm   AbtStack, AbtStackSz    /* for the Abort mode */
52    .comm   UndStack, UndStackSz    /* for the Undef mode */
53    .comm   SysStack, SysStackSz    /* for the System mode */
54    /* User mode has the same stack as system mode. */
55
56/*********************************************************************/
57   
58    .extern start
59
60    .global reset
61    .global coldstart
62    .global lukewarmstart
63    .global warmstart
64
65    .text
66       
67    /*
68     * Exception table at address 0
69     */
70reset: 
71    b coldstart
72    b undefined_instruction
73    b software_interrupt
74    b abort_prefetch
75    b abort_data
76    b not_assigned
77    b interrupt_request
78    b fast_interrupt_request
79
80#include "etheraddr.S"
81#include "moncomptr.S"
82#include "alttfsdevtbl.S"
83
84coldstart:
85        ldr     pc, =coldstart_1                // jump to actual ROM location
86        nop
87
88coldstart_1:
89        /* Make sure interrupts are off, and we're in supervisor mode...
90         */
91        mrs     r0,cpsr                         // Retreive current program status register
92        bic     r0,r0,#0x1f                     // Clear all mode bits.
93        orr     r0,r0,#0xd3                     // Set mode to supervisor, IRQ FIQ disabled.
94        msr     cpsr,r0
95
96//      bl cache_init
97
98/********************************************************************/
99
100midstart:
101    ldr r0, =INITIALIZE
102   
103    /* fall-through to 'lukewarmstart' */
104
105/********************************************************************/
106   
107lukewarmstart: 
108    /* Save the argument to r11 */
109    mov r11, r0
110
111    /*
112     * *** DO NOT TOUCH R11 ***
113     */
114
115    /*
116     * Set-up the stack-pointers for all operating modes
117     */
118
119    /* FIQ mode */
120    mrs r0, cpsr                /* move CPSR to r0 */
121    bic r0, r0, #0x1f           /* clear all mode bits */
122    orr r0, r0, #0x11           /* set FIQ mode bits */
123    msr CPSR_c, r0              /* move back to CPSR */
124    ldr sp, =(FiqStack + FiqStackSz - 4)    /* initialize the stack ptr */
125    /* IRQ mode */
126    mrs r0, cpsr                /* move CPSR to r0 */
127    bic r0, r0, #0x1f           /* clear all mode bits */
128    orr r0, r0, #0x12           /* set IRQ mode bits */
129    msr CPSR_c, r0              /* move back to CPSR */
130    ldr sp, =(IrqStack + IrqStackSz - 4)    /* initialize the stack ptr */
131    /* Abort mode */
132    mrs r0, cpsr                /* move CPSR to r0 */
133    bic r0, r0, #0x1f           /* clear all mode bits */
134    orr r0, r0, #0x17           /* set Abort mode bits */
135    msr CPSR_c, r0              /* move back to CPSR */
136    ldr sp, =(AbtStack + AbtStackSz - 4)    /* initialize the stack ptr */
137    /* Undef mode */
138    mrs r0, cpsr                /* move CPSR to r0 */
139    bic r0, r0, #0x1f           /* clear all mode bits */
140    orr r0, r0, #0x1b           /* set Undef mode bits */
141    msr CPSR_c, r0              /* move back to CPSR */
142    ldr sp, =(UndStack + UndStackSz - 4)    /* initialize the stack ptr */
143    /* System mode */
144    mrs r0, cpsr                /* move CPSR to r0 */
145    bic r0, r0, #0x1f           /* clear all mode bits */
146    orr r0, r0, #0x1f           /* set System mode bits */
147    msr CPSR_c, r0              /* move back to CPSR */
148    ldr sp, =(SysStack + SysStackSz - 4)    /* initialize the stack ptr */
149    /* 'warmstart' will take us back to SVC mode
150       stack for SVC mode will also be setup in warmstart */
151
152    mov r0, r11     /* get argument back from r11 */
153    b   warmstart
154
155   
156/********************************************************************/
157   
158warmstart:
159    /* Save the argument to r11 */
160    mov r11, r0
161
162    /*
163     * *** DO NOT TOUCH R11 ***
164     */
165
166
167    /* Change (back) to SVC mode */
168    mrs r0, cpsr                /* move CPSR to r0 */
169    bic r0, r0, #0x1f           /* clear all mode bits */
170    orr r0, r0, #0x13           /* set System mode bits */
171    msr CPSR_c, r0              /* move back to CPSR */
172    /* Reset the stack pointer for the SVC mode (our current mode) */
173    ldr sp, =(MonStack + MONSTACKSIZE - 4)
174
175    /*
176     * Restore argument which was saved to r11 and jump to
177     * the C function start().
178     */
179   
180    mov r0, r11
181jump_to_c:
182    bl start
183
184    /* the C code should never return */
185    b reset
186
187.align 4
188
189
190/*********************************************************************
191 * simple delay loop
192 */
193delay_200:
194        ldr             r3, =200                        /* loop count */
195delay_loop:
196        subs    r3,r3,#1
197        bne             delay_loop
198        nop
199
200        mov             pc, lr
201
202raise:  mov             pc, lr  /* to make linker happy */
203
204/*********************************************************************
205 * Cache initialization:
206 * Turn everything down and invalidate...
207 */
208cache_init:
209        /* Make sure caches are turned down...
210         */
211        mrc     p15, 0, r3, cr1, cr0, 0         // turn off I/D-cache
212        bic     r3, r3, #4096                           // I
213        bic     r3, r3, #4                                      // D
214        mcr     p15, 0, r3, cr1, cr0, 0
215       
216        mov     r0, #0
217//      mcr     p15, 0, r0, cr7, cr7, 0  // arm_cache_invalidate
218        mcr     p15, 0, r0, cr7, cr6, 0  // arm_dcache_invalidate
219        mcr     p15, 0, r0, cr7, cr5, 0  // arm_icache_invalidate
220
221        mrc     p15, 0, r0, cr1, cr0, 1  // l2cache_disable
222        bic     r0, r0, #2
223        mcr     p15, 0, r0, cr1, cr0, 1
224
225        mov     r0, #1
226        mrc     p15, 1, r0, cr0, cr0, 1  // emu_ext_boot_l2_inv
227        mov             pc, lr
228
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