1 | .file "ram_reset.s" |
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2 | |
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3 | /* |
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4 | * General notice: |
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5 | * This code is part of a boot-monitor package developed as a generic base |
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6 | * platform for embedded system designs. As such, it is likely to be |
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7 | * distributed to various projects beyond the control of the original |
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8 | * author. Please notify the author of any enhancements made or bugs found |
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9 | * so that all may benefit from the changes. In addition, notification back |
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10 | * to the author will allow the new user to pick up changes that may have |
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11 | * been made by other users after this version of the code was distributed. |
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12 | * |
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13 | * Author: Ed Sutter |
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14 | * email: esutter@lucent.com |
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15 | * phone: 908-582-2351 |
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16 | * |
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17 | * |
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18 | * Modified for the CSB740 - OMAP3530 Single Board |
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19 | * |
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20 | * ram_reset.s: |
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21 | */ |
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22 | |
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23 | #include "warmstart.h" |
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24 | #include "omap3530.h" |
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25 | #include "config.h" |
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26 | |
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27 | /* |
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28 | * Have a separate stack for each processor mode. |
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29 | */ |
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30 | |
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31 | /* define sizes for each mode's stack */ |
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32 | .equ FiqStackSz, 4096 |
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33 | .equ IrqStackSz, 4096 |
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34 | .equ AbtStackSz, 4096 |
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35 | .equ UndStackSz, 4096 |
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36 | .equ SysStackSz, 4096 |
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37 | |
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38 | /* declare the stacks */ |
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39 | .extern MonStack |
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40 | .global FiqStack |
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41 | .global IrqStack |
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42 | .global AbtStack |
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43 | .global UndStack |
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44 | .global SysStack |
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45 | |
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46 | /* allocate the stacks */ |
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47 | .comm FiqStack, FiqStackSz /* for the FIQ mode */ |
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48 | .comm IrqStack, IrqStackSz /* for the IRQ mode */ |
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49 | .comm AbtStack, AbtStackSz /* for the Abort mode */ |
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50 | .comm UndStack, UndStackSz /* for the Undef mode */ |
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51 | .comm SysStack, SysStackSz /* for the System mode */ |
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52 | /* User mode has the same stack as system mode. */ |
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53 | |
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54 | /*********************************************************************/ |
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55 | |
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56 | .extern start |
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57 | |
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58 | .global reset |
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59 | .global coldstart |
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60 | .global lukewarmstart |
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61 | .global warmstart |
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62 | .global ipaddr |
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63 | .global etheraddr |
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64 | .global moncomptr |
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65 | |
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66 | .text |
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67 | |
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68 | /* |
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69 | * Exception table at address 0 |
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70 | */ |
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71 | reset: |
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72 | b coldstart |
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73 | b undefined_instruction |
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74 | b software_interrupt |
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75 | b abort_prefetch |
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76 | b abort_data |
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77 | b not_assigned |
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78 | b interrupt_request |
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79 | b fast_interrupt_request |
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80 | |
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81 | #include "etheraddr.S" |
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82 | #include "moncomptr.S" |
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83 | |
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84 | /*********************************************************************/ |
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85 | |
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86 | /* |
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87 | * At the end of the reset sequence, MMU, Icache, Dcache, |
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88 | * and write buffer are all disabled. |
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89 | * Also IRQs and FIQs are disabled in the processor's CPSR |
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90 | * The operating mode is SVC (supervisory mode), and the |
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91 | * PC is vectored at 0x00000000. A branch in 0x00000000 |
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92 | * brings us directly here. |
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93 | * |
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94 | */ |
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95 | |
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96 | coldstart: |
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97 | // ldr r0, =0x2001 /* allow access to all coprocessors */ |
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98 | // mcr p15,0,r0,c15,c1,0 |
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99 | // nop |
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100 | // nop |
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101 | // nop |
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102 | |
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103 | // ldr r0, =0x00000078 |
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104 | // mcr p15,0,r0,c1,c0,0 /* Disable MMU, caches, write buffer */ |
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105 | // nop |
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106 | // nop |
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107 | // nop |
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108 | |
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109 | // ldr r0, =0x00000000 |
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110 | // mcr p15,0,r0,c8,c7,0 /* flush TLB's */ |
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111 | // mcr p15,0,r0,c7,c7,0 /* flush Caches */ |
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112 | // mcr p15,0,r0,c7,c10,4 /* Flush Write Buffer */ |
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113 | // nop |
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114 | // nop |
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115 | // nop |
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116 | |
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117 | // mvn r0, #0 /* grant manager access to all domains */ |
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118 | // mcr p15,0,r0,c3,c0,0 |
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119 | |
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120 | /********************************************************************/ |
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121 | |
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122 | midstart: |
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123 | ldr r0, =INITIALIZE |
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124 | |
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125 | /* fall-through to 'lukewarmstart' */ |
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126 | |
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127 | /********************************************************************/ |
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128 | |
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129 | lukewarmstart: |
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130 | /* Save the argument to r11 */ |
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131 | mov r11, r0 |
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132 | |
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133 | /* |
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134 | * *** DO NOT TOUCH R11 *** |
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135 | */ |
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136 | |
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137 | /* |
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138 | * Set-up the stack-pointers for all operating modes |
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139 | */ |
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140 | |
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141 | /* FIQ mode */ |
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142 | mrs r0, cpsr /* move CPSR to r0 */ |
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143 | bic r0, r0, #0x1f /* clear all mode bits */ |
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144 | orr r0, r0, #0x11 /* set FIQ mode bits */ |
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145 | msr CPSR_c, r0 /* move back to CPSR */ |
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146 | ldr sp, =(FiqStack + FiqStackSz - 4) /* initialize the stack ptr */ |
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147 | /* IRQ mode */ |
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148 | mrs r0, cpsr /* move CPSR to r0 */ |
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149 | bic r0, r0, #0x1f /* clear all mode bits */ |
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150 | orr r0, r0, #0x12 /* set IRQ mode bits */ |
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151 | msr CPSR_c, r0 /* move back to CPSR */ |
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152 | ldr sp, =(IrqStack + IrqStackSz - 4) /* initialize the stack ptr */ |
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153 | /* Abort mode */ |
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154 | mrs r0, cpsr /* move CPSR to r0 */ |
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155 | bic r0, r0, #0x1f /* clear all mode bits */ |
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156 | orr r0, r0, #0x17 /* set Abort mode bits */ |
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157 | msr CPSR_c, r0 /* move back to CPSR */ |
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158 | ldr sp, =(AbtStack + AbtStackSz - 4) /* initialize the stack ptr */ |
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159 | /* Undef mode */ |
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160 | mrs r0, cpsr /* move CPSR to r0 */ |
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161 | bic r0, r0, #0x1f /* clear all mode bits */ |
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162 | orr r0, r0, #0x1b /* set Undef mode bits */ |
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163 | msr CPSR_c, r0 /* move back to CPSR */ |
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164 | ldr sp, =(UndStack + UndStackSz - 4) /* initialize the stack ptr */ |
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165 | /* System mode */ |
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166 | mrs r0, cpsr /* move CPSR to r0 */ |
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167 | bic r0, r0, #0x1f /* clear all mode bits */ |
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168 | orr r0, r0, #0x1f /* set System mode bits */ |
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169 | msr CPSR_c, r0 /* move back to CPSR */ |
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170 | ldr sp, =(SysStack + SysStackSz - 4) /* initialize the stack ptr */ |
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171 | /* 'warmstart' will take us back to SVC mode |
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172 | stack for SVC mode will also be setup in warmstart */ |
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173 | |
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174 | mov r0, r11 /* get argument back from r11 */ |
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175 | |
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176 | b warmstart |
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177 | |
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178 | |
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179 | /********************************************************************/ |
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180 | |
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181 | warmstart: |
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182 | /* Save the argument to r11 */ |
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183 | mov r11, r0 |
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184 | |
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185 | /* |
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186 | * *** DO NOT TOUCH R11 *** |
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187 | */ |
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188 | |
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189 | |
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190 | /* Change (back) to SVC mode */ |
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191 | mrs r0, cpsr /* move CPSR to r0 */ |
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192 | bic r0, r0, #0x1f /* clear all mode bits */ |
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193 | orr r0, r0, #0x13 /* set System mode bits */ |
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194 | msr CPSR_c, r0 /* move back to CPSR */ |
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195 | /* Reset the stack pointer for the SVC mode (our current mode) */ |
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196 | ldr sp, =(MonStack + MONSTACKSIZE - 4) |
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197 | |
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198 | /* |
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199 | * Restore argument which was saved to r11 and jump to |
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200 | * the C function start(). |
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201 | */ |
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202 | |
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203 | mov r0, r11 |
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204 | jump_to_c: |
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205 | bl start |
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206 | |
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207 | /* the C code should never return */ |
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208 | b reset |
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209 | |
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210 | .align 4 |
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211 | |
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