source: umon/ports/beagleboneblack/ram_reset.S @ 220ee4b

Last change on this file since 220ee4b was 35608bb, checked in by Jarielle Catbagan <jcatbagan93@…>, on 06/20/15 at 02:58:01

Replaced omap3530.h with am335x.h in BBB port

am335x.h contains register base addresses and offsets specific to the AM335x found
on the BBB. The inclusion of this file replaces omap3530.h found in rom_reset.S
and ram_reset.S.
  • Property mode set to 100644
File size: 5.9 KB
Line 
1    .file "ram_reset.s"
2
3/*
4 * General notice:
5 * This code is part of a boot-monitor package developed as a generic base
6 * platform for embedded system designs.  As such, it is likely to be
7 * distributed to various projects beyond the control of the original
8 * author.  Please notify the author of any enhancements made or bugs found
9 * so that all may benefit from the changes.  In addition, notification back
10 * to the author will allow the new user to pick up changes that may have
11 * been made by other users after this version of the code was distributed.
12 *
13 * Author:  Ed Sutter
14 * email:   esutter@lucent.com
15 * phone:   908-582-2351
16 *
17 *
18 * Modified for the CSB740 - OMAP3530 Single Board
19 *
20 * ram_reset.s:
21  */
22
23#include "warmstart.h"
24#include "am335x.h"
25#include "config.h"
26
27    /*
28     * Have a separate stack for each processor mode.
29     */
30
31    /* define sizes for each mode's stack */
32    .equ FiqStackSz, 4096
33    .equ IrqStackSz, 4096
34    .equ AbtStackSz, 4096
35    .equ UndStackSz, 4096
36    .equ SysStackSz, 4096
37
38    /* declare the stacks */
39    .extern MonStack
40    .global FiqStack
41    .global IrqStack
42    .global AbtStack
43    .global UndStack
44    .global SysStack       
45   
46    /* allocate the stacks */
47    .comm   FiqStack, FiqStackSz    /* for the FIQ mode */
48    .comm   IrqStack, IrqStackSz    /* for the IRQ mode */
49    .comm   AbtStack, AbtStackSz    /* for the Abort mode */
50    .comm   UndStack, UndStackSz    /* for the Undef mode */
51    .comm   SysStack, SysStackSz    /* for the System mode */
52    /* User mode has the same stack as system mode. */
53
54/*********************************************************************/
55   
56    .extern start
57
58    .global reset
59    .global coldstart
60    .global lukewarmstart
61    .global warmstart
62    .global ipaddr
63    .global etheraddr
64    .global moncomptr
65
66    .text
67       
68    /*
69     * Exception table at address 0
70     */
71reset: 
72    b coldstart
73    b undefined_instruction
74    b software_interrupt
75    b abort_prefetch
76    b abort_data
77    b not_assigned
78    b interrupt_request
79    b fast_interrupt_request
80
81#include "etheraddr.S"
82#include "moncomptr.S"
83
84/*********************************************************************/
85
86    /*
87     * At the end of the reset sequence, MMU, Icache, Dcache,
88     * and write buffer are all disabled.
89     * Also IRQs and FIQs are disabled in the processor's CPSR
90     * The operating mode is SVC (supervisory mode), and the
91     * PC is vectored at 0x00000000. A branch in 0x00000000
92     * brings us directly here.
93         *
94         */
95
96coldstart:
97//      ldr r0, =0x2001                                 /* allow access to all coprocessors */
98//      mcr     p15,0,r0,c15,c1,0
99//      nop
100//      nop
101//      nop
102
103//      ldr     r0, =0x00000078
104//      mcr     p15,0,r0,c1,c0,0                /* Disable MMU, caches, write buffer */
105//      nop
106//      nop
107//      nop
108
109//      ldr     r0, =0x00000000
110//      mcr     p15,0,r0,c8,c7,0                /* flush TLB's */
111//      mcr     p15,0,r0,c7,c7,0                /* flush Caches */
112//      mcr             p15,0,r0,c7,c10,4               /* Flush Write Buffer */
113//      nop
114//      nop
115//      nop
116
117//      mvn    r0, #0                   /* grant manager access to all domains */
118//      mcr    p15,0,r0,c3,c0,0 
119
120/********************************************************************/
121
122midstart:
123    ldr r0, =INITIALIZE
124   
125    /* fall-through to 'lukewarmstart' */
126
127/********************************************************************/
128   
129lukewarmstart: 
130    /* Save the argument to r11 */
131    mov r11, r0
132
133    /*
134     * *** DO NOT TOUCH R11 ***
135     */
136
137    /*
138     * Set-up the stack-pointers for all operating modes
139     */
140
141    /* FIQ mode */
142    mrs r0, cpsr                /* move CPSR to r0 */
143    bic r0, r0, #0x1f           /* clear all mode bits */
144    orr r0, r0, #0x11           /* set FIQ mode bits */
145    msr CPSR_c, r0              /* move back to CPSR */
146    ldr sp, =(FiqStack + FiqStackSz - 4)    /* initialize the stack ptr */
147    /* IRQ mode */
148    mrs r0, cpsr                /* move CPSR to r0 */
149    bic r0, r0, #0x1f           /* clear all mode bits */
150    orr r0, r0, #0x12           /* set IRQ mode bits */
151    msr CPSR_c, r0              /* move back to CPSR */
152    ldr sp, =(IrqStack + IrqStackSz - 4)    /* initialize the stack ptr */
153    /* Abort mode */
154    mrs r0, cpsr                /* move CPSR to r0 */
155    bic r0, r0, #0x1f           /* clear all mode bits */
156    orr r0, r0, #0x17           /* set Abort mode bits */
157    msr CPSR_c, r0              /* move back to CPSR */
158    ldr sp, =(AbtStack + AbtStackSz - 4)    /* initialize the stack ptr */
159    /* Undef mode */
160    mrs r0, cpsr                /* move CPSR to r0 */
161    bic r0, r0, #0x1f           /* clear all mode bits */
162    orr r0, r0, #0x1b           /* set Undef mode bits */
163    msr CPSR_c, r0              /* move back to CPSR */
164    ldr sp, =(UndStack + UndStackSz - 4)    /* initialize the stack ptr */
165    /* System mode */
166    mrs r0, cpsr                /* move CPSR to r0 */
167    bic r0, r0, #0x1f           /* clear all mode bits */
168    orr r0, r0, #0x1f           /* set System mode bits */
169    msr CPSR_c, r0              /* move back to CPSR */
170    ldr sp, =(SysStack + SysStackSz - 4)    /* initialize the stack ptr */
171    /* 'warmstart' will take us back to SVC mode
172       stack for SVC mode will also be setup in warmstart */
173
174    mov r0, r11     /* get argument back from r11 */
175
176    b   warmstart
177
178   
179/********************************************************************/
180
181warmstart:
182    /* Save the argument to r11 */
183    mov r11, r0
184
185    /*
186     * *** DO NOT TOUCH R11 ***
187     */
188
189
190    /* Change (back) to SVC mode */
191    mrs r0, cpsr                /* move CPSR to r0 */
192    bic r0, r0, #0x1f           /* clear all mode bits */
193    orr r0, r0, #0x13           /* set System mode bits */
194    msr CPSR_c, r0              /* move back to CPSR */
195    /* Reset the stack pointer for the SVC mode (our current mode) */
196    ldr sp, =(MonStack + MONSTACKSIZE - 4)
197
198    /*
199     * Restore argument which was saved to r11 and jump to
200     * the C function start().
201     */
202   
203    mov r0, r11
204jump_to_c:
205    bl start
206
207    /* the C code should never return */
208    b reset
209
210.align 4
211
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