1 | //mx31_iomux.c |
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2 | |
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3 | #include "config.h" |
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4 | #include "cpuio.h" |
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5 | #include "stddefs.h" |
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6 | #include "genlib.h" |
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7 | #include "omap3530.h" |
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8 | #include "omap3530_iomux.h" |
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9 | #include "cpu_gpio.h" // pull in target board specific header |
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10 | |
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11 | void iomux_init() |
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12 | { |
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13 | |
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14 | // Initialization of GPR for CSB733 |
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15 | IOMUX_CTL_REG(GENERAL_REGISTER) = WEIM_ON_CS3_EN | CSPI1_ON_UART_EN; |
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16 | |
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17 | // MX31_PIN_TTM_PAD = can not be written to. |
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18 | // cspi_miso = U2_RXD, cspi3_sclk = U2_RTS, cspi3_spi_rdy = U2_CTS, ttm_pad = default |
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19 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER1) = MX31_PIN_CSPI3_MISO((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)) |
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20 | | MX31_PIN_CSPI3_SCLK((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)) |
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21 | | MX31_PIN_CSPI3_SPI_RDY((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)); |
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22 | // | MX31_PIN_TTM_PAD(); |
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23 | |
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24 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER1) = MX31_PIN_CSPI3_MISO(0x20) |
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25 | // | MX31_PIN_CSPI3_SCLK(0x20) |
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26 | // | MX31_PIN_CSPI3_SPI_RDY(0x20); |
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27 | //// | MX31_PIN_TTM_PAD(); |
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28 | |
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29 | // MX31_PIN_CLKSS and MX31_PIN_CE_CONTROL = can not be written to. |
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30 | // reset_b = NC, ce_control = default, ctl_clkss = default, cspi3_mosi = U2_RXD |
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31 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER2) = MX31_PIN_ATA_RESET_B((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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32 | | MX31_PIN_CE_CONTROL((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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33 | // | MX31_PIN_CLKSS() |
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34 | | MX31_PIN_CSPI3_MOSI((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1)); |
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35 | |
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36 | // ata_cs1 = NC, ata_dior = D_TXD, ata_diow = NC, ata, dmack = NC |
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37 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER3) = MX31_PIN_ATA_CS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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38 | | MX31_PIN_ATA_DIOR((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)) |
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39 | | MX31_PIN_ATA_DIOW((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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40 | | MX31_PIN_ATA_DMACK((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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41 | |
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42 | // sd1_data1 = SD_D1, sd1_data2 = SD_D2, sd1_data3 = SD_D3, ata_cs0 = D_RXD |
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43 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER4) = MX31_PIN_SD1_DATA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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44 | | MX31_PIN_SD1_DATA2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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45 | | MX31_PIN_SD1_DATA3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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46 | | MX31_PIN_ATA_CS0((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1)); |
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47 | |
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48 | // d3_spl = NC, sd1_cmd = SD_CMD, sd1_clk - SD_CLK, sd1_data0 = SD_D0 |
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49 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER5) = MX31_PIN_D3_SPL((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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50 | | MX31_PIN_SD1_CMD((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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51 | | MX31_PIN_SD1_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)) |
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52 | | MX31_PIN_SD1_DATA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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53 | |
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54 | // vsync3 = LCD_VSYNC, contrast = NC, d3_rev = NC, d3_cls = NC |
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55 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER6) = MX31_PIN_VSYNC3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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56 | | MX31_PIN_CONTRAST((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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57 | | MX31_PIN_D3_REV((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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58 | | MX31_PIN_D3_CLS((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)); |
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59 | |
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60 | // ser_rs = NC, par_rs = NC, write = NC, read = NC |
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61 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER7) = MX31_PIN_SER_RS((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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62 | | MX31_PIN_PAR_RS((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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63 | | MX31_PIN_WRITE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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64 | | MX31_PIN_READ((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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65 | |
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66 | // sd_d_io = NC, sd_d_clk = NC, lcs0 = NC, lcs1 = NC |
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67 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER8) = MX31_PIN_SD_D_IO((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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68 | | MX31_PIN_SD_D_CLK((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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69 | | MX31_PIN_LCS0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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70 | | MX31_PIN_LCS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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71 | |
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72 | // hsync = LCD_HSYNC, fpshift = LCD_PCLK, drdy0 = LCD_OE, sd_d_i = NC |
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73 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER9) = MX31_PIN_HSYNC((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)) |
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74 | | MX31_PIN_FPSHIFT((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)) |
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75 | | MX31_PIN_DRDY0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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76 | | MX31_PIN_SD_D_I((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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77 | |
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78 | // ld15 = LCD_R3, ld16 = LCD_R4, ld17 = LCD_R5, sd_d_i = NC |
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79 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER10) = MX31_PIN_LD15((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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80 | | MX31_PIN_LD16((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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81 | | MX31_PIN_LD17((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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82 | | MX31_PIN_VSYNC0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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83 | |
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84 | // ld11 = LCD_G5, ld12 = LCD_R0, ld13 = LCD_R1, ld14 = LCD_R2 |
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85 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER11) = MX31_PIN_LD11((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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86 | | MX31_PIN_LD12((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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87 | | MX31_PIN_LD13((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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88 | | MX31_PIN_LD14((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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89 | |
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90 | // ld7 = LCD_G1, ld8 = LCD_G2, ld9 = LCD_G3, ld10 = LCD_G4 |
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91 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER12) = MX31_PIN_LD7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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92 | | MX31_PIN_LD8((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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93 | | MX31_PIN_LD9((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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94 | | MX31_PIN_LD10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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95 | |
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96 | // ld3 = LCD_B3, ld4 = LCD_B4, ld5 = LCD_B5, ld6 = LCD_G0 |
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97 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER13) = MX31_PIN_LD3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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98 | | MX31_PIN_LD4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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99 | | MX31_PIN_LD5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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100 | | MX31_PIN_LD6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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101 | |
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102 | // usbh2_data1 = UH2_D1, ld0 = LCD_B0, ld1 = LCD_B1, ld2 = LCD_B0 |
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103 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER14) = MX31_PIN_USBH2_DATA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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104 | | MX31_PIN_LD0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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105 | | MX31_PIN_LD1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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106 | | MX31_PIN_LD2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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107 | |
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108 | // usbh2_dir = UH2_DIR, usbh2_stp = UH2_STP, usbh2_nxt = UH2_NXT, usbh2_data0 = UH2_D0 |
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109 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER15) = MX31_PIN_USBH2_DIR((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)) |
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110 | | MX31_PIN_USBH2_STP((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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111 | | MX31_PIN_USBH2_NXT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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112 | | MX31_PIN_USBH2_DATA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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113 | |
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114 | // usbotg_data5 = UD_D5, usbotg_data6 = UD_D6, usbotg_data7 = UD_D7, usbh2_clk = UH2_CLK |
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115 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER16) = MX31_PIN_USBOTG_DATA5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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116 | | MX31_PIN_USBOTG_DATA6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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117 | | MX31_PIN_USBOTG_DATA7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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118 | | MX31_PIN_USBH2_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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119 | |
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120 | // usbotg_data1 = UD_D1, usbotg_data2 = UD_D2, usbotg_data3 = UD_D3, usbotg_data4 = UD_D4 |
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121 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER17) = MX31_PIN_USBOTG_DATA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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122 | | MX31_PIN_USBOTG_DATA2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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123 | | MX31_PIN_USBOTG_DATA3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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124 | | MX31_PIN_USBOTG_DATA4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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125 | |
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126 | // usbotg_dir = UD_DIR, usbotg_stp = UD_STP, usbotg_nxt = UD_NXT, usbotg_data0 = UD_D0 |
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127 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER18) = MX31_PIN_USBOTG_DIR((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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128 | | MX31_PIN_USBOTG_STP((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)) |
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129 | | MX31_PIN_USBOTG_NXT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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130 | | MX31_PIN_USBOTG_DATA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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131 | |
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132 | // usb_pwr = NC, usb_oc = CF_RST, usb_byp = NC, usbotg_clk = UD_CLK |
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133 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER19) = MX31_PIN_USB_PWR((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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134 | | MX31_PIN_USB_OC((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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135 | | MX31_PIN_USB_BYP((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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136 | | MX31_PIN_USBOTG_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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137 | |
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138 | // MX31_PIN_TDO and MX31_PIN_SJC_MOD = can not be written to |
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139 | // tdo = TDO_C, trstb = TRST_C, de_b = TP1, sjc_mod = GND |
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140 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER20) = MX31_PIN_TDO() |
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141 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER20) = MX31_PIN_TRSTB((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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142 | | MX31_PIN_DE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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143 | // | MX31_PIN_SJC_MOD(); |
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144 | |
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145 | // MX31_PIN_RTCK = can not be written to. |
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146 | // rtck = NC, tck = TCK_C, tms = TMS_C, tdi = TDI_C |
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147 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER21) = MX31_PIN_RTCK() |
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148 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER21) = MX31_PIN_TCK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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149 | | MX31_PIN_TMS((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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150 | | MX31_PIN_TDI((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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151 | |
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152 | // key_col4 = NC, key_col5 = NC, key_col6 = NC, key_col7 = NC |
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153 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER22) = MX31_PIN_KEY_COL4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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154 | | MX31_PIN_KEY_COL5((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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155 | | MX31_PIN_KEY_COL6((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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156 | | MX31_PIN_KEY_COL7((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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157 | |
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158 | // key_col0 = NC, key_col1 = NC, key_col2 = NC, key_col3 = NC |
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159 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER23) = MX31_PIN_KEY_COL0((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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160 | | MX31_PIN_KEY_COL1((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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161 | | MX31_PIN_KEY_COL2((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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162 | | MX31_PIN_KEY_COL3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)); |
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163 | |
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164 | // key_row4 = NC, key_row5 = NC, key_row6 = NC, key_row7 = NC |
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165 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER24) = MX31_PIN_KEY_ROW4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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166 | | MX31_PIN_KEY_ROW5((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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167 | | MX31_PIN_KEY_ROW6((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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168 | | MX31_PIN_KEY_ROW7((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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169 | |
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170 | // key_row0 = NC, key_row1 = NC, key_row2 = NC, key_row3 = NC |
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171 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER25) = MX31_PIN_KEY_ROW0((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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172 | | MX31_PIN_KEY_ROW1((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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173 | | MX31_PIN_KEY_ROW2((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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174 | | MX31_PIN_KEY_ROW3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)); |
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175 | |
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176 | // txd2 = U1_TXD, rts2 = U1_RTS, cts2 = U1_CTS, batt_line = NC |
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177 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER26) = MX31_PIN_TXD2((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)) |
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178 | | MX31_PIN_RTS2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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179 | | MX31_PIN_CTS2((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)) |
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180 | | MX31_PIN_BATT_LINE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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181 | |
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182 | // ri_dte1, dcd_dte1, and dtr_dce2 are set to CSPI1 signals by GPR(2) |
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183 | // rxd2 = U1_RXD |
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184 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER27) = MX31_PIN_RI_DTE1() |
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185 | // | MX31_PIN_DCD_DTE1() |
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186 | // | MX31_PIN_DTR_DCE2() |
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187 | // | MX31_PIN_RXD2(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC); |
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188 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER27) = MX31_PIN_RXD2((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC)); |
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189 | |
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190 | // dtr_dte1 and dsr_dte1 are set to CSPI1 signals by GPR(2) |
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191 | // ri_dce1 = SPI0_RDY, dcd_dce1 = NC |
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192 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER28) = MX31_PIN_RI_DCE1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)) |
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193 | | MX31_PIN_DCD_DCE1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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194 | // | MX31_PIN_DTR_DTE1() |
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195 | // | MX31_PIN_DSR_DTE1(); |
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196 | |
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197 | // rts1 = U0_RTS, cts1 = U0_CTS, dtr_dce1 = NC, dsr_dce1 = SPI0_CLK |
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198 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER29) = MX31_PIN_RTS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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199 | | MX31_PIN_CTS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)) |
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200 | | MX31_PIN_DTR_DCE1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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201 | | MX31_PIN_DSR_DCE1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)); |
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202 | |
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203 | // cspi2_sclk = SPI1_CLK, cspi2_spi_rdy = SPI1_RDY, rxd1 = U0_RXD, txd1 = U0_TXD |
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204 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER30) = MX31_PIN_CSPI2_SCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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205 | | MX31_PIN_CSPI2_SPI_RDY((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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206 | | MX31_PIN_RXD1((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC)) |
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207 | | MX31_PIN_TXD1((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)); |
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208 | |
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209 | // cspi2_miso = SPI1_MISO, cspi2_ss0 = SPI1_CS0, cspi2_ss1 = SPI1_CS1, cspi2_ss2 = NC |
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210 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER31) = MX31_PIN_CSPI2_MISO((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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211 | | MX31_PIN_CSPI2_SS0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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212 | | MX31_PIN_CSPI2_SS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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213 | | MX31_PIN_CSPI2_SS2((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)); |
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214 | |
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215 | // cspi1_ss2 = UH1_RCV, cspi1_sclk = UH1_OE, cspi1_spi_rdy = UH1_FS, cspi2_mosi = SPI1_MOSI |
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216 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER32) = MX31_PIN_CSPI1_SS2((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)) |
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217 | | MX31_PIN_CSPI1_SCLK((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)) |
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218 | | MX31_PIN_CSPI1_SPI_RDY((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)) |
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219 | | MX31_PIN_CSPI2_MOSI((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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220 | |
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221 | // cspi1_mosi = UH1_RXDM, cspi1_miso = UH1_RXDP, cspi1_ss0 = UH1_TXDM, cspi1_ss1 = UH1_TXDP |
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222 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER33) = MX31_PIN_CSPI1_MOSI((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1)) |
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223 | | MX31_PIN_CSPI1_MISO((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1)) |
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224 | | MX31_PIN_CSPI1_SS0((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)) |
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225 | | MX31_PIN_CSPI1_SS1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)); |
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226 | |
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227 | // stxd6 = AC_SDOUT, srxd6 = AC_SDIN, sck6 = AC_BCLK, sfs6 = AC_SYNC |
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228 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER34) = MX31_PIN_STXD6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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229 | | MX31_PIN_SRXD6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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230 | | MX31_PIN_SCK6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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231 | | MX31_PIN_SFS6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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232 | |
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233 | // stxd5 = SSI_TXD, srxd5 = SSI_RXD, sck5 = SSI_CLK, sfs5 = SSI_FRM |
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234 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER35) = MX31_PIN_STXD5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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235 | | MX31_PIN_SRXD5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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236 | | MX31_PIN_SCK5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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237 | | MX31_PIN_SFS5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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238 | |
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239 | // stxd4 = NC, srxd4 = NC, sck4 = SSI_MCLK, sfs4 = NC |
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240 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER36) = MX31_PIN_STXD4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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241 | | MX31_PIN_SRXD4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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242 | | MX31_PIN_SCK4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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243 | | MX31_PIN_SFS4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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244 | |
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245 | // stxd3 = AC_RST, srxd3 = NC, sck3 = NC, sfs3 = NC |
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246 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER37) = MX31_PIN_STXD3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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247 | | MX31_PIN_SRXD3((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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248 | | MX31_PIN_SCK3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
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249 | | MX31_PIN_SFS3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)); |
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250 | |
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251 | // csi_hsync = VIP_HSYNC, csi_pixclk = VIP_PCLK, i2c_clk = I2C_SCL, i2c_dat = I2C_SDA |
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252 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER38) = MX31_PIN_CSI_HSYNC((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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253 | | MX31_PIN_CSI_PIXCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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254 | | MX31_PIN_I2C_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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255 | | MX31_PIN_I2C_DAT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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256 | |
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257 | // csi_d14 = VIP_D8, csi_d15 = VIP_D9, csi_mclk = VIP_MCLK, csi_vsync = VIP_VSYNC |
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258 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER39) = MX31_PIN_CSI_D14((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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259 | | MX31_PIN_CSI_D15((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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260 | | MX31_PIN_CSI_MCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)) |
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261 | | MX31_PIN_CSI_VSYNC((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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262 | |
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263 | // csi_d10 = VIP_D4, csi_d11 = VIP_D5, csi_D12 = VIP_D6, csi_D13 = VIP_D7 |
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264 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER40) = MX31_PIN_CSI_D10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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265 | | MX31_PIN_CSI_D11((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
266 | | MX31_PIN_CSI_D12((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
267 | | MX31_PIN_CSI_D13((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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268 | |
---|
269 | // csi_d6 = VIP_D0, csi_d7 = VIP_D1, csi_D8 = VIP_D2, csi_D9 = VIP_D3 |
---|
270 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER41) = MX31_PIN_CSI_D6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
271 | | MX31_PIN_CSI_D7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
272 | | MX31_PIN_CSI_D8((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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273 | | MX31_PIN_CSI_D9((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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274 | |
---|
275 | // m_request = NC, m_grant = NC, csi_d4 = NC, csi_d5 = NC |
---|
276 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER42) = MX31_PIN_M_REQUEST((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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277 | | MX31_PIN_M_GRANT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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278 | | MX31_PIN_CSI_D4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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279 | | MX31_PIN_CSI_D5((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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280 | |
---|
281 | // pc_rst = UH2_D5, isis16 = UH2_D6, pc_rw_b = UH2_D7, pc_poe = NC |
---|
282 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER43) = MX31_PIN_PC_RST((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)) |
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283 | | MX31_PIN_IOIS16((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)) |
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284 | | MX31_PIN_PC_RW_B((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)) |
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285 | | MX31_PIN_PC_POE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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286 | |
---|
287 | // pc_vs1 = NC, pc_vs2 = UH2_D2, pc_bvd1 = UH2_D3, pc_bvd2 = UH2_D4 |
---|
288 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER44) = MX31_PIN_PC_VS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
289 | | MX31_PIN_PC_VS2((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)) |
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290 | | MX31_PIN_PC_BVD1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)) |
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291 | | MX31_PIN_PC_BVD2((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)); |
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292 | |
---|
293 | // pc_cd2_b = CF_CD, pc_wait_b = CF_WAIT, pc_ready = CF_RDY, pc_pwron = NC |
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294 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER45) = MX31_PIN_PC_CD2_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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295 | | MX31_PIN_PC_WAIT_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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296 | | MX31_PIN_PC_READY((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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297 | | MX31_PIN_PC_PWRON((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
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298 | |
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299 | // d2, d1, and d0 are not writable, reset values are correct. |
---|
300 | // d2 = LD2, d1 = LD1, d0 = LD0, pc_cd1_b = CF_CD |
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301 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER46) = MX31_PIN_D2() |
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302 | // | MX31_PIN_D1() |
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303 | // | MX31_PIN_D0() |
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304 | // | MX31_PIN_PC_CD1_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC); |
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305 | |
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306 | // d6, d5, d4 and d3 are not writable, reset values are correct. |
---|
307 | // d6 = LD6, d5 = LD5, d4 = LD4, d3 = LD3 |
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308 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER47) = MX31_PIN_D6() |
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309 | // | MX31_PIN_D5() |
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310 | // | MX31_PIN_D4() |
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311 | // | MX31_PIN_D3(); |
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312 | |
---|
313 | // d10, d9, d8 and d7 are not writable, reset values are correct. |
---|
314 | // d10 = LD10, d9 = LD9, d8 = LD8, d7 = LD7 |
---|
315 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER48) = MX31_PIN_D10() |
---|
316 | // | MX31_PIN_D9() |
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317 | // | MX31_PIN_D8() |
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318 | // | MX31_PIN_D7(); |
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319 | |
---|
320 | // d14, d13, d12 and d11 are not writable, reset values are correct. |
---|
321 | // d14 = LD14, d13 = LD13, d12 = LD12, d11 = L11 |
---|
322 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER49) = MX31_PIN_D14() |
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323 | // | MX31_PIN_D13() |
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324 | // | MX31_PIN_D12() |
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325 | // | MX31_PIN_D11(); |
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326 | |
---|
327 | // d15 is not writable, reset value is correct. |
---|
328 | // nfwp_b = *N_WP, nfce_b = *N_CE, nfrb = N_RDY, d15 = LD15 |
---|
329 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER50) = MX31_PIN_NFWP_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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330 | | MX31_PIN_NFCE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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331 | | MX31_PIN_NFRB((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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332 | // | MX31_PIN_D15(); |
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333 | |
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334 | // nfwe_b = *N_WE, nfre_b = *N_RE, nfale = N_ALE, nfcle = N_CLE |
---|
335 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER51) = MX31_PIN_NFWE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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336 | | MX31_PIN_NFRE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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337 | | MX31_PIN_NFALE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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338 | | MX31_PIN_NFCLE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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339 | |
---|
340 | // sdqs0, sdqs1, sdqs2, and sdqs3 are not writable, reset values are correct. |
---|
341 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER52) = MX31_PIN_SDQS0() |
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342 | // | MX31_PIN_SDQS1() |
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343 | // | MX31_PIN_SDQS2() |
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344 | // | MX31_PIN_SDQS3(); |
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345 | |
---|
346 | // sdclk_b is not writable, reset value is correct. |
---|
347 | // sdcke0 = SDCKE, sdcke1 = NC, sdclk = SDCLK, sdclk_b = *SDCLK |
---|
348 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER53) = MX31_PIN_SDCKE0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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349 | | MX31_PIN_SDCKE1((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC)) |
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350 | | MX31_PIN_SDCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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351 | // | MX31_PIN_SDCLK_B(); |
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352 | |
---|
353 | // rw = *WE, ras = *SDRAS, cas = *SDCAS, sdwe = *SDWE |
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354 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER54) = MX31_PIN_RW((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
355 | | MX31_PIN_RAS((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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356 | | MX31_PIN_CAS((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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357 | | MX31_PIN_SDWE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
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358 | |
---|
359 | // ecb is not writable, reset value is correct. |
---|
360 | // cs5 = *CS5, ecb = ECB, lba = LBA, bclk = NC |
---|
361 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER55) = MX31_PIN_CS5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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362 | // | MX31_PIN_ECB() |
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363 | | MX31_PIN_LBA((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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364 | | MX31_PIN_BCLK((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
---|
365 | |
---|
366 | // cs1 = *CS1, cs2 = *SDCS, cs3 = NC, cs4 = *DTACK |
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367 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER56) = MX31_PIN_CS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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368 | | MX31_PIN_CS2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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369 | | MX31_PIN_CS3((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
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370 | | MX31_PIN_CS4((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)); |
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371 | |
---|
372 | // eb0 = *BE0, eb1 = *BE1, oe = *OE, cs0 = *CS0 |
---|
373 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER57) = MX31_PIN_EB0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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374 | | MX31_PIN_EB1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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375 | | MX31_PIN_OE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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376 | | MX31_PIN_CS0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
377 | |
---|
378 | // dqm0 = DQM0, dqm1 = DQM1, dqm2 = DQM2, dqm3 = DQM3 |
---|
379 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER58) = MX31_PIN_DQM0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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380 | | MX31_PIN_DQM1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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381 | | MX31_PIN_DQM2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
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382 | | MX31_PIN_DQM3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
383 | |
---|
384 | // sd28, sd29, sd30 and sd31 are not writable, reset values are correct. |
---|
385 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER59) = MX31_PIN_SD28() |
---|
386 | // | MX31_PIN_SD29() |
---|
387 | // | MX31_PIN_SD30() |
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388 | // | MX31_PIN_SD31(); |
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389 | |
---|
390 | // sd24, sd25, sd26 and sd27 are not writable, reset values are correct. |
---|
391 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER60) = MX31_PIN_SD24() |
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392 | // | MX31_PIN_SD25() |
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393 | // | MX31_PIN_SD26() |
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394 | // | MX31_PIN_SD27(); |
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395 | |
---|
396 | // sd20, sd21, sd22 and sd23 are not writable, reset values are correct. |
---|
397 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER61) = MX31_PIN_SD20() |
---|
398 | // | MX31_PIN_SD21() |
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399 | // | MX31_PIN_SD22() |
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400 | // | MX31_PIN_SD23(); |
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401 | |
---|
402 | // sd16, sd17, sd18 and sd19 are not writable, reset values are correct. |
---|
403 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER62) = MX31_PIN_SD16() |
---|
404 | // | MX31_PIN_SD17() |
---|
405 | // | MX31_PIN_SD18() |
---|
406 | // | MX31_PIN_SD19(); |
---|
407 | |
---|
408 | // sd12, sd13, sd14 and sd15 are not writable, reset values are correct. |
---|
409 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER63) = MX31_PIN_SD12() |
---|
410 | // | MX31_PIN_SD13() |
---|
411 | // | MX31_PIN_SD14() |
---|
412 | // | MX31_PIN_SD15(); |
---|
413 | |
---|
414 | // sd8, sd9, sd10 and sd11 are not writable, reset values are correct. |
---|
415 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER64) = MX31_PIN_SD8() |
---|
416 | // | MX31_PIN_SD9() |
---|
417 | // | MX31_PIN_SD10() |
---|
418 | // | MX31_PIN_SD11(); |
---|
419 | |
---|
420 | // sd4, sd5, sd6 and sd7 are not writable, reset values are correct. |
---|
421 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER65) = MX31_PIN_SD4() |
---|
422 | // | MX31_PIN_SD5() |
---|
423 | // | MX31_PIN_SD6() |
---|
424 | // | MX31_PIN_SD7(); |
---|
425 | |
---|
426 | // sd0, sd1, sd2 and sd3 are not writable, reset values are correct. |
---|
427 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER66) = MX31_PIN_SD0() |
---|
428 | // | MX31_PIN_SD1() |
---|
429 | // | MX31_PIN_SD2() |
---|
430 | // | MX31_PIN_SD3(); |
---|
431 | |
---|
432 | // a24 = A24, a25 = A25, sdba1 = SDBA1, sdba0 = SDBA0 |
---|
433 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER67) = MX31_PIN_A24((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
434 | | MX31_PIN_A25((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
435 | | MX31_PIN_SDBA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
436 | | MX31_PIN_SDBA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
437 | |
---|
438 | // address lines are one to one. |
---|
439 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER68) = MX31_PIN_A20((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
440 | | MX31_PIN_A21((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
441 | | MX31_PIN_A22((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
442 | | MX31_PIN_A23((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
443 | |
---|
444 | // address lines are one to one. |
---|
445 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER69) = MX31_PIN_A16((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
446 | | MX31_PIN_A17((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
447 | | MX31_PIN_A18((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
448 | | MX31_PIN_A19((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
449 | |
---|
450 | // address lines are one to one. |
---|
451 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER70) = MX31_PIN_A12((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
452 | | MX31_PIN_A13((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
453 | | MX31_PIN_A14((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
454 | | MX31_PIN_A15((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
455 | |
---|
456 | // address lines are one to one. |
---|
457 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER71) = MX31_PIN_A9((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
458 | | MX31_PIN_A10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
459 | | MX31_PIN_MA10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
460 | | MX31_PIN_A11((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
461 | |
---|
462 | // address lines are one to one. |
---|
463 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER72) = MX31_PIN_A5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
464 | | MX31_PIN_A6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
465 | | MX31_PIN_A7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
466 | | MX31_PIN_A8((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
467 | |
---|
468 | // address lines are one to one. |
---|
469 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER73) = MX31_PIN_A1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
470 | | MX31_PIN_A2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
471 | | MX31_PIN_A3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)) |
---|
472 | | MX31_PIN_A4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
473 | |
---|
474 | // dvfs1 = NC, vpg0 = NC, vpg1 = NC, a0 = A0 |
---|
475 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER74) = MX31_PIN_DVFS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
476 | | MX31_PIN_VPG0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
477 | | MX31_PIN_VPG1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
478 | | MX31_PIN_A0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
479 | |
---|
480 | // ckil and power_fail are not writable, reset values are correct. |
---|
481 | //ckil = 32K, power_fail = PWR_FAIL, vstby = VSTBY, dvfs0 = NC |
---|
482 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER75) = MX31_PIN_CKIL() |
---|
483 | // | MX31_PIN_POWER_FAIL() |
---|
484 | // | MX31_PIN_VSTBY(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC) |
---|
485 | // | MX31_PIN_DVFS0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO); |
---|
486 | |
---|
487 | // boot_mode1, boot_mode2, boot_mode3, and boot_mode4 are not writable, reset values are correct. |
---|
488 | //IOMUX_CTL_REG(SW_MUX_CTL_REGISTER76) = MX31_PIN_BOOT_MODE1() |
---|
489 | // | MX31_PIN_BOOT_MODE2() |
---|
490 | // | MX31_PIN_BOOT_MODE3() |
---|
491 | // | MX31_PIN_BOOT_MODE4(); |
---|
492 | |
---|
493 | // por_b, clko, and boot_mode0 are not writable, reset values are correct. |
---|
494 | // reset_in_b = *RST_IN (this is set in the GPR) |
---|
495 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER77) = MX31_PIN_RESET_IN_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)); |
---|
496 | // | MX31_PIN_POR_B() |
---|
497 | // | MX31_PIN_CLKO() |
---|
498 | // | MX31_PIN_BOOT_MODE0(); |
---|
499 | |
---|
500 | // ckih is not writable, reset value is correct. |
---|
501 | // stx0 = GPIO1, srx0 = GPIO4, simpd0 = GPIO5 |
---|
502 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER78) = MX31_PIN_STX0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
503 | | MX31_PIN_SRX0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
504 | | MX31_PIN_SIMPD0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
---|
505 | // | MX31_PIN_CKIH(); |
---|
506 | |
---|
507 | // gpio3_1 = VF_EN, sclk0 = GPIO8, srst0 = GPIO9, sven0 = GPIO0 (USR_LED) |
---|
508 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER79) = MX31_PIN_GPIO3_1((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)) |
---|
509 | | MX31_PIN_SCLK0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
510 | | MX31_PIN_SRST0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
511 | | MX31_PIN_SVEN0((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)); |
---|
512 | |
---|
513 | // gpio1_4 = UH1_SUSP, gpio1_5 = PWR_RDY, gpio1_6 = UH1_MODE, gpio3_0 = NC |
---|
514 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER80) = MX31_PIN_GPIO1_4((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)) |
---|
515 | | MX31_PIN_GPIO1_5((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC)) |
---|
516 | | MX31_PIN_GPIO1_6((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
517 | | MX31_PIN_GPIO3_0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
---|
518 | |
---|
519 | // gpio1_0 = *PIRQ, gpio1_1 = *E_INT, gpio1_2 = *EXP_INT, gpio1_3 = *I2C_INT |
---|
520 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER81) = MX31_PIN_GPIO1_0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
521 | | MX31_PIN_GPIO1_1((OUTPUTCONFIG_FUNC | INPUTCONFIG_GPIO)) |
---|
522 | | MX31_PIN_GPIO1_2((OUTPUTCONFIG_FUNC | INPUTCONFIG_GPIO)) |
---|
523 | | MX31_PIN_GPIO1_3((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)); |
---|
524 | |
---|
525 | // capture = GPIO2, compare = GPIO3, watchdog_rst = NC, pwm0 = LCD_BKL |
---|
526 | IOMUX_CTL_REG(SW_MUX_CTL_REGISTER82) = MX31_PIN_CAPTURE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
527 | | MX31_PIN_COMPARE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
528 | | MX31_PIN_WATCHDOG_RST((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)) |
---|
529 | | MX31_PIN_PWMO((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)); |
---|
530 | } |
---|