source: umon/ports/beagleboneblack/cpuio.c @ d77ed25

Last change on this file since d77ed25 was d77ed25, checked in by Jarielle Catbagan <jcatbagan93@…>, on Jul 3, 2015 at 5:54:50 PM

BBB: cpuio.*: Add UART0 initialization and set DEFAULT_BAUD_RATE to 115200

  • Property mode set to 100644
File size: 4.1 KB
Line 
1#include "config.h"
2#include "stddefs.h"
3#include "cpuio.h"
4#include "genlib.h"
5#include "cache.h"
6#include "warmstart.h"
7#include "timer.h"
8#include "am335x.h"
9#include "uart16550.h"
10
11int
12getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
13{
14        *lo = ((48000000/16)/baud) & 0x00ff;
15        *hi = (((48000000/16)/baud) & 0xff00) >> 8;
16        return(0);
17}
18
19/* devInit():
20 * As a bare minimum, initialize the console UART here using the
21 * incoming 'baud' value as the baud rate.
22 */
23void
24devInit(int baud)
25{
26        /* ADD_CODE_HERE */
27}
28
29/* ConsoleBaudSet():
30 * Provide a means to change the baud rate of the running
31 * console interface.  If the incoming value is not a valid
32 * baud rate, then default to 9600.
33 * In the early stages of a new port this can be left empty.
34 * Return 0 if successful; else -1.
35 */
36/*int
37ConsoleBaudSet(int baud)
38{
39        // ADD_CODE_HERE
40        return(0);
41}*/
42
43/* target_console_empty():
44 * Target-specific portion of flush_console() in chario.c.
45 * This function returns 1 if there are no characters waiting to
46 * be put out on the UART; else return 0 indicating that the UART
47 * is still busy outputting characters from its FIFO.
48 * In the early stages of a new port this can simply return 1.
49 */
50/*int
51target_console_empty(void)
52{
53        // if (UART_OUTPUT_BUFFER_IS_EMPTY())  <- FIX CODE HERE
54                return(0);
55        return(1);
56}*/
57
58/* intsoff():
59 * Disable all system interrupts here and return a value that can
60 * be used by intsrestore() (later) to restore the interrupt state.
61 */
62ulong
63intsoff(void)
64{
65        ulong status = 0;
66
67        /* ADD_CODE_HERE */
68        return(status);
69}
70
71/* intsrestore():
72 * Re-establish system interrupts here by using the status value
73 * that was returned by an earlier call to intsoff().
74 */
75void
76intsrestore(ulong status)
77{
78        /* ADD_CODE_HERE */
79}
80
81/* cacheInitForTarget():
82 * Establish target specific function pointers and
83 * enable i-cache...
84 * Refer to $core/cache.c for a description of the function pointers.
85 * NOTE:
86 * If cache (either I or D or both) is enabled, then it is important
87 * that the appropriate cacheflush/invalidate function be established.
88 * This is very important because programs (i.e. cpu instructions) are
89 * transferred to memory using data memory accesses and could
90 * potentially result in cache coherency problems.
91 */
92void
93cacheInitForTarget(void)
94{
95        /* ADD_CODE_HERE */
96}
97
98/* target_reset():
99 * The default (absolute minimum) action to be taken by this function
100 * is to call monrestart(INITIALIZE).  It would be better if there was
101 * some target-specific function that would really cause the target
102 * to reset...
103 */
104void
105target_reset(void)
106{
107//      flushDcache(0,0);
108//      disableDcache();
109//      invalidateIcache(0,0);
110//      disableIcache();
111        monrestart(INITIALIZE);
112}
113
114/* Override the default exception handlers provided by the AM335x
115 * internal ROM code with uMon's custom exception handlers
116 */
117void
118ram_vector_install(void)
119{
120        extern unsigned long abort_data;
121        extern unsigned long abort_prefetch;
122        extern unsigned long undefined_instruction;
123        extern unsigned long software_interrupt;
124        extern unsigned long interrupt_request;
125        extern unsigned long fast_interrupt_request;
126        extern unsigned long not_assigned;
127
128        *(ulong **)0x4030ce24 = &undefined_instruction;
129        *(ulong **)0x4030ce28 = &software_interrupt;
130        *(ulong **)0x4030ce2c = &abort_prefetch;
131        *(ulong **)0x4030ce30 = &abort_data;
132        *(ulong **)0x4030ce34 = &not_assigned;
133        *(ulong **)0x4030ce38 = &interrupt_request;
134        *(ulong **)0x4030ce3c = &fast_interrupt_request;
135}
136
137void
138pinMuxInit(void)
139{
140        // Set pin mux configuration for UART0 RX/TX pins
141        CNTL_MODULE_REG(CONF_UART0_RXD) = SLEWSLOW | RX_ON |
142                PULL_OFF | MUXMODE_0;
143        CNTL_MODULE_REG(CONF_UART0_TXD) = SLEWSLOW | RX_OFF |
144                PULL_OFF | MUXMODE_0;
145}
146
147/* If any CPU IO wasn't initialized in reset.S, do it here...
148 * This just provides a "C-level" IO init opportunity.
149 */
150void
151initCPUio(void)
152{
153        ram_vector_install();
154
155        // Enable the control module:
156        CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
157
158        // Enable clock for UART0:
159        CM_WKUP_REG(CM_WKUP_UART0_CLKCTRL) |= 2;
160
161        pinMuxInit();
162
163        InitUART(DEFAULT_BAUD_RATE);
164
165        // Set UART0 mode to 16x
166        UART0_REG(UART_MDR1) &= ~7;
167}
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