source: umon/ports/beagleboneblack/cpuio.c @ 91be006

Last change on this file since 91be006 was 976c170, checked in by Jarielle Catbagan <jcatbagan93@…>, on 08/07/15 at 18:04:18

BBB: Clean up *.c and *.h files using 'astyle --unpad-paren --align-pointer=name --lineend=linux --add-brackets --convert-tabs -A4 <file>'

Note: <file> is the file being formatted

  • Property mode set to 100644
File size: 18.0 KB
Line 
1#include "config.h"
2#include "stddefs.h"
3#include "cpuio.h"
4#include "genlib.h"
5#include "cache.h"
6#include "warmstart.h"
7#include "timer.h"
8#include "am335x.h"
9#include "uart16550.h"
10#include "cli.h"
11
12int
13getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
14{
15    *lo = ((48000000/16)/baud) & 0x00ff;
16    *hi = (((48000000/16)/baud) & 0xff00) >> 8;
17    return(0);
18}
19
20/* devInit():
21 * As a bare minimum, initialize the console UART here using the
22 * incoming 'baud' value as the baud rate.
23 */
24int
25devInit(int baud)
26{
27    return(0);
28}
29
30/* ConsoleBaudSet():
31 * Provide a means to change the baud rate of the running
32 * console interface.  If the incoming value is not a valid
33 * baud rate, then default to 9600.
34 * In the early stages of a new port this can be left empty.
35 * Return 0 if successful; else -1.
36 */
37/*int
38ConsoleBaudSet(int baud)
39{
40    // ADD_CODE_HERE
41    return(0);
42}*/
43
44/* target_console_empty():
45 * Target-specific portion of flush_console() in chario.c.
46 * This function returns 1 if there are no characters waiting to
47 * be put out on the UART; else return 0 indicating that the UART
48 * is still busy outputting characters from its FIFO.
49 * In the early stages of a new port this can simply return 1.
50 */
51/*int
52target_console_empty(void)
53{
54    // if (UART_OUTPUT_BUFFER_IS_EMPTY())  <- FIX CODE HERE
55        return(0);
56    return(1);
57}*/
58
59/* intsoff():
60 * Disable all system interrupts here and return a value that can
61 * be used by intsrestore() (later) to restore the interrupt state.
62 */
63ulong
64intsoff(void)
65{
66    ulong status = 0;
67
68    /* ADD_CODE_HERE */
69    return(status);
70}
71
72/* intsrestore():
73 * Re-establish system interrupts here by using the status value
74 * that was returned by an earlier call to intsoff().
75 */
76void
77intsrestore(ulong status)
78{
79    /* ADD_CODE_HERE */
80}
81
82/* cacheInitForTarget():
83 * Establish target specific function pointers and
84 * enable i-cache...
85 * Refer to $core/cache.c for a description of the function pointers.
86 * NOTE:
87 * If cache (either I or D or both) is enabled, then it is important
88 * that the appropriate cacheflush/invalidate function be established.
89 * This is very important because programs (i.e. cpu instructions) are
90 * transferred to memory using data memory accesses and could
91 * potentially result in cache coherency problems.
92 */
93void
94cacheInitForTarget(void)
95{
96    /* ADD_CODE_HERE */
97}
98
99/* target_reset():
100 * The default (absolute minimum) action to be taken by this function
101 * is to call monrestart(INITIALIZE).  It would be better if there was
102 * some target-specific function that would really cause the target
103 * to reset...
104 */
105void
106target_reset(void)
107{
108//  flushDcache(0,0);
109//  disableDcache();
110//  invalidateIcache(0,0);
111//  disableIcache();
112    monrestart(INITIALIZE);
113}
114
115/* Override the default exception handlers provided by the AM335x
116 * internal ROM code with uMon's custom exception handlers
117 */
118void
119ram_vector_install(void)
120{
121    extern unsigned long abort_data;
122    extern unsigned long abort_prefetch;
123    extern unsigned long undefined_instruction;
124    extern unsigned long software_interrupt;
125    extern unsigned long interrupt_request;
126    extern unsigned long fast_interrupt_request;
127    extern unsigned long not_assigned;
128
129    *(ulong **)0x4030ce24 = &undefined_instruction;
130    *(ulong **)0x4030ce28 = &software_interrupt;
131    *(ulong **)0x4030ce2c = &abort_prefetch;
132    *(ulong **)0x4030ce30 = &abort_data;
133    *(ulong **)0x4030ce34 = &not_assigned;
134    *(ulong **)0x4030ce38 = &interrupt_request;
135    *(ulong **)0x4030ce3c = &fast_interrupt_request;
136}
137
138void
139pinMuxInit(void)
140{
141    // Set pin mux configuration for UART0 RX/TX pins
142    CNTL_MODULE_REG(CONF_UART0_RXD) = SLEWSLOW | RX_ON |
143                                      PULL_OFF | MUXMODE_0;
144    CNTL_MODULE_REG(CONF_UART0_TXD) = SLEWSLOW | RX_OFF |
145                                      PULL_OFF | MUXMODE_0;
146
147    // Configure GPIO pins tied to four USR LEDS...
148    // GPIO1_21: USER0 LED (D2)
149    CNTL_MODULE_REG(CONF_GPMC_A5) = SLEWSLOW | RX_ON |
150                                    PULL_OFF | MUXMODE_7;
151    // GPIO1_22: USER1 LED (D3)
152    CNTL_MODULE_REG(CONF_GPMC_A6) = SLEWSLOW | RX_ON |
153                                    PULL_OFF | MUXMODE_7;
154    // GPIO1_23: USER2 LED (D4)
155    CNTL_MODULE_REG(CONF_GPMC_A7) = SLEWSLOW | RX_ON |
156                                    PULL_OFF | MUXMODE_7;
157    // GPIO1_24: USER3 LED (D5)
158    CNTL_MODULE_REG(CONF_GPMC_A8) = SLEWSLOW | RX_ON |
159                                    PULL_OFF | MUXMODE_7;
160
161    // Configure the pins for the MMC0 interface
162    CNTL_MODULE_REG(CONF_MMC0_DAT0) = RX_ON | PULL_ON |
163                                      PULLUP | MUXMODE_0;
164    CNTL_MODULE_REG(CONF_MMC0_DAT1) = RX_ON | PULL_ON |
165                                      PULLUP | MUXMODE_0;
166    CNTL_MODULE_REG(CONF_MMC0_DAT2) = RX_ON | PULL_ON |
167                                      PULLUP | MUXMODE_0;
168    CNTL_MODULE_REG(CONF_MMC0_DAT3) = RX_ON | PULL_ON |
169                                      PULLUP | MUXMODE_0;
170    CNTL_MODULE_REG(CONF_MMC0_CLK) = RX_ON | PULL_OFF |
171                                     MUXMODE_0;
172    CNTL_MODULE_REG(CONF_MMC0_CMD) = RX_ON | PULL_ON |
173                                     PULLUP | MUXMODE_0;
174    CNTL_MODULE_REG(CONF_SPI0_CS1) = RX_ON | PULL_ON |
175                                     PULLUP | MUXMODE_5;
176
177    // Configure the pins for the MMC1 interface
178    /* MMC1_DAT0 */
179    CNTL_MODULE_REG(CONF_GPMC_AD0) = RX_ON | PULL_ON |
180                                     PULLUP | MUXMODE_1;
181    /* MMC1_DAT1 */
182    CNTL_MODULE_REG(CONF_GPMC_AD1) = RX_ON | PULL_ON |
183                                     PULLUP | MUXMODE_1;
184    /* MMC1_DAT2 */
185    CNTL_MODULE_REG(CONF_GPMC_AD2) = RX_ON | PULL_ON |
186                                     PULLUP | MUXMODE_1;
187    /* MMC1_DAT3 */
188    CNTL_MODULE_REG(CONF_GPMC_AD3) = RX_ON | PULL_ON |
189                                     PULLUP | MUXMODE_1;
190    /* MMC1_DAT4 */
191    CNTL_MODULE_REG(CONF_GPMC_AD4) = RX_ON | PULL_ON |
192                                     PULLUP | MUXMODE_1;
193    /* MMC1_DAT5 */
194    CNTL_MODULE_REG(CONF_GPMC_AD5) = RX_ON | PULL_ON |
195                                     PULLUP | MUXMODE_1;
196    /* MMC1_DAT6 */
197    CNTL_MODULE_REG(CONF_GPMC_AD6) = RX_ON | PULL_ON |
198                                     PULLUP | MUXMODE_1;
199    /* MMC1_DAT7 */
200    CNTL_MODULE_REG(CONF_GPMC_AD7) = RX_ON | PULL_ON |
201                                     PULLUP | MUXMODE_1;
202    /* MMC1_CLK */
203    CNTL_MODULE_REG(CONF_GPMC_CSN1) = RX_ON | PULL_OFF |
204                                      MUXMODE_2;
205    /* MMC1_CMD */
206    CNTL_MODULE_REG(CONF_GPMC_CSN2) = RX_ON | PULL_ON |
207                                      PULLUP | MUXMODE_2;
208}
209
210void
211InitGPIO1(void)
212{
213    // GPIO_CTRL: Enable GPIO1 module
214    GPIO1_REG(0x130) = 0;
215
216    // GPIO_OE: 25-24 are outputs...
217    GPIO1_REG(0x134) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
218
219    // All LEDs off...
220    GPIO1_REG(0x13c) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
221}
222
223/* If any CPU IO wasn't initialized in reset.S, do it here...
224 * This just provides a "C-level" IO init opportunity.
225 */
226void
227initCPUio(void)
228{
229    ram_vector_install();
230
231    // Enable the control module:
232    CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
233
234    // Enable clock for UART0:
235    CM_WKUP_REG(CM_WKUP_UART0_CLKCTRL) |= 2;
236
237    // Enable clock for GPIO1:
238    CM_PER_REG(CM_PER_GPIO1_CLKCTRL) |= 2;
239
240    /* Enable MMC0 clocks */
241    CM_PER_REG(CM_PER_MMC0_CLKCTRL) |= CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE;
242    while(CM_PER_REG(CM_PER_MMC0_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
243
244    /* Enable MMC1 clocks */
245    CM_PER_REG(CM_PER_MMC1_CLKCTRL) |= CM_PER_MMC1_CLKCTRL_MODULEMODE_ENABLE;
246    while(CM_PER_REG(CM_PER_MMC1_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
247
248    pinMuxInit();
249
250    InitUART(DEFAULT_BAUD_RATE);
251    InitGPIO1();
252
253    // Set UART0 mode to 16x
254    UART0_REG(UART_MDR1) &= ~7;
255}
256
257int
258led(int num, int on)
259{
260    unsigned long bit;
261
262    switch(num) {
263    case 0: // D0
264        bit = USR0_LED;
265        break;
266    case 1: // D1
267        bit = USR1_LED;
268        break;
269    case 2: // D2
270        bit = USR2_LED;
271        break;
272    case 3: // D3
273        bit = USR3_LED;
274        break;
275    default:
276        return(-1);
277    }
278
279    // GPIO21-24:
280    if(on) {
281        GPIO1_REG(0x13c) |= bit;
282    } else {
283        GPIO1_REG(0x13c) &= ~bit;
284    }
285    return(0);
286}
287
288void
289target_blinkled(void)
290{
291#if INCLUDE_BLINKLED
292    static uint8_t ledstate;
293    static struct elapsed_tmr tmr;
294
295#define STATLED_ON()    led(0,1)
296#define STATLED_OFF()   led(0,0)
297#ifndef BLINKON_MSEC
298#define BLINKON_MSEC 10000
299#define BLINKOFF_MSEC 10000
300#endif
301
302    switch(ledstate) {
303    case 0:
304        startElapsedTimer(&tmr,BLINKON_MSEC);
305        STATLED_ON();
306        ledstate = 1;
307        break;
308    case 1:
309        if(msecElapsed(&tmr)) {
310            STATLED_OFF();
311            ledstate = 2;
312            startElapsedTimer(&tmr,BLINKOFF_MSEC);
313        }
314        break;
315    case 2:
316        if(msecElapsed(&tmr)) {
317            STATLED_ON();
318            ledstate = 1;
319            startElapsedTimer(&tmr,BLINKON_MSEC);
320        }
321        break;
322    }
323#endif
324}
325
326void
327mpu_pll_init(void)
328{
329    uint32_t cm_clkmode_dpll_mpu;
330    uint32_t cm_clksel_dpll_mpu;
331    uint32_t cm_div_m2_dpll_mpu;
332
333    // Put MPU PLL in MN Bypass mode
334    cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
335    cm_clkmode_dpll_mpu &= ~0x00000007;
336    cm_clkmode_dpll_mpu |= 0x00000004;
337    CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
338    // Wait for MPU PLL to enter MN Bypass mode
339    while((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000101) != 0x00000100);
340
341    // Set the ARM core frequency to 1 GHz
342    cm_clksel_dpll_mpu = CM_WKUP_REG(CM_CLKSEL_DPLL_MPU);
343    cm_clksel_dpll_mpu &= ~0x0007FF7F;
344    cm_clksel_dpll_mpu |= 1000 << 8;
345    cm_clksel_dpll_mpu |= 23;
346    CM_WKUP_REG(CM_CLKSEL_DPLL_MPU) = cm_clksel_dpll_mpu;
347    cm_div_m2_dpll_mpu = CM_WKUP_REG(CM_DIV_M2_DPLL_MPU);
348    cm_div_m2_dpll_mpu &= ~0x0000001F;
349    cm_div_m2_dpll_mpu |= 0x00000001;
350    CM_WKUP_REG(CM_DIV_M2_DPLL_MPU) = cm_div_m2_dpll_mpu;
351
352    // Lock MPU PLL
353    cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
354    cm_clkmode_dpll_mpu &= ~0x00000007;
355    cm_clkmode_dpll_mpu |= 0x00000007;
356    CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
357    // Wait for MPU PLL to lock
358    while((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000001) != 0x00000001);
359}
360
361void
362core_pll_init(void)
363{
364    uint32_t cm_clkmode_dpll_core;
365    uint32_t cm_clksel_dpll_core;
366    uint32_t cm_div_m4_dpll_core;
367    uint32_t cm_div_m5_dpll_core;
368    uint32_t cm_div_m6_dpll_core;
369
370    // Put Core PLL in MN Bypass mode
371    cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
372    cm_clkmode_dpll_core &= ~0x00000007;
373    cm_clkmode_dpll_core |= 0x00000004;
374    CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
375    // Wait for Core PLL to enter MN Bypass mode
376    while((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000101) != 0x00000100);
377
378    // Configure the multiplier and divider
379    cm_clksel_dpll_core = CM_WKUP_REG(CM_CLKSEL_DPLL_CORE);
380    cm_clksel_dpll_core &= ~0x0007FF7F;
381    cm_clksel_dpll_core |= 1000 << 8;
382    cm_clksel_dpll_core |= 23;
383    CM_WKUP_REG(CM_CLKSEL_DPLL_CORE) = cm_clksel_dpll_core;
384    // Configure the M4, M5, and M6 dividers
385    cm_div_m4_dpll_core = CM_WKUP_REG(CM_DIV_M4_DPLL_CORE);
386    cm_div_m4_dpll_core &= ~0x0000001F;
387    cm_div_m4_dpll_core |= 10;
388    CM_WKUP_REG(CM_DIV_M4_DPLL_CORE) = cm_div_m4_dpll_core;
389    cm_div_m5_dpll_core = CM_WKUP_REG(CM_DIV_M5_DPLL_CORE);
390    cm_div_m5_dpll_core &= ~0x0000001F;
391    cm_div_m5_dpll_core |= 8;
392    CM_WKUP_REG(CM_DIV_M5_DPLL_CORE) = cm_div_m5_dpll_core;
393    cm_div_m6_dpll_core = CM_WKUP_REG(CM_DIV_M6_DPLL_CORE);
394    cm_div_m6_dpll_core &= ~0x0000001F;
395    cm_div_m6_dpll_core |= 4;
396    CM_WKUP_REG(CM_DIV_M6_DPLL_CORE) = cm_div_m6_dpll_core;
397
398    // Lock Core PLL
399    cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
400    cm_clkmode_dpll_core &= ~0x00000007;
401    cm_clkmode_dpll_core |= 0x00000007;
402    CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
403    // Wait for Core PLL to lock
404    while((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000001) != 0x00000001);
405}
406
407void
408ddr_pll_init(void)
409{
410    uint32_t cm_clkmode_dpll_ddr;
411    uint32_t cm_clksel_dpll_ddr;
412    uint32_t cm_div_m2_dpll_ddr;
413
414    // Put DDR PLL in MN Bypass mode
415    cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
416    cm_clkmode_dpll_ddr &= ~0x00000007;
417    cm_clkmode_dpll_ddr |= 0x00000004;
418    CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
419    // Wait for DDR PLL to enter MN Bypass mode
420    while((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000101) != 0x00000100);
421
422    // Set the DDR frequency to 400 MHz
423    cm_clksel_dpll_ddr = CM_WKUP_REG(CM_CLKSEL_DPLL_DDR);
424    cm_clksel_dpll_ddr &= ~0x0007FF7F;
425    cm_clksel_dpll_ddr |= 400 << 8;
426    cm_clksel_dpll_ddr |= 23;
427    CM_WKUP_REG(CM_CLKSEL_DPLL_DDR) = cm_clksel_dpll_ddr;
428    // Set M2 divider
429    cm_div_m2_dpll_ddr = CM_WKUP_REG(CM_DIV_M2_DPLL_DDR);
430    cm_div_m2_dpll_ddr &= ~0x0000001F;
431    cm_div_m2_dpll_ddr |= 1;
432    CM_WKUP_REG(CM_DIV_M2_DPLL_DDR) = cm_div_m2_dpll_ddr;
433
434    // Lock the DDR PLL
435    cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
436    cm_clkmode_dpll_ddr &= ~0x00000007;
437    cm_clkmode_dpll_ddr |= 0x00000007;
438    CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
439    // Wait for DDR PLL to lock
440    while((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x00000001);
441}
442
443void
444per_pll_init(void)
445{
446    uint32_t cm_clkmode_dpll_per;
447    uint32_t cm_clksel_dpll_per;
448    uint32_t cm_div_m2_dpll_per;
449
450    // Put Per PLL in MN Bypass mode
451    cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
452    cm_clkmode_dpll_per &= ~0x00000007;
453    cm_clkmode_dpll_per |= 0x00000004;
454    CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
455    // Wait for Per PLL to enter MN Bypass mode
456    while((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000101) != 0x00000100);
457
458    // Configure the multiplier and divider
459    cm_clksel_dpll_per = CM_WKUP_REG(CM_CLKSEL_DPLL_PER);
460    cm_clksel_dpll_per &= ~0xFF0FFFFF;
461    cm_clksel_dpll_per |= CM_CLKSEL_DPLL_PER_DPLL_SD_DIV | CM_CLKSEL_DPLL_PER_DPLL_MULT |
462                          CM_CLKSEL_DPLL_PER_DPLL_DIV;
463    CM_WKUP_REG(CM_CLKSEL_DPLL_PER) = cm_clksel_dpll_per;
464    // Set M2 divider
465    cm_div_m2_dpll_per = CM_WKUP_REG(CM_DIV_M2_DPLL_PER);
466    cm_div_m2_dpll_per &= ~0x0000007F;
467    cm_div_m2_dpll_per |= 5;
468    CM_WKUP_REG(CM_DIV_M2_DPLL_PER) = cm_div_m2_dpll_per;
469
470    // Lock the Per PLL
471    cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
472    cm_clkmode_dpll_per &= ~0x00000007;
473    cm_clkmode_dpll_per |= 0x00000007;
474    CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
475    // Wait for Per PLL to lock
476    while((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000001) != 0x00000001);
477}
478
479void
480pll_init(void)
481{
482    mpu_pll_init();
483    core_pll_init();
484    ddr_pll_init();
485    per_pll_init();
486}
487
488void
489ddr_init(void)
490{
491    uint32_t reg;
492
493    // Enable the control module:
494    CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
495
496    // Enable EMIF module
497    reg = CM_PER_REG(CM_PER_EMIF_CLKCTRL);
498    reg &= ~3;
499    reg |= 2;
500    CM_PER_REG(CM_PER_EMIF_CLKCTRL) = reg;
501    while((CM_PER_REG(CM_PER_L3_CLKSTCTRL) & 0x00000004) != 0x00000004);
502
503    // Configure VTP control
504    CNTL_MODULE_REG(VTP_CTRL) |= 0x00000040;
505    CNTL_MODULE_REG(VTP_CTRL) &= ~1;
506    CNTL_MODULE_REG(VTP_CTRL) |= 1;
507    // Wait for VTP control to be ready
508    while((CNTL_MODULE_REG(VTP_CTRL) & 0x00000020) != 0x00000020);
509
510    // Configure the DDR PHY CMDx/DATAx registers
511    DDR_PHY_REG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
512    DDR_PHY_REG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
513    DDR_PHY_REG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
514    DDR_PHY_REG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
515    DDR_PHY_REG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
516    DDR_PHY_REG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
517
518    DDR_PHY_REG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
519    DDR_PHY_REG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
520    DDR_PHY_REG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
521    DDR_PHY_REG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
522
523    DDR_PHY_REG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
524    DDR_PHY_REG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
525    DDR_PHY_REG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
526    DDR_PHY_REG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
527
528    CNTL_MODULE_REG(DDR_CMD0_IOCTRL) = 0x018B;
529    CNTL_MODULE_REG(DDR_CMD1_IOCTRL) = 0x018B;
530    CNTL_MODULE_REG(DDR_CMD2_IOCTRL) = 0x018B;
531    CNTL_MODULE_REG(DDR_DATA0_IOCTRL) = 0x018B;
532    CNTL_MODULE_REG(DDR_DATA1_IOCTRL) = 0x018B;
533
534    CNTL_MODULE_REG(DDR_IO_CTRL) &= ~0x10000000;
535
536    CNTL_MODULE_REG(DDR_CKE_CTRL) |= 0x00000001;
537
538    // Enable dynamic power down when no read is being performed and set read latency
539    // to CAS Latency + 2 - 1
540    EMIF0_REG(DDR_PHY_CTRL_1) = 0x00100007;
541    EMIF0_REG(DDR_PHY_CTRL_1_SHDW) = 0x00100007;
542
543    // Configure the AC timing characteristics
544    EMIF0_REG(SDRAM_TIM_1) = 0x0AAAD4DB;
545    EMIF0_REG(SDRAM_TIM_1_SHDW) = 0x0AAAD4DB;
546    EMIF0_REG(SDRAM_TIM_2) = 0x266B7FDA;
547    EMIF0_REG(SDRAM_TIM_2_SHDW) = 0x266B7FDA;
548    EMIF0_REG(SDRAM_TIM_3) = 0x501F867F;
549    EMIF0_REG(SDRAM_TIM_3_SHDW) = 0x501F867F;
550
551    // Set the refresh rate, 400,000,000 * 7.8 * 10^-6 = 3120 = 0x0C30
552    EMIF0_REG(SDRAM_REF_CTRL) = 0x00000C30;
553    // set the referesh rate shadow register to the same value as previous
554    EMIF0_REG(SDRAM_REF_CTRL_SHDW) = 0x00000C30;
555
556    // Configure the ZQ Calibration
557    EMIF0_REG(ZQ_CONFIG) = 0x50074BE4;
558
559    // Configure the SDRAM characteristics
560    reg |= SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 | SDRAM_CONFIG_REG_IBANK_POS_0 |
561           SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 | SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS |
562           SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 | SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE |
563           SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 | SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 |
564           SDRAM_CONFIG_REG_NARROW_MODE_16BIT | SDRAM_CONFIG_REG_CAS_LATENCY_6 |
565           SDRAM_CONFIG_REG_ROWSIZE_15BIT | SDRAM_CONFIG_REG_IBANK_8 |
566           SDRAM_CONFIG_REG_EBANK_1 | SDRAM_CONFIG_REG_PAGESIZE_1024_WORD;
567    EMIF0_REG(SDRAM_CONFIG) = reg;
568    CNTL_MODULE_REG(CONTROL_EMIF_SDRAM_CONFIG) = reg;
569
570    // Set the external bank position to 0
571    EMIF0_REG(SDRAM_CONFIG_2) |= SDRAM_CONFIG_2_REG_EBANK_POS_0;
572}
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