source: umon/ports/beagleboneblack/cpuio.c @ 5a75bc2

Last change on this file since 5a75bc2 was 5a75bc2, checked in by Jarielle Catbagan <jcatbagan93@…>, on Aug 3, 2015 at 4:16:39 AM

BBB: cpuio.c: Configure pins used for MMC0 interface

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File size: 14.8 KB
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1#include "config.h"
2#include "stddefs.h"
3#include "cpuio.h"
4#include "genlib.h"
5#include "cache.h"
6#include "warmstart.h"
7#include "timer.h"
8#include "am335x.h"
9#include "uart16550.h"
10#include "cli.h"
11
12int
13getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
14{
15        *lo = ((48000000/16)/baud) & 0x00ff;
16        *hi = (((48000000/16)/baud) & 0xff00) >> 8;
17        return(0);
18}
19
20/* devInit():
21 * As a bare minimum, initialize the console UART here using the
22 * incoming 'baud' value as the baud rate.
23 */
24int
25devInit(int baud)
26{
27        return(0);
28}
29
30/* ConsoleBaudSet():
31 * Provide a means to change the baud rate of the running
32 * console interface.  If the incoming value is not a valid
33 * baud rate, then default to 9600.
34 * In the early stages of a new port this can be left empty.
35 * Return 0 if successful; else -1.
36 */
37/*int
38ConsoleBaudSet(int baud)
39{
40        // ADD_CODE_HERE
41        return(0);
42}*/
43
44/* target_console_empty():
45 * Target-specific portion of flush_console() in chario.c.
46 * This function returns 1 if there are no characters waiting to
47 * be put out on the UART; else return 0 indicating that the UART
48 * is still busy outputting characters from its FIFO.
49 * In the early stages of a new port this can simply return 1.
50 */
51/*int
52target_console_empty(void)
53{
54        // if (UART_OUTPUT_BUFFER_IS_EMPTY())  <- FIX CODE HERE
55                return(0);
56        return(1);
57}*/
58
59/* intsoff():
60 * Disable all system interrupts here and return a value that can
61 * be used by intsrestore() (later) to restore the interrupt state.
62 */
63ulong
64intsoff(void)
65{
66        ulong status = 0;
67
68        /* ADD_CODE_HERE */
69        return(status);
70}
71
72/* intsrestore():
73 * Re-establish system interrupts here by using the status value
74 * that was returned by an earlier call to intsoff().
75 */
76void
77intsrestore(ulong status)
78{
79        /* ADD_CODE_HERE */
80}
81
82/* cacheInitForTarget():
83 * Establish target specific function pointers and
84 * enable i-cache...
85 * Refer to $core/cache.c for a description of the function pointers.
86 * NOTE:
87 * If cache (either I or D or both) is enabled, then it is important
88 * that the appropriate cacheflush/invalidate function be established.
89 * This is very important because programs (i.e. cpu instructions) are
90 * transferred to memory using data memory accesses and could
91 * potentially result in cache coherency problems.
92 */
93void
94cacheInitForTarget(void)
95{
96        /* ADD_CODE_HERE */
97}
98
99/* target_reset():
100 * The default (absolute minimum) action to be taken by this function
101 * is to call monrestart(INITIALIZE).  It would be better if there was
102 * some target-specific function that would really cause the target
103 * to reset...
104 */
105void
106target_reset(void)
107{
108//      flushDcache(0,0);
109//      disableDcache();
110//      invalidateIcache(0,0);
111//      disableIcache();
112        monrestart(INITIALIZE);
113}
114
115/* Override the default exception handlers provided by the AM335x
116 * internal ROM code with uMon's custom exception handlers
117 */
118void
119ram_vector_install(void)
120{
121        extern unsigned long abort_data;
122        extern unsigned long abort_prefetch;
123        extern unsigned long undefined_instruction;
124        extern unsigned long software_interrupt;
125        extern unsigned long interrupt_request;
126        extern unsigned long fast_interrupt_request;
127        extern unsigned long not_assigned;
128
129        *(ulong **)0x4030ce24 = &undefined_instruction;
130        *(ulong **)0x4030ce28 = &software_interrupt;
131        *(ulong **)0x4030ce2c = &abort_prefetch;
132        *(ulong **)0x4030ce30 = &abort_data;
133        *(ulong **)0x4030ce34 = &not_assigned;
134        *(ulong **)0x4030ce38 = &interrupt_request;
135        *(ulong **)0x4030ce3c = &fast_interrupt_request;
136}
137
138void
139pinMuxInit(void)
140{
141        // Set pin mux configuration for UART0 RX/TX pins
142        CNTL_MODULE_REG(CONF_UART0_RXD) = SLEWSLOW | RX_ON |
143                PULL_OFF | MUXMODE_0;
144        CNTL_MODULE_REG(CONF_UART0_TXD) = SLEWSLOW | RX_OFF |
145                PULL_OFF | MUXMODE_0;
146
147        // Configure GPIO pins tied to four USR LEDS...
148        // GPIO1_21: USER0 LED (D2)
149        CNTL_MODULE_REG(CONF_GPMC_A5) = SLEWSLOW | RX_ON |
150                PULL_OFF | MUXMODE_7;
151        // GPIO1_22: USER1 LED (D3)
152        CNTL_MODULE_REG(CONF_GPMC_A6) = SLEWSLOW | RX_ON |
153                PULL_OFF | MUXMODE_7;
154        // GPIO1_23: USER2 LED (D4)
155        CNTL_MODULE_REG(CONF_GPMC_A7) = SLEWSLOW | RX_ON |
156                PULL_OFF | MUXMODE_7;
157        // GPIO1_24: USER3 LED (D5)
158        CNTL_MODULE_REG(CONF_GPMC_A8) = SLEWSLOW | RX_ON |
159                PULL_OFF | MUXMODE_7;
160
161        // Configure the pins for the MMC0 interface
162        CNTL_MODULE_REG(CONF_MMC0_DAT0) = RX_ON | PULL_ON |
163                PULLUP | MUXMODE_0;
164        CNTL_MODULE_REG(CONF_MMC0_DAT1) = RX_ON | PULL_ON |
165                PULLUP | MUXMODE_0;
166        CNTL_MODULE_REG(CONF_MMC0_DAT2) = RX_ON | PULL_ON |
167                PULLUP | MUXMODE_0;
168        CNTL_MODULE_REG(CONF_MMC0_DAT3) = RX_ON | PULL_ON |
169                PULLUP | MUXMODE_0;
170        CNTL_MODULE_REG(CONF_MMC0_CLK) = RX_ON | PULL_OFF |
171                MUXMODE_0;
172        CNTL_MODULE_REG(CONF_MMC0_CMD) = RX_ON | PULL_ON |
173                PULLUP | MUXMODE_0;
174        CNTL_MODULE_REG(CONF_SPI0_CS1) = RX_ON | PULL_ON |
175                PULLUP | MUXMODE_5;
176}
177
178void
179InitGPIO1(void)
180{
181        // GPIO_CTRL: Enable GPIO1 module
182        GPIO1_REG(0x130) = 0;
183
184        // GPIO_OE: 25-24 are outputs...
185        GPIO1_REG(0x134) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
186
187        // All LEDs off...
188        GPIO1_REG(0x13c) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
189}
190
191/* If any CPU IO wasn't initialized in reset.S, do it here...
192 * This just provides a "C-level" IO init opportunity.
193 */
194void
195initCPUio(void)
196{
197        ram_vector_install();
198
199        // Enable the control module:
200        CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
201
202        // Enable clock for UART0:
203        CM_WKUP_REG(CM_WKUP_UART0_CLKCTRL) |= 2;
204
205        // Enable clock for GPIO1:
206        CM_PER_REG(CM_PER_GPIO1_CLKCTRL) |= 2;
207
208        pinMuxInit();
209
210        InitUART(DEFAULT_BAUD_RATE);
211        InitGPIO1();
212
213        // Set UART0 mode to 16x
214        UART0_REG(UART_MDR1) &= ~7;
215}
216
217int
218led(int num, int on)
219{
220        unsigned long bit;
221
222        switch(num) {
223                case 0: // D0
224                        bit = USR0_LED;
225                        break;
226                case 1: // D1
227                        bit = USR1_LED;
228                        break;
229                case 2: // D2
230                        bit = USR2_LED;
231                        break;
232                case 3: // D3
233                        bit = USR3_LED;
234                        break;
235                default:
236                        return(-1);
237        }
238
239        // GPIO21-24:
240        if (on)
241            GPIO1_REG(0x13c) |= bit;
242        else
243            GPIO1_REG(0x13c) &= ~bit;
244        return(0);
245}
246
247void
248target_blinkled(void)
249{
250#if INCLUDE_BLINKLED
251        static uint8_t ledstate;
252        static struct elapsed_tmr tmr;
253
254#define STATLED_ON()    led(0,1)
255#define STATLED_OFF()   led(0,0)
256#ifndef BLINKON_MSEC
257#define BLINKON_MSEC 10000
258#define BLINKOFF_MSEC 10000
259#endif
260
261        switch(ledstate) {
262                case 0:
263                        startElapsedTimer(&tmr,BLINKON_MSEC);
264                        STATLED_ON();
265                        ledstate = 1;
266                        break;
267                case 1:
268                        if(msecElapsed(&tmr)) {
269                                STATLED_OFF();
270                                ledstate = 2;
271                                startElapsedTimer(&tmr,BLINKOFF_MSEC);
272                        }
273                        break;
274                case 2:
275                        if(msecElapsed(&tmr)) {
276                                STATLED_ON();
277                                ledstate = 1;
278                                startElapsedTimer(&tmr,BLINKON_MSEC);
279                        }
280                        break;
281        }
282#endif
283}
284
285void
286mpu_pll_init(void)
287{
288        uint32_t cm_clkmode_dpll_mpu;
289        uint32_t cm_clksel_dpll_mpu;
290        uint32_t cm_div_m2_dpll_mpu;
291
292        // Put MPU PLL in MN Bypass mode
293        cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
294        cm_clkmode_dpll_mpu &= ~0x00000007;
295        cm_clkmode_dpll_mpu |= 0x00000004;
296        CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
297        // Wait for MPU PLL to enter MN Bypass mode
298        while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000101) != 0x00000100);
299
300        // Set the ARM core frequency to 1 GHz
301        cm_clksel_dpll_mpu = CM_WKUP_REG(CM_CLKSEL_DPLL_MPU);
302        cm_clksel_dpll_mpu &= ~0x0007FF7F;
303        cm_clksel_dpll_mpu |= 1000 << 8;
304        cm_clksel_dpll_mpu |= 23;
305        CM_WKUP_REG(CM_CLKSEL_DPLL_MPU) = cm_clksel_dpll_mpu;
306        cm_div_m2_dpll_mpu = CM_WKUP_REG(CM_DIV_M2_DPLL_MPU);
307        cm_div_m2_dpll_mpu &= ~0x0000001F;
308        cm_div_m2_dpll_mpu |= 0x00000001;
309        CM_WKUP_REG(CM_DIV_M2_DPLL_MPU) = cm_div_m2_dpll_mpu;
310
311        // Lock MPU PLL
312        cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
313        cm_clkmode_dpll_mpu &= ~0x00000007;
314        cm_clkmode_dpll_mpu |= 0x00000007;
315        CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
316        // Wait for MPU PLL to lock
317        while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000001) != 0x00000001);
318}
319
320void
321core_pll_init(void)
322{
323        uint32_t cm_clkmode_dpll_core;
324        uint32_t cm_clksel_dpll_core;
325        uint32_t cm_div_m4_dpll_core;
326        uint32_t cm_div_m5_dpll_core;
327        uint32_t cm_div_m6_dpll_core;
328
329        // Put Core PLL in MN Bypass mode
330        cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
331        cm_clkmode_dpll_core &= ~0x00000007;
332        cm_clkmode_dpll_core |= 0x00000004;
333        CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
334        // Wait for Core PLL to enter MN Bypass mode
335        while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000101) != 0x00000100);
336
337        // Configure the multiplier and divider
338        cm_clksel_dpll_core = CM_WKUP_REG(CM_CLKSEL_DPLL_CORE);
339        cm_clksel_dpll_core &= ~0x0007FF7F;
340        cm_clksel_dpll_core |= 1000 << 8;
341        cm_clksel_dpll_core |= 23;
342        CM_WKUP_REG(CM_CLKSEL_DPLL_CORE) = cm_clksel_dpll_core;
343        // Configure the M4, M5, and M6 dividers
344        cm_div_m4_dpll_core = CM_WKUP_REG(CM_DIV_M4_DPLL_CORE);
345        cm_div_m4_dpll_core &= ~0x0000001F;
346        cm_div_m4_dpll_core |= 10;
347        CM_WKUP_REG(CM_DIV_M4_DPLL_CORE) = cm_div_m4_dpll_core;
348        cm_div_m5_dpll_core = CM_WKUP_REG(CM_DIV_M5_DPLL_CORE);
349        cm_div_m5_dpll_core &= ~0x0000001F;
350        cm_div_m5_dpll_core |= 8;
351        CM_WKUP_REG(CM_DIV_M5_DPLL_CORE) = cm_div_m5_dpll_core;
352        cm_div_m6_dpll_core = CM_WKUP_REG(CM_DIV_M6_DPLL_CORE);
353        cm_div_m6_dpll_core &= ~0x0000001F;
354        cm_div_m6_dpll_core |= 4;
355        CM_WKUP_REG(CM_DIV_M6_DPLL_CORE) = cm_div_m6_dpll_core;
356
357        // Lock Core PLL
358        cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
359        cm_clkmode_dpll_core &= ~0x00000007;
360        cm_clkmode_dpll_core |= 0x00000007;
361        CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
362        // Wait for Core PLL to lock
363        while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000001) != 0x00000001);
364}
365
366void
367ddr_pll_init(void)
368{
369        uint32_t cm_clkmode_dpll_ddr;
370        uint32_t cm_clksel_dpll_ddr;
371        uint32_t cm_div_m2_dpll_ddr;
372
373        // Put DDR PLL in MN Bypass mode
374        cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
375        cm_clkmode_dpll_ddr &= ~0x00000007;
376        cm_clkmode_dpll_ddr |= 0x00000004;
377        CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
378        // Wait for DDR PLL to enter MN Bypass mode
379        while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000101) != 0x00000100);
380
381        // Set the DDR frequency to 400 MHz
382        cm_clksel_dpll_ddr = CM_WKUP_REG(CM_CLKSEL_DPLL_DDR);
383        cm_clksel_dpll_ddr &= ~0x0007FF7F;
384        cm_clksel_dpll_ddr |= 400 << 8;
385        cm_clksel_dpll_ddr |= 23;
386        CM_WKUP_REG(CM_CLKSEL_DPLL_DDR) = cm_clksel_dpll_ddr;
387        // Set M2 divider
388        cm_div_m2_dpll_ddr = CM_WKUP_REG(CM_DIV_M2_DPLL_DDR);
389        cm_div_m2_dpll_ddr &= ~0x0000001F;
390        cm_div_m2_dpll_ddr |= 1;
391        CM_WKUP_REG(CM_DIV_M2_DPLL_DDR) = cm_div_m2_dpll_ddr;
392
393        // Lock the DDR PLL
394        cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
395        cm_clkmode_dpll_ddr &= ~0x00000007;
396        cm_clkmode_dpll_ddr |= 0x00000007;
397        CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
398        // Wait for DDR PLL to lock
399        while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x00000001);
400}
401
402void
403per_pll_init(void)
404{
405        uint32_t cm_clkmode_dpll_per;
406        uint32_t cm_clksel_dpll_per;
407        uint32_t cm_div_m2_dpll_per;
408
409        // Put Per PLL in MN Bypass mode
410        cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
411        cm_clkmode_dpll_per &= ~0x00000007;
412        cm_clkmode_dpll_per |= 0x00000004;
413        CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
414        // Wait for Per PLL to enter MN Bypass mode
415        while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000101) != 0x00000100);
416
417        // Configure the multiplier and divider
418        cm_clksel_dpll_per = CM_WKUP_REG(CM_CLKSEL_DPLL_PER);
419        cm_clksel_dpll_per &= ~0xFF0FFFFF;
420        cm_clksel_dpll_per |= CM_CLKSEL_DPLL_PER_DPLL_SD_DIV | CM_CLKSEL_DPLL_PER_DPLL_MULT |
421                CM_CLKSEL_DPLL_PER_DPLL_DIV;
422        CM_WKUP_REG(CM_CLKSEL_DPLL_PER) = cm_clksel_dpll_per;
423        // Set M2 divider
424        cm_div_m2_dpll_per = CM_WKUP_REG(CM_DIV_M2_DPLL_PER);
425        cm_div_m2_dpll_per &= ~0x0000007F;
426        cm_div_m2_dpll_per |= 5;
427        CM_WKUP_REG(CM_DIV_M2_DPLL_PER) = cm_div_m2_dpll_per;
428
429        // Lock the Per PLL
430        cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
431        cm_clkmode_dpll_per &= ~0x00000007;
432        cm_clkmode_dpll_per |= 0x00000007;
433        CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
434        // Wait for Per PLL to lock
435        while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000001) != 0x00000001);
436}
437
438void
439pll_init(void)
440{
441        mpu_pll_init();
442        core_pll_init();
443        ddr_pll_init();
444        per_pll_init();
445}
446
447void
448ddr_init(void)
449{
450        uint32_t reg;
451
452        // Enable the control module:
453        CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
454
455        // Enable EMIF module
456        reg = CM_PER_REG(CM_PER_EMIF_CLKCTRL);
457        reg &= ~3;
458        reg |= 2;
459        CM_PER_REG(CM_PER_EMIF_CLKCTRL) = reg;
460        while ((CM_PER_REG(CM_PER_L3_CLKSTCTRL) & 0x00000004) != 0x00000004);
461
462        // Configure VTP control
463        CNTL_MODULE_REG(VTP_CTRL) |= 0x00000040;
464        CNTL_MODULE_REG(VTP_CTRL) &= ~1;
465        CNTL_MODULE_REG(VTP_CTRL) |= 1;
466        // Wait for VTP control to be ready
467        while ((CNTL_MODULE_REG(VTP_CTRL) & 0x00000020) != 0x00000020);
468
469        // Configure the DDR PHY CMDx/DATAx registers
470        DDR_PHY_REG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
471        DDR_PHY_REG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
472        DDR_PHY_REG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
473        DDR_PHY_REG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
474        DDR_PHY_REG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
475        DDR_PHY_REG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
476
477        DDR_PHY_REG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
478        DDR_PHY_REG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
479        DDR_PHY_REG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
480        DDR_PHY_REG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
481
482        DDR_PHY_REG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
483        DDR_PHY_REG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
484        DDR_PHY_REG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
485        DDR_PHY_REG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
486
487        CNTL_MODULE_REG(DDR_CMD0_IOCTRL) = 0x018B;
488        CNTL_MODULE_REG(DDR_CMD1_IOCTRL) = 0x018B;
489        CNTL_MODULE_REG(DDR_CMD2_IOCTRL) = 0x018B;
490        CNTL_MODULE_REG(DDR_DATA0_IOCTRL) = 0x018B;
491        CNTL_MODULE_REG(DDR_DATA1_IOCTRL) = 0x018B;
492
493        CNTL_MODULE_REG(DDR_IO_CTRL) &= ~0x10000000;
494
495        CNTL_MODULE_REG(DDR_CKE_CTRL) |= 0x00000001;
496
497        // Enable dynamic power down when no read is being performed and set read latency
498        // to CAS Latency + 2 - 1
499        EMIF0_REG(DDR_PHY_CTRL_1) = 0x00100007;
500        EMIF0_REG(DDR_PHY_CTRL_1_SHDW) = 0x00100007;
501
502        // Configure the AC timing characteristics
503        EMIF0_REG(SDRAM_TIM_1) = 0x0AAAD4DB;
504        EMIF0_REG(SDRAM_TIM_1_SHDW) = 0x0AAAD4DB;
505        EMIF0_REG(SDRAM_TIM_2) = 0x266B7FDA;
506        EMIF0_REG(SDRAM_TIM_2_SHDW) = 0x266B7FDA;
507        EMIF0_REG(SDRAM_TIM_3) = 0x501F867F;
508        EMIF0_REG(SDRAM_TIM_3_SHDW) = 0x501F867F;
509
510        // Set the refresh rate, 400,000,000 * 7.8 * 10^-6 = 3120 = 0x0C30
511        EMIF0_REG(SDRAM_REF_CTRL) = 0x00000C30;
512        // set the referesh rate shadow register to the same value as previous
513        EMIF0_REG(SDRAM_REF_CTRL_SHDW) = 0x00000C30;
514
515        // Configure the ZQ Calibration
516        EMIF0_REG(ZQ_CONFIG) = 0x50074BE4;
517
518        // Configure the SDRAM characteristics
519        reg |= SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 | SDRAM_CONFIG_REG_IBANK_POS_0 |
520                SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 | SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS |
521                SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 | SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE |
522                SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 | SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 |
523                SDRAM_CONFIG_REG_NARROW_MODE_16BIT | SDRAM_CONFIG_REG_CAS_LATENCY_6 |
524                SDRAM_CONFIG_REG_ROWSIZE_15BIT | SDRAM_CONFIG_REG_IBANK_8 |
525                SDRAM_CONFIG_REG_EBANK_1 | SDRAM_CONFIG_REG_PAGESIZE_1024_WORD;
526        EMIF0_REG(SDRAM_CONFIG) = reg;
527        CNTL_MODULE_REG(CONTROL_EMIF_SDRAM_CONFIG) = reg;
528
529        // Set the external bank position to 0
530        EMIF0_REG(SDRAM_CONFIG_2) |= SDRAM_CONFIG_2_REG_EBANK_POS_0;
531}
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