source: umon/ports/beagleboneblack/cpuio.c @ 0e24873

Last change on this file since 0e24873 was 0e24873, checked in by Jarielle Catbagan <jcatbagan93@…>, on Aug 4, 2015 at 6:03:22 PM

BBB: Migrate MMC0 clock enable from am335x_sd.c:sdInit() to cpuio.c:initCPUio()

The reason why the MMC0 clock enable has to be executed much earlier is a result of the invocation
of sdInstalled() in sd.h before sdInit(). Without this migration, an exception occurs since the
MMC0 interface has not been enabled before it is accessed by sdInstalled().

  • Property mode set to 100644
File size: 15.0 KB
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1#include "config.h"
2#include "stddefs.h"
3#include "cpuio.h"
4#include "genlib.h"
5#include "cache.h"
6#include "warmstart.h"
7#include "timer.h"
8#include "am335x.h"
9#include "uart16550.h"
10#include "cli.h"
11
12int
13getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
14{
15        *lo = ((48000000/16)/baud) & 0x00ff;
16        *hi = (((48000000/16)/baud) & 0xff00) >> 8;
17        return(0);
18}
19
20/* devInit():
21 * As a bare minimum, initialize the console UART here using the
22 * incoming 'baud' value as the baud rate.
23 */
24int
25devInit(int baud)
26{
27        return(0);
28}
29
30/* ConsoleBaudSet():
31 * Provide a means to change the baud rate of the running
32 * console interface.  If the incoming value is not a valid
33 * baud rate, then default to 9600.
34 * In the early stages of a new port this can be left empty.
35 * Return 0 if successful; else -1.
36 */
37/*int
38ConsoleBaudSet(int baud)
39{
40        // ADD_CODE_HERE
41        return(0);
42}*/
43
44/* target_console_empty():
45 * Target-specific portion of flush_console() in chario.c.
46 * This function returns 1 if there are no characters waiting to
47 * be put out on the UART; else return 0 indicating that the UART
48 * is still busy outputting characters from its FIFO.
49 * In the early stages of a new port this can simply return 1.
50 */
51/*int
52target_console_empty(void)
53{
54        // if (UART_OUTPUT_BUFFER_IS_EMPTY())  <- FIX CODE HERE
55                return(0);
56        return(1);
57}*/
58
59/* intsoff():
60 * Disable all system interrupts here and return a value that can
61 * be used by intsrestore() (later) to restore the interrupt state.
62 */
63ulong
64intsoff(void)
65{
66        ulong status = 0;
67
68        /* ADD_CODE_HERE */
69        return(status);
70}
71
72/* intsrestore():
73 * Re-establish system interrupts here by using the status value
74 * that was returned by an earlier call to intsoff().
75 */
76void
77intsrestore(ulong status)
78{
79        /* ADD_CODE_HERE */
80}
81
82/* cacheInitForTarget():
83 * Establish target specific function pointers and
84 * enable i-cache...
85 * Refer to $core/cache.c for a description of the function pointers.
86 * NOTE:
87 * If cache (either I or D or both) is enabled, then it is important
88 * that the appropriate cacheflush/invalidate function be established.
89 * This is very important because programs (i.e. cpu instructions) are
90 * transferred to memory using data memory accesses and could
91 * potentially result in cache coherency problems.
92 */
93void
94cacheInitForTarget(void)
95{
96        /* ADD_CODE_HERE */
97}
98
99/* target_reset():
100 * The default (absolute minimum) action to be taken by this function
101 * is to call monrestart(INITIALIZE).  It would be better if there was
102 * some target-specific function that would really cause the target
103 * to reset...
104 */
105void
106target_reset(void)
107{
108//      flushDcache(0,0);
109//      disableDcache();
110//      invalidateIcache(0,0);
111//      disableIcache();
112        monrestart(INITIALIZE);
113}
114
115/* Override the default exception handlers provided by the AM335x
116 * internal ROM code with uMon's custom exception handlers
117 */
118void
119ram_vector_install(void)
120{
121        extern unsigned long abort_data;
122        extern unsigned long abort_prefetch;
123        extern unsigned long undefined_instruction;
124        extern unsigned long software_interrupt;
125        extern unsigned long interrupt_request;
126        extern unsigned long fast_interrupt_request;
127        extern unsigned long not_assigned;
128
129        *(ulong **)0x4030ce24 = &undefined_instruction;
130        *(ulong **)0x4030ce28 = &software_interrupt;
131        *(ulong **)0x4030ce2c = &abort_prefetch;
132        *(ulong **)0x4030ce30 = &abort_data;
133        *(ulong **)0x4030ce34 = &not_assigned;
134        *(ulong **)0x4030ce38 = &interrupt_request;
135        *(ulong **)0x4030ce3c = &fast_interrupt_request;
136}
137
138void
139pinMuxInit(void)
140{
141        // Set pin mux configuration for UART0 RX/TX pins
142        CNTL_MODULE_REG(CONF_UART0_RXD) = SLEWSLOW | RX_ON |
143                PULL_OFF | MUXMODE_0;
144        CNTL_MODULE_REG(CONF_UART0_TXD) = SLEWSLOW | RX_OFF |
145                PULL_OFF | MUXMODE_0;
146
147        // Configure GPIO pins tied to four USR LEDS...
148        // GPIO1_21: USER0 LED (D2)
149        CNTL_MODULE_REG(CONF_GPMC_A5) = SLEWSLOW | RX_ON |
150                PULL_OFF | MUXMODE_7;
151        // GPIO1_22: USER1 LED (D3)
152        CNTL_MODULE_REG(CONF_GPMC_A6) = SLEWSLOW | RX_ON |
153                PULL_OFF | MUXMODE_7;
154        // GPIO1_23: USER2 LED (D4)
155        CNTL_MODULE_REG(CONF_GPMC_A7) = SLEWSLOW | RX_ON |
156                PULL_OFF | MUXMODE_7;
157        // GPIO1_24: USER3 LED (D5)
158        CNTL_MODULE_REG(CONF_GPMC_A8) = SLEWSLOW | RX_ON |
159                PULL_OFF | MUXMODE_7;
160
161        // Configure the pins for the MMC0 interface
162        CNTL_MODULE_REG(CONF_MMC0_DAT0) = RX_ON | PULL_ON |
163                PULLUP | MUXMODE_0;
164        CNTL_MODULE_REG(CONF_MMC0_DAT1) = RX_ON | PULL_ON |
165                PULLUP | MUXMODE_0;
166        CNTL_MODULE_REG(CONF_MMC0_DAT2) = RX_ON | PULL_ON |
167                PULLUP | MUXMODE_0;
168        CNTL_MODULE_REG(CONF_MMC0_DAT3) = RX_ON | PULL_ON |
169                PULLUP | MUXMODE_0;
170        CNTL_MODULE_REG(CONF_MMC0_CLK) = RX_ON | PULL_OFF |
171                MUXMODE_0;
172        CNTL_MODULE_REG(CONF_MMC0_CMD) = RX_ON | PULL_ON |
173                PULLUP | MUXMODE_0;
174        CNTL_MODULE_REG(CONF_SPI0_CS1) = RX_ON | PULL_ON |
175                PULLUP | MUXMODE_5;
176}
177
178void
179InitGPIO1(void)
180{
181        // GPIO_CTRL: Enable GPIO1 module
182        GPIO1_REG(0x130) = 0;
183
184        // GPIO_OE: 25-24 are outputs...
185        GPIO1_REG(0x134) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
186
187        // All LEDs off...
188        GPIO1_REG(0x13c) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
189}
190
191/* If any CPU IO wasn't initialized in reset.S, do it here...
192 * This just provides a "C-level" IO init opportunity.
193 */
194void
195initCPUio(void)
196{
197        ram_vector_install();
198
199        // Enable the control module:
200        CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
201
202        // Enable clock for UART0:
203        CM_WKUP_REG(CM_WKUP_UART0_CLKCTRL) |= 2;
204
205        // Enable clock for GPIO1:
206        CM_PER_REG(CM_PER_GPIO1_CLKCTRL) |= 2;
207
208        /* Enable MMC0 clocks */
209        CM_PER_REG(CM_PER_MMC0_CLKCTRL) |= CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE;
210        while (CM_PER_REG(CM_PER_MMC0_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
211
212        pinMuxInit();
213
214        InitUART(DEFAULT_BAUD_RATE);
215        InitGPIO1();
216
217        // Set UART0 mode to 16x
218        UART0_REG(UART_MDR1) &= ~7;
219}
220
221int
222led(int num, int on)
223{
224        unsigned long bit;
225
226        switch(num) {
227                case 0: // D0
228                        bit = USR0_LED;
229                        break;
230                case 1: // D1
231                        bit = USR1_LED;
232                        break;
233                case 2: // D2
234                        bit = USR2_LED;
235                        break;
236                case 3: // D3
237                        bit = USR3_LED;
238                        break;
239                default:
240                        return(-1);
241        }
242
243        // GPIO21-24:
244        if (on)
245            GPIO1_REG(0x13c) |= bit;
246        else
247            GPIO1_REG(0x13c) &= ~bit;
248        return(0);
249}
250
251void
252target_blinkled(void)
253{
254#if INCLUDE_BLINKLED
255        static uint8_t ledstate;
256        static struct elapsed_tmr tmr;
257
258#define STATLED_ON()    led(0,1)
259#define STATLED_OFF()   led(0,0)
260#ifndef BLINKON_MSEC
261#define BLINKON_MSEC 10000
262#define BLINKOFF_MSEC 10000
263#endif
264
265        switch(ledstate) {
266                case 0:
267                        startElapsedTimer(&tmr,BLINKON_MSEC);
268                        STATLED_ON();
269                        ledstate = 1;
270                        break;
271                case 1:
272                        if(msecElapsed(&tmr)) {
273                                STATLED_OFF();
274                                ledstate = 2;
275                                startElapsedTimer(&tmr,BLINKOFF_MSEC);
276                        }
277                        break;
278                case 2:
279                        if(msecElapsed(&tmr)) {
280                                STATLED_ON();
281                                ledstate = 1;
282                                startElapsedTimer(&tmr,BLINKON_MSEC);
283                        }
284                        break;
285        }
286#endif
287}
288
289void
290mpu_pll_init(void)
291{
292        uint32_t cm_clkmode_dpll_mpu;
293        uint32_t cm_clksel_dpll_mpu;
294        uint32_t cm_div_m2_dpll_mpu;
295
296        // Put MPU PLL in MN Bypass mode
297        cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
298        cm_clkmode_dpll_mpu &= ~0x00000007;
299        cm_clkmode_dpll_mpu |= 0x00000004;
300        CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
301        // Wait for MPU PLL to enter MN Bypass mode
302        while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000101) != 0x00000100);
303
304        // Set the ARM core frequency to 1 GHz
305        cm_clksel_dpll_mpu = CM_WKUP_REG(CM_CLKSEL_DPLL_MPU);
306        cm_clksel_dpll_mpu &= ~0x0007FF7F;
307        cm_clksel_dpll_mpu |= 1000 << 8;
308        cm_clksel_dpll_mpu |= 23;
309        CM_WKUP_REG(CM_CLKSEL_DPLL_MPU) = cm_clksel_dpll_mpu;
310        cm_div_m2_dpll_mpu = CM_WKUP_REG(CM_DIV_M2_DPLL_MPU);
311        cm_div_m2_dpll_mpu &= ~0x0000001F;
312        cm_div_m2_dpll_mpu |= 0x00000001;
313        CM_WKUP_REG(CM_DIV_M2_DPLL_MPU) = cm_div_m2_dpll_mpu;
314
315        // Lock MPU PLL
316        cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
317        cm_clkmode_dpll_mpu &= ~0x00000007;
318        cm_clkmode_dpll_mpu |= 0x00000007;
319        CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
320        // Wait for MPU PLL to lock
321        while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000001) != 0x00000001);
322}
323
324void
325core_pll_init(void)
326{
327        uint32_t cm_clkmode_dpll_core;
328        uint32_t cm_clksel_dpll_core;
329        uint32_t cm_div_m4_dpll_core;
330        uint32_t cm_div_m5_dpll_core;
331        uint32_t cm_div_m6_dpll_core;
332
333        // Put Core PLL in MN Bypass mode
334        cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
335        cm_clkmode_dpll_core &= ~0x00000007;
336        cm_clkmode_dpll_core |= 0x00000004;
337        CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
338        // Wait for Core PLL to enter MN Bypass mode
339        while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000101) != 0x00000100);
340
341        // Configure the multiplier and divider
342        cm_clksel_dpll_core = CM_WKUP_REG(CM_CLKSEL_DPLL_CORE);
343        cm_clksel_dpll_core &= ~0x0007FF7F;
344        cm_clksel_dpll_core |= 1000 << 8;
345        cm_clksel_dpll_core |= 23;
346        CM_WKUP_REG(CM_CLKSEL_DPLL_CORE) = cm_clksel_dpll_core;
347        // Configure the M4, M5, and M6 dividers
348        cm_div_m4_dpll_core = CM_WKUP_REG(CM_DIV_M4_DPLL_CORE);
349        cm_div_m4_dpll_core &= ~0x0000001F;
350        cm_div_m4_dpll_core |= 10;
351        CM_WKUP_REG(CM_DIV_M4_DPLL_CORE) = cm_div_m4_dpll_core;
352        cm_div_m5_dpll_core = CM_WKUP_REG(CM_DIV_M5_DPLL_CORE);
353        cm_div_m5_dpll_core &= ~0x0000001F;
354        cm_div_m5_dpll_core |= 8;
355        CM_WKUP_REG(CM_DIV_M5_DPLL_CORE) = cm_div_m5_dpll_core;
356        cm_div_m6_dpll_core = CM_WKUP_REG(CM_DIV_M6_DPLL_CORE);
357        cm_div_m6_dpll_core &= ~0x0000001F;
358        cm_div_m6_dpll_core |= 4;
359        CM_WKUP_REG(CM_DIV_M6_DPLL_CORE) = cm_div_m6_dpll_core;
360
361        // Lock Core PLL
362        cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
363        cm_clkmode_dpll_core &= ~0x00000007;
364        cm_clkmode_dpll_core |= 0x00000007;
365        CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
366        // Wait for Core PLL to lock
367        while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000001) != 0x00000001);
368}
369
370void
371ddr_pll_init(void)
372{
373        uint32_t cm_clkmode_dpll_ddr;
374        uint32_t cm_clksel_dpll_ddr;
375        uint32_t cm_div_m2_dpll_ddr;
376
377        // Put DDR PLL in MN Bypass mode
378        cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
379        cm_clkmode_dpll_ddr &= ~0x00000007;
380        cm_clkmode_dpll_ddr |= 0x00000004;
381        CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
382        // Wait for DDR PLL to enter MN Bypass mode
383        while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000101) != 0x00000100);
384
385        // Set the DDR frequency to 400 MHz
386        cm_clksel_dpll_ddr = CM_WKUP_REG(CM_CLKSEL_DPLL_DDR);
387        cm_clksel_dpll_ddr &= ~0x0007FF7F;
388        cm_clksel_dpll_ddr |= 400 << 8;
389        cm_clksel_dpll_ddr |= 23;
390        CM_WKUP_REG(CM_CLKSEL_DPLL_DDR) = cm_clksel_dpll_ddr;
391        // Set M2 divider
392        cm_div_m2_dpll_ddr = CM_WKUP_REG(CM_DIV_M2_DPLL_DDR);
393        cm_div_m2_dpll_ddr &= ~0x0000001F;
394        cm_div_m2_dpll_ddr |= 1;
395        CM_WKUP_REG(CM_DIV_M2_DPLL_DDR) = cm_div_m2_dpll_ddr;
396
397        // Lock the DDR PLL
398        cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
399        cm_clkmode_dpll_ddr &= ~0x00000007;
400        cm_clkmode_dpll_ddr |= 0x00000007;
401        CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
402        // Wait for DDR PLL to lock
403        while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x00000001);
404}
405
406void
407per_pll_init(void)
408{
409        uint32_t cm_clkmode_dpll_per;
410        uint32_t cm_clksel_dpll_per;
411        uint32_t cm_div_m2_dpll_per;
412
413        // Put Per PLL in MN Bypass mode
414        cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
415        cm_clkmode_dpll_per &= ~0x00000007;
416        cm_clkmode_dpll_per |= 0x00000004;
417        CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
418        // Wait for Per PLL to enter MN Bypass mode
419        while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000101) != 0x00000100);
420
421        // Configure the multiplier and divider
422        cm_clksel_dpll_per = CM_WKUP_REG(CM_CLKSEL_DPLL_PER);
423        cm_clksel_dpll_per &= ~0xFF0FFFFF;
424        cm_clksel_dpll_per |= CM_CLKSEL_DPLL_PER_DPLL_SD_DIV | CM_CLKSEL_DPLL_PER_DPLL_MULT |
425                CM_CLKSEL_DPLL_PER_DPLL_DIV;
426        CM_WKUP_REG(CM_CLKSEL_DPLL_PER) = cm_clksel_dpll_per;
427        // Set M2 divider
428        cm_div_m2_dpll_per = CM_WKUP_REG(CM_DIV_M2_DPLL_PER);
429        cm_div_m2_dpll_per &= ~0x0000007F;
430        cm_div_m2_dpll_per |= 5;
431        CM_WKUP_REG(CM_DIV_M2_DPLL_PER) = cm_div_m2_dpll_per;
432
433        // Lock the Per PLL
434        cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
435        cm_clkmode_dpll_per &= ~0x00000007;
436        cm_clkmode_dpll_per |= 0x00000007;
437        CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
438        // Wait for Per PLL to lock
439        while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000001) != 0x00000001);
440}
441
442void
443pll_init(void)
444{
445        mpu_pll_init();
446        core_pll_init();
447        ddr_pll_init();
448        per_pll_init();
449}
450
451void
452ddr_init(void)
453{
454        uint32_t reg;
455
456        // Enable the control module:
457        CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
458
459        // Enable EMIF module
460        reg = CM_PER_REG(CM_PER_EMIF_CLKCTRL);
461        reg &= ~3;
462        reg |= 2;
463        CM_PER_REG(CM_PER_EMIF_CLKCTRL) = reg;
464        while ((CM_PER_REG(CM_PER_L3_CLKSTCTRL) & 0x00000004) != 0x00000004);
465
466        // Configure VTP control
467        CNTL_MODULE_REG(VTP_CTRL) |= 0x00000040;
468        CNTL_MODULE_REG(VTP_CTRL) &= ~1;
469        CNTL_MODULE_REG(VTP_CTRL) |= 1;
470        // Wait for VTP control to be ready
471        while ((CNTL_MODULE_REG(VTP_CTRL) & 0x00000020) != 0x00000020);
472
473        // Configure the DDR PHY CMDx/DATAx registers
474        DDR_PHY_REG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
475        DDR_PHY_REG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
476        DDR_PHY_REG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
477        DDR_PHY_REG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
478        DDR_PHY_REG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
479        DDR_PHY_REG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
480
481        DDR_PHY_REG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
482        DDR_PHY_REG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
483        DDR_PHY_REG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
484        DDR_PHY_REG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
485
486        DDR_PHY_REG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
487        DDR_PHY_REG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
488        DDR_PHY_REG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
489        DDR_PHY_REG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
490
491        CNTL_MODULE_REG(DDR_CMD0_IOCTRL) = 0x018B;
492        CNTL_MODULE_REG(DDR_CMD1_IOCTRL) = 0x018B;
493        CNTL_MODULE_REG(DDR_CMD2_IOCTRL) = 0x018B;
494        CNTL_MODULE_REG(DDR_DATA0_IOCTRL) = 0x018B;
495        CNTL_MODULE_REG(DDR_DATA1_IOCTRL) = 0x018B;
496
497        CNTL_MODULE_REG(DDR_IO_CTRL) &= ~0x10000000;
498
499        CNTL_MODULE_REG(DDR_CKE_CTRL) |= 0x00000001;
500
501        // Enable dynamic power down when no read is being performed and set read latency
502        // to CAS Latency + 2 - 1
503        EMIF0_REG(DDR_PHY_CTRL_1) = 0x00100007;
504        EMIF0_REG(DDR_PHY_CTRL_1_SHDW) = 0x00100007;
505
506        // Configure the AC timing characteristics
507        EMIF0_REG(SDRAM_TIM_1) = 0x0AAAD4DB;
508        EMIF0_REG(SDRAM_TIM_1_SHDW) = 0x0AAAD4DB;
509        EMIF0_REG(SDRAM_TIM_2) = 0x266B7FDA;
510        EMIF0_REG(SDRAM_TIM_2_SHDW) = 0x266B7FDA;
511        EMIF0_REG(SDRAM_TIM_3) = 0x501F867F;
512        EMIF0_REG(SDRAM_TIM_3_SHDW) = 0x501F867F;
513
514        // Set the refresh rate, 400,000,000 * 7.8 * 10^-6 = 3120 = 0x0C30
515        EMIF0_REG(SDRAM_REF_CTRL) = 0x00000C30;
516        // set the referesh rate shadow register to the same value as previous
517        EMIF0_REG(SDRAM_REF_CTRL_SHDW) = 0x00000C30;
518
519        // Configure the ZQ Calibration
520        EMIF0_REG(ZQ_CONFIG) = 0x50074BE4;
521
522        // Configure the SDRAM characteristics
523        reg |= SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 | SDRAM_CONFIG_REG_IBANK_POS_0 |
524                SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 | SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS |
525                SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 | SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE |
526                SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 | SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 |
527                SDRAM_CONFIG_REG_NARROW_MODE_16BIT | SDRAM_CONFIG_REG_CAS_LATENCY_6 |
528                SDRAM_CONFIG_REG_ROWSIZE_15BIT | SDRAM_CONFIG_REG_IBANK_8 |
529                SDRAM_CONFIG_REG_EBANK_1 | SDRAM_CONFIG_REG_PAGESIZE_1024_WORD;
530        EMIF0_REG(SDRAM_CONFIG) = reg;
531        CNTL_MODULE_REG(CONTROL_EMIF_SDRAM_CONFIG) = reg;
532
533        // Set the external bank position to 0
534        EMIF0_REG(SDRAM_CONFIG_2) |= SDRAM_CONFIG_2_REG_EBANK_POS_0;
535}
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