source: umon/ports/beagleboneblack/cpuio.c @ 723a2e2

Last change on this file since 723a2e2 was 723a2e2, checked in by Ed Sutter <edsutterjr@…>, on Jul 18, 2015 at 3:28:03 PM

fix uninitialized variable issue in mpu_pll_init()

  • Property mode set to 100644
File size: 14.3 KB
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[dee5246]1#include "config.h"
[11c6677]2#include "stddefs.h"
[dee5246]3#include "cpuio.h"
4#include "genlib.h"
[11c6677]5#include "cache.h"
[dee5246]6#include "warmstart.h"
[11c6677]7#include "timer.h"
[d77ed25]8#include "am335x.h"
9#include "uart16550.h"
[b8ffb40]10#include "cli.h"
[dee5246]11
12int
13getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
14{
15        *lo = ((48000000/16)/baud) & 0x00ff;
16        *hi = (((48000000/16)/baud) & 0xff00) >> 8;
17        return(0);
18}
19
[11c6677]20/* devInit():
21 * As a bare minimum, initialize the console UART here using the
22 * incoming 'baud' value as the baud rate.
23 */
[40b5966]24int
[dee5246]25devInit(int baud)
26{
[40b5966]27        return(0);
[dee5246]28}
29
[11c6677]30/* ConsoleBaudSet():
31 * Provide a means to change the baud rate of the running
32 * console interface.  If the incoming value is not a valid
33 * baud rate, then default to 9600.
34 * In the early stages of a new port this can be left empty.
35 * Return 0 if successful; else -1.
[dee5246]36 */
[11c6677]37/*int
38ConsoleBaudSet(int baud)
[dee5246]39{
[11c6677]40        // ADD_CODE_HERE
41        return(0);
42}*/
43
44/* target_console_empty():
45 * Target-specific portion of flush_console() in chario.c.
46 * This function returns 1 if there are no characters waiting to
47 * be put out on the UART; else return 0 indicating that the UART
48 * is still busy outputting characters from its FIFO.
49 * In the early stages of a new port this can simply return 1.
50 */
51/*int
52target_console_empty(void)
[dee5246]53{
[11c6677]54        // if (UART_OUTPUT_BUFFER_IS_EMPTY())  <- FIX CODE HERE
55                return(0);
56        return(1);
57}*/
58
59/* intsoff():
60 * Disable all system interrupts here and return a value that can
61 * be used by intsrestore() (later) to restore the interrupt state.
[dee5246]62 */
[11c6677]63ulong
64intsoff(void)
[dee5246]65{
[d6c7226]66        ulong status = 0;
[dee5246]67
[11c6677]68        /* ADD_CODE_HERE */
69        return(status);
[dee5246]70}
71
[11c6677]72/* intsrestore():
73 * Re-establish system interrupts here by using the status value
74 * that was returned by an earlier call to intsoff().
75 */
[dee5246]76void
[11c6677]77intsrestore(ulong status)
[dee5246]78{
[11c6677]79        /* ADD_CODE_HERE */
[dee5246]80}
81
[11c6677]82/* cacheInitForTarget():
83 * Establish target specific function pointers and
84 * enable i-cache...
85 * Refer to $core/cache.c for a description of the function pointers.
86 * NOTE:
87 * If cache (either I or D or both) is enabled, then it is important
88 * that the appropriate cacheflush/invalidate function be established.
89 * This is very important because programs (i.e. cpu instructions) are
90 * transferred to memory using data memory accesses and could
91 * potentially result in cache coherency problems.
[dee5246]92 */
[11c6677]93void
94cacheInitForTarget(void)
[dee5246]95{
[11c6677]96        /* ADD_CODE_HERE */
[dee5246]97}
98
[11c6677]99/* target_reset():
100 * The default (absolute minimum) action to be taken by this function
101 * is to call monrestart(INITIALIZE).  It would be better if there was
102 * some target-specific function that would really cause the target
103 * to reset...
[dee5246]104 */
105void
[11c6677]106target_reset(void)
[dee5246]107{
[11c6677]108//      flushDcache(0,0);
109//      disableDcache();
110//      invalidateIcache(0,0);
111//      disableIcache();
112        monrestart(INITIALIZE);
[dee5246]113}
114
[a5f94c8]115/* Override the default exception handlers provided by the AM335x
116 * internal ROM code with uMon's custom exception handlers
117 */
118void
119ram_vector_install(void)
120{
121        extern unsigned long abort_data;
122        extern unsigned long abort_prefetch;
123        extern unsigned long undefined_instruction;
124        extern unsigned long software_interrupt;
125        extern unsigned long interrupt_request;
126        extern unsigned long fast_interrupt_request;
127        extern unsigned long not_assigned;
128
129        *(ulong **)0x4030ce24 = &undefined_instruction;
130        *(ulong **)0x4030ce28 = &software_interrupt;
131        *(ulong **)0x4030ce2c = &abort_prefetch;
132        *(ulong **)0x4030ce30 = &abort_data;
133        *(ulong **)0x4030ce34 = &not_assigned;
134        *(ulong **)0x4030ce38 = &interrupt_request;
135        *(ulong **)0x4030ce3c = &fast_interrupt_request;
136}
137
[d77ed25]138void
139pinMuxInit(void)
140{
[82f6941]141        // Set pin mux configuration for UART0 RX/TX pins
142        CNTL_MODULE_REG(CONF_UART0_RXD) = SLEWSLOW | RX_ON |
143                PULL_OFF | MUXMODE_0;
144        CNTL_MODULE_REG(CONF_UART0_TXD) = SLEWSLOW | RX_OFF |
145                PULL_OFF | MUXMODE_0;
[b8ffb40]146
[82f6941]147        // Configure GPIO pins tied to four USR LEDS...
148        // GPIO1_21: USER0 LED (D2)
149        CNTL_MODULE_REG(CONF_GPMC_A5) = SLEWSLOW | RX_ON |
150                PULL_OFF | MUXMODE_7;
151        // GPIO1_22: USER1 LED (D3)
152        CNTL_MODULE_REG(CONF_GPMC_A6) = SLEWSLOW | RX_ON |
153                PULL_OFF | MUXMODE_7;
154        // GPIO1_23: USER2 LED (D4)
155        CNTL_MODULE_REG(CONF_GPMC_A7) = SLEWSLOW | RX_ON |
156                PULL_OFF | MUXMODE_7;
157        // GPIO1_24: USER3 LED (D5)
158        CNTL_MODULE_REG(CONF_GPMC_A8) = SLEWSLOW | RX_ON |
159                PULL_OFF | MUXMODE_7;
[b8ffb40]160}
161
162void
163InitGPIO1(void)
164{
[82f6941]165        // GPIO_CTRL: Enable GPIO1 module
[b8ffb40]166        GPIO1_REG(0x130) = 0;
167
[82f6941]168        // GPIO_OE: 25-24 are outputs...
[b8ffb40]169        GPIO1_REG(0x134) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
170
[82f6941]171        // All LEDs off...
[b8ffb40]172        GPIO1_REG(0x13c) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
[d77ed25]173}
174
[11c6677]175/* If any CPU IO wasn't initialized in reset.S, do it here...
176 * This just provides a "C-level" IO init opportunity.
[dee5246]177 */
178void
[11c6677]179initCPUio(void)
[dee5246]180{
[a5f94c8]181        ram_vector_install();
[d77ed25]182
[82f6941]183        // Enable the control module:
184        CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
[b8ffb40]185
[82f6941]186        // Enable clock for UART0:
187        CM_WKUP_REG(CM_WKUP_UART0_CLKCTRL) |= 2;
[b8ffb40]188
[82f6941]189        // Enable clock for GPIO1:
[b9f0b9e]190        CM_PER_REG(CM_PER_GPIO1_CLKCTRL) |= 2;
[d77ed25]191
[82f6941]192        pinMuxInit();
[d77ed25]193
[82f6941]194        InitUART(DEFAULT_BAUD_RATE);
[b8ffb40]195        InitGPIO1();
196
[82f6941]197        // Set UART0 mode to 16x
198        UART0_REG(UART_MDR1) &= ~7;
[b8ffb40]199}
200
201int
202led(int num, int on)
203{
204        unsigned long bit;
205
206        switch(num) {
207                case 0: // D0
208                        bit = USR0_LED;
209                        break;
210                case 1: // D1
211                        bit = USR1_LED;
212                        break;
213                case 2: // D2
214                        bit = USR2_LED;
215                        break;
216                case 3: // D3
217                        bit = USR3_LED;
218                        break;
219                default:
220                        return(-1);
221        }
222
[82f6941]223        // GPIO21-24:
[b8ffb40]224        if (on)
225            GPIO1_REG(0x13c) |= bit;
226        else
227            GPIO1_REG(0x13c) &= ~bit;
228        return(0);
229}
230
231void
232target_blinkled(void)
233{
234#if INCLUDE_BLINKLED
235        static uint8_t ledstate;
236        static struct elapsed_tmr tmr;
[d77ed25]237
[b8ffb40]238#define STATLED_ON()    led(0,1)
239#define STATLED_OFF()   led(0,0)
240#ifndef BLINKON_MSEC
241#define BLINKON_MSEC 10000
242#define BLINKOFF_MSEC 10000
243#endif
[d77ed25]244
[b8ffb40]245        switch(ledstate) {
246                case 0:
247                        startElapsedTimer(&tmr,BLINKON_MSEC);
248                        STATLED_ON();
249                        ledstate = 1;
250                        break;
251                case 1:
252                        if(msecElapsed(&tmr)) {
253                                STATLED_OFF();
254                                ledstate = 2;
255                                startElapsedTimer(&tmr,BLINKOFF_MSEC);
256                        }
257                        break;
258                case 2:
259                        if(msecElapsed(&tmr)) {
260                                STATLED_ON();
261                                ledstate = 1;
262                                startElapsedTimer(&tmr,BLINKON_MSEC);
263                        }
264                        break;
265        }
266#endif
[dee5246]267}
[273af8f]268
269void
270mpu_pll_init(void)
271{
272        uint32_t cm_clkmode_dpll_mpu;
273        uint32_t cm_clksel_dpll_mpu;
274        uint32_t cm_div_m2_dpll_mpu;
275
276        // Put MPU PLL in MN Bypass mode
277        cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
278        cm_clkmode_dpll_mpu &= ~0x00000007;
279        cm_clkmode_dpll_mpu |= 0x00000004;
280        CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
281        // Wait for MPU PLL to enter MN Bypass mode
282        while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000101) != 0x00000100);
283
284        // Set the ARM core frequency to 1 GHz
[723a2e2]285        cm_clksel_dpll_mpu = CM_WKUP_REG(CM_CLKSEL_DPLL_MPU);
[273af8f]286        cm_clksel_dpll_mpu &= ~0x0007FF7F;
287        cm_clksel_dpll_mpu |= 1000 << 8;
288        cm_clksel_dpll_mpu |= 23;
289        CM_WKUP_REG(CM_CLKSEL_DPLL_MPU) = cm_clksel_dpll_mpu;
290        cm_div_m2_dpll_mpu = CM_WKUP_REG(CM_DIV_M2_DPLL_MPU);
291        cm_div_m2_dpll_mpu &= ~0x0000001F;
292        cm_div_m2_dpll_mpu |= 0x00000001;
293        CM_WKUP_REG(CM_DIV_M2_DPLL_MPU) = cm_div_m2_dpll_mpu;
294
295        // Lock MPU PLL
296        cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
297        cm_clkmode_dpll_mpu &= ~0x00000007;
298        cm_clkmode_dpll_mpu |= 0x00000007;
299        CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
300        // Wait for MPU PLL to lock
301        while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000001) != 0x00000001);
302}
303
304void
305core_pll_init(void)
306{
307        uint32_t cm_clkmode_dpll_core;
308        uint32_t cm_clksel_dpll_core;
309        uint32_t cm_div_m4_dpll_core;
310        uint32_t cm_div_m5_dpll_core;
311        uint32_t cm_div_m6_dpll_core;
312
313        // Put Core PLL in MN Bypass mode
314        cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
315        cm_clkmode_dpll_core &= ~0x00000007;
316        cm_clkmode_dpll_core |= 0x00000004;
317        CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
318        // Wait for Core PLL to enter MN Bypass mode
319        while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000101) != 0x00000100);
320
321        // Configure the multiplier and divider
322        cm_clksel_dpll_core = CM_WKUP_REG(CM_CLKSEL_DPLL_CORE);
323        cm_clksel_dpll_core &= ~0x0007FF7F;
324        cm_clksel_dpll_core |= 1000 << 8;
325        cm_clksel_dpll_core |= 23;
326        CM_WKUP_REG(CM_CLKSEL_DPLL_CORE) = cm_clksel_dpll_core;
327        // Configure the M4, M5, and M6 dividers
328        cm_div_m4_dpll_core = CM_WKUP_REG(CM_DIV_M4_DPLL_CORE);
329        cm_div_m4_dpll_core &= ~0x0000001F;
330        cm_div_m4_dpll_core |= 10;
331        CM_WKUP_REG(CM_DIV_M4_DPLL_CORE) = cm_div_m4_dpll_core;
332        cm_div_m5_dpll_core = CM_WKUP_REG(CM_DIV_M5_DPLL_CORE);
333        cm_div_m5_dpll_core &= ~0x0000001F;
334        cm_div_m5_dpll_core |= 8;
335        CM_WKUP_REG(CM_DIV_M5_DPLL_CORE) = cm_div_m5_dpll_core;
336        cm_div_m6_dpll_core = CM_WKUP_REG(CM_DIV_M6_DPLL_CORE);
337        cm_div_m6_dpll_core &= ~0x0000001F;
338        cm_div_m6_dpll_core |= 4;
339        CM_WKUP_REG(CM_DIV_M6_DPLL_CORE) = cm_div_m6_dpll_core;
340
341        // Lock Core PLL
342        cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
343        cm_clkmode_dpll_core &= ~0x00000007;
344        cm_clkmode_dpll_core |= 0x00000007;
345        CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
346        // Wait for Core PLL to lock
347        while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000001) != 0x00000001);
348}
349
350void
351ddr_pll_init(void)
352{
353        uint32_t cm_clkmode_dpll_ddr;
354        uint32_t cm_clksel_dpll_ddr;
355        uint32_t cm_div_m2_dpll_ddr;
356
357        // Put DDR PLL in MN Bypass mode
358        cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
359        cm_clkmode_dpll_ddr &= ~0x00000007;
360        cm_clkmode_dpll_ddr |= 0x00000004;
361        CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
362        // Wait for DDR PLL to enter MN Bypass mode
363        while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000101) != 0x00000100);
364
365        // Set the DDR frequency to 400 MHz
366        cm_clksel_dpll_ddr = CM_WKUP_REG(CM_CLKSEL_DPLL_DDR);
367        cm_clksel_dpll_ddr &= ~0x0007FF7F;
368        cm_clksel_dpll_ddr |= 400 << 8;
369        cm_clksel_dpll_ddr |= 23;
370        CM_WKUP_REG(CM_CLKSEL_DPLL_DDR) = cm_clksel_dpll_ddr;
371        // Set M2 divider
372        cm_div_m2_dpll_ddr = CM_WKUP_REG(CM_DIV_M2_DPLL_DDR);
373        cm_div_m2_dpll_ddr &= ~0x0000001F;
374        cm_div_m2_dpll_ddr |= 1;
375        CM_WKUP_REG(CM_DIV_M2_DPLL_DDR) = cm_div_m2_dpll_ddr;
376
377        // Lock the DDR PLL
378        cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
379        cm_clkmode_dpll_ddr &= ~0x00000007;
380        cm_clkmode_dpll_ddr |= 0x00000007;
381        CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
382        // Wait for DDR PLL to lock
383        while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x00000001);
384}
385
386void
387per_pll_init(void)
388{
389        uint32_t cm_clkmode_dpll_per;
390        uint32_t cm_clksel_dpll_per;
391        uint32_t cm_div_m2_dpll_per;
392
393        // Put Per PLL in MN Bypass mode
394        cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
395        cm_clkmode_dpll_per &= ~0x00000007;
396        cm_clkmode_dpll_per |= 0x00000004;
397        CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
398        // Wait for Per PLL to enter MN Bypass mode
399        while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000101) != 0x00000100);
400
401        // Configure the multiplier and divider
402        cm_clksel_dpll_per = CM_WKUP_REG(CM_CLKSEL_DPLL_PER);
403        cm_clksel_dpll_per &= ~0xFF0FFFFF;
404        cm_clksel_dpll_per |= CM_CLKSEL_DPLL_PER_DPLL_SD_DIV | CM_CLKSEL_DPLL_PER_DPLL_MULT |
405                CM_CLKSEL_DPLL_PER_DPLL_DIV;
406        CM_WKUP_REG(CM_CLKSEL_DPLL_PER) = cm_clksel_dpll_per;
407        // Set M2 divider
408        cm_div_m2_dpll_per = CM_WKUP_REG(CM_DIV_M2_DPLL_PER);
409        cm_div_m2_dpll_per &= ~0x0000007F;
410        cm_div_m2_dpll_per |= 5;
411        CM_WKUP_REG(CM_DIV_M2_DPLL_PER) = cm_div_m2_dpll_per;
412
413        // Lock the Per PLL
414        cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
415        cm_clkmode_dpll_per &= ~0x00000007;
416        cm_clkmode_dpll_per |= 0x00000007;
417        CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
418        // Wait for Per PLL to lock
419        while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000001) != 0x00000001);
420}
421
422void
423pll_init(void)
424{
425        mpu_pll_init();
426        core_pll_init();
427        ddr_pll_init();
428        per_pll_init();
429}
430
431void
432ddr_init(void)
433{
434        uint32_t reg;
435
436        // Enable the control module:
437        CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
438
439        // Enable EMIF module
440        reg = CM_PER_REG(CM_PER_EMIF_CLKCTRL);
441        reg &= ~3;
442        reg |= 2;
443        CM_PER_REG(CM_PER_EMIF_CLKCTRL) = reg;
444        while ((CM_PER_REG(CM_PER_L3_CLKSTCTRL) & 0x00000004) != 0x00000004);
445
446        // Configure VTP control
447        CNTL_MODULE_REG(VTP_CTRL) |= 0x00000040;
448        CNTL_MODULE_REG(VTP_CTRL) &= ~1;
449        CNTL_MODULE_REG(VTP_CTRL) |= 1;
450        // Wait for VTP control to be ready
451        while ((CNTL_MODULE_REG(VTP_CTRL) & 0x00000020) != 0x00000020);
452
453        // Configure the DDR PHY CMDx/DATAx registers
454        DDR_PHY_REG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
455        DDR_PHY_REG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
456        DDR_PHY_REG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
457        DDR_PHY_REG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
458        DDR_PHY_REG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
459        DDR_PHY_REG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
460
461        DDR_PHY_REG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
462        DDR_PHY_REG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
463        DDR_PHY_REG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
464        DDR_PHY_REG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
465
466        DDR_PHY_REG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
467        DDR_PHY_REG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
468        DDR_PHY_REG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
469        DDR_PHY_REG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
470
471        CNTL_MODULE_REG(DDR_CMD0_IOCTRL) = 0x018B;
472        CNTL_MODULE_REG(DDR_CMD1_IOCTRL) = 0x018B;
473        CNTL_MODULE_REG(DDR_CMD2_IOCTRL) = 0x018B;
474        CNTL_MODULE_REG(DDR_DATA0_IOCTRL) = 0x018B;
475        CNTL_MODULE_REG(DDR_DATA1_IOCTRL) = 0x018B;
476
477        CNTL_MODULE_REG(DDR_IO_CTRL) &= ~0x10000000;
478
479        CNTL_MODULE_REG(DDR_CKE_CTRL) |= 0x00000001;
480
481        // Enable dynamic power down when no read is being performed and set read latency
482        // to CAS Latency + 2 - 1
483        EMIF0_REG(DDR_PHY_CTRL_1) = 0x00100007;
484        EMIF0_REG(DDR_PHY_CTRL_1_SHDW) = 0x00100007;
485
486        // Configure the AC timing characteristics
487        EMIF0_REG(SDRAM_TIM_1) = 0x0AAAD4DB;
488        EMIF0_REG(SDRAM_TIM_1_SHDW) = 0x0AAAD4DB;
489        EMIF0_REG(SDRAM_TIM_2) = 0x266B7FDA;
490        EMIF0_REG(SDRAM_TIM_2_SHDW) = 0x266B7FDA;
491        EMIF0_REG(SDRAM_TIM_3) = 0x501F867F;
492        EMIF0_REG(SDRAM_TIM_3_SHDW) = 0x501F867F;
493
494        // Set the refresh rate, 400,000,000 * 7.8 * 10^-6 = 3120 = 0x0C30
495        EMIF0_REG(SDRAM_REF_CTRL) = 0x00000C30;
496        // set the referesh rate shadow register to the same value as previous
497        EMIF0_REG(SDRAM_REF_CTRL_SHDW) = 0x00000C30;
498
499        // Configure the ZQ Calibration
500        EMIF0_REG(ZQ_CONFIG) = 0x50074BE4;
501
502        // Configure the SDRAM characteristics
503        reg |= SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 | SDRAM_CONFIG_REG_IBANK_POS_0 |
504                SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 | SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS |
505                SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 | SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE |
506                SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 | SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 |
507                SDRAM_CONFIG_REG_NARROW_MODE_16BIT | SDRAM_CONFIG_REG_CAS_LATENCY_6 |
508                SDRAM_CONFIG_REG_ROWSIZE_15BIT | SDRAM_CONFIG_REG_IBANK_8 |
509                SDRAM_CONFIG_REG_EBANK_1 | SDRAM_CONFIG_REG_PAGESIZE_1024_WORD;
510        EMIF0_REG(SDRAM_CONFIG) = reg;
511        CNTL_MODULE_REG(CONTROL_EMIF_SDRAM_CONFIG) = reg;
512
513        // Set the external bank position to 0
514        EMIF0_REG(SDRAM_CONFIG_2) |= SDRAM_CONFIG_2_REG_EBANK_POS_0;
515}
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