[dee5246] | 1 | #include "config.h" |
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[11c6677] | 2 | #include "stddefs.h" |
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[dee5246] | 3 | #include "cpuio.h" |
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| 4 | #include "genlib.h" |
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[11c6677] | 5 | #include "cache.h" |
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[dee5246] | 6 | #include "warmstart.h" |
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[11c6677] | 7 | #include "timer.h" |
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[d77ed25] | 8 | #include "am335x.h" |
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| 9 | #include "uart16550.h" |
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[b8ffb40] | 10 | #include "cli.h" |
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[dee5246] | 11 | |
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| 12 | int |
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| 13 | getUartDivisor(int baud, unsigned char *hi, unsigned char *lo) |
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| 14 | { |
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| 15 | *lo = ((48000000/16)/baud) & 0x00ff; |
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| 16 | *hi = (((48000000/16)/baud) & 0xff00) >> 8; |
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| 17 | return(0); |
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| 18 | } |
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| 19 | |
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[11c6677] | 20 | /* devInit(): |
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| 21 | * As a bare minimum, initialize the console UART here using the |
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| 22 | * incoming 'baud' value as the baud rate. |
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| 23 | */ |
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[40b5966] | 24 | int |
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[dee5246] | 25 | devInit(int baud) |
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| 26 | { |
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[40b5966] | 27 | return(0); |
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[dee5246] | 28 | } |
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| 29 | |
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[11c6677] | 30 | /* ConsoleBaudSet(): |
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| 31 | * Provide a means to change the baud rate of the running |
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| 32 | * console interface. If the incoming value is not a valid |
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| 33 | * baud rate, then default to 9600. |
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| 34 | * In the early stages of a new port this can be left empty. |
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| 35 | * Return 0 if successful; else -1. |
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[dee5246] | 36 | */ |
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[11c6677] | 37 | /*int |
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| 38 | ConsoleBaudSet(int baud) |
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[dee5246] | 39 | { |
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[11c6677] | 40 | // ADD_CODE_HERE |
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| 41 | return(0); |
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| 42 | }*/ |
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| 43 | |
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| 44 | /* target_console_empty(): |
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| 45 | * Target-specific portion of flush_console() in chario.c. |
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| 46 | * This function returns 1 if there are no characters waiting to |
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| 47 | * be put out on the UART; else return 0 indicating that the UART |
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| 48 | * is still busy outputting characters from its FIFO. |
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| 49 | * In the early stages of a new port this can simply return 1. |
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| 50 | */ |
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| 51 | /*int |
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| 52 | target_console_empty(void) |
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[dee5246] | 53 | { |
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[11c6677] | 54 | // if (UART_OUTPUT_BUFFER_IS_EMPTY()) <- FIX CODE HERE |
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| 55 | return(0); |
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| 56 | return(1); |
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| 57 | }*/ |
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| 58 | |
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| 59 | /* intsoff(): |
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| 60 | * Disable all system interrupts here and return a value that can |
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| 61 | * be used by intsrestore() (later) to restore the interrupt state. |
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[dee5246] | 62 | */ |
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[11c6677] | 63 | ulong |
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| 64 | intsoff(void) |
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[dee5246] | 65 | { |
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[d6c7226] | 66 | ulong status = 0; |
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[dee5246] | 67 | |
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[11c6677] | 68 | /* ADD_CODE_HERE */ |
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| 69 | return(status); |
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[dee5246] | 70 | } |
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| 71 | |
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[11c6677] | 72 | /* intsrestore(): |
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| 73 | * Re-establish system interrupts here by using the status value |
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| 74 | * that was returned by an earlier call to intsoff(). |
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| 75 | */ |
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[dee5246] | 76 | void |
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[11c6677] | 77 | intsrestore(ulong status) |
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[dee5246] | 78 | { |
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[11c6677] | 79 | /* ADD_CODE_HERE */ |
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[dee5246] | 80 | } |
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| 81 | |
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[11c6677] | 82 | /* cacheInitForTarget(): |
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| 83 | * Establish target specific function pointers and |
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| 84 | * enable i-cache... |
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| 85 | * Refer to $core/cache.c for a description of the function pointers. |
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| 86 | * NOTE: |
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| 87 | * If cache (either I or D or both) is enabled, then it is important |
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| 88 | * that the appropriate cacheflush/invalidate function be established. |
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| 89 | * This is very important because programs (i.e. cpu instructions) are |
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| 90 | * transferred to memory using data memory accesses and could |
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| 91 | * potentially result in cache coherency problems. |
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[dee5246] | 92 | */ |
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[11c6677] | 93 | void |
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| 94 | cacheInitForTarget(void) |
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[dee5246] | 95 | { |
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[11c6677] | 96 | /* ADD_CODE_HERE */ |
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[dee5246] | 97 | } |
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| 98 | |
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[11c6677] | 99 | /* target_reset(): |
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| 100 | * The default (absolute minimum) action to be taken by this function |
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| 101 | * is to call monrestart(INITIALIZE). It would be better if there was |
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| 102 | * some target-specific function that would really cause the target |
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| 103 | * to reset... |
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[dee5246] | 104 | */ |
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| 105 | void |
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[11c6677] | 106 | target_reset(void) |
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[dee5246] | 107 | { |
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[11c6677] | 108 | // flushDcache(0,0); |
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| 109 | // disableDcache(); |
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| 110 | // invalidateIcache(0,0); |
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| 111 | // disableIcache(); |
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| 112 | monrestart(INITIALIZE); |
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[dee5246] | 113 | } |
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| 114 | |
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[a5f94c8] | 115 | /* Override the default exception handlers provided by the AM335x |
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| 116 | * internal ROM code with uMon's custom exception handlers |
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| 117 | */ |
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| 118 | void |
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| 119 | ram_vector_install(void) |
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| 120 | { |
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| 121 | extern unsigned long abort_data; |
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| 122 | extern unsigned long abort_prefetch; |
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| 123 | extern unsigned long undefined_instruction; |
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| 124 | extern unsigned long software_interrupt; |
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| 125 | extern unsigned long interrupt_request; |
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| 126 | extern unsigned long fast_interrupt_request; |
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| 127 | extern unsigned long not_assigned; |
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| 128 | |
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| 129 | *(ulong **)0x4030ce24 = &undefined_instruction; |
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| 130 | *(ulong **)0x4030ce28 = &software_interrupt; |
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| 131 | *(ulong **)0x4030ce2c = &abort_prefetch; |
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| 132 | *(ulong **)0x4030ce30 = &abort_data; |
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| 133 | *(ulong **)0x4030ce34 = ¬_assigned; |
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| 134 | *(ulong **)0x4030ce38 = &interrupt_request; |
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| 135 | *(ulong **)0x4030ce3c = &fast_interrupt_request; |
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| 136 | } |
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| 137 | |
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[d77ed25] | 138 | void |
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| 139 | pinMuxInit(void) |
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| 140 | { |
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[82f6941] | 141 | // Set pin mux configuration for UART0 RX/TX pins |
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| 142 | CNTL_MODULE_REG(CONF_UART0_RXD) = SLEWSLOW | RX_ON | |
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| 143 | PULL_OFF | MUXMODE_0; |
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| 144 | CNTL_MODULE_REG(CONF_UART0_TXD) = SLEWSLOW | RX_OFF | |
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| 145 | PULL_OFF | MUXMODE_0; |
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[b8ffb40] | 146 | |
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[82f6941] | 147 | // Configure GPIO pins tied to four USR LEDS... |
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| 148 | // GPIO1_21: USER0 LED (D2) |
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| 149 | CNTL_MODULE_REG(CONF_GPMC_A5) = SLEWSLOW | RX_ON | |
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| 150 | PULL_OFF | MUXMODE_7; |
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| 151 | // GPIO1_22: USER1 LED (D3) |
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| 152 | CNTL_MODULE_REG(CONF_GPMC_A6) = SLEWSLOW | RX_ON | |
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| 153 | PULL_OFF | MUXMODE_7; |
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| 154 | // GPIO1_23: USER2 LED (D4) |
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| 155 | CNTL_MODULE_REG(CONF_GPMC_A7) = SLEWSLOW | RX_ON | |
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| 156 | PULL_OFF | MUXMODE_7; |
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| 157 | // GPIO1_24: USER3 LED (D5) |
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| 158 | CNTL_MODULE_REG(CONF_GPMC_A8) = SLEWSLOW | RX_ON | |
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| 159 | PULL_OFF | MUXMODE_7; |
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[5a75bc2] | 160 | |
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| 161 | // Configure the pins for the MMC0 interface |
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| 162 | CNTL_MODULE_REG(CONF_MMC0_DAT0) = RX_ON | PULL_ON | |
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| 163 | PULLUP | MUXMODE_0; |
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| 164 | CNTL_MODULE_REG(CONF_MMC0_DAT1) = RX_ON | PULL_ON | |
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| 165 | PULLUP | MUXMODE_0; |
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| 166 | CNTL_MODULE_REG(CONF_MMC0_DAT2) = RX_ON | PULL_ON | |
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| 167 | PULLUP | MUXMODE_0; |
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| 168 | CNTL_MODULE_REG(CONF_MMC0_DAT3) = RX_ON | PULL_ON | |
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| 169 | PULLUP | MUXMODE_0; |
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| 170 | CNTL_MODULE_REG(CONF_MMC0_CLK) = RX_ON | PULL_OFF | |
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| 171 | MUXMODE_0; |
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| 172 | CNTL_MODULE_REG(CONF_MMC0_CMD) = RX_ON | PULL_ON | |
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| 173 | PULLUP | MUXMODE_0; |
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| 174 | CNTL_MODULE_REG(CONF_SPI0_CS1) = RX_ON | PULL_ON | |
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| 175 | PULLUP | MUXMODE_5; |
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[b8ffb40] | 176 | } |
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| 177 | |
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| 178 | void |
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| 179 | InitGPIO1(void) |
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| 180 | { |
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[82f6941] | 181 | // GPIO_CTRL: Enable GPIO1 module |
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[b8ffb40] | 182 | GPIO1_REG(0x130) = 0; |
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| 183 | |
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[82f6941] | 184 | // GPIO_OE: 25-24 are outputs... |
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[b8ffb40] | 185 | GPIO1_REG(0x134) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED); |
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| 186 | |
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[82f6941] | 187 | // All LEDs off... |
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[b8ffb40] | 188 | GPIO1_REG(0x13c) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED); |
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[d77ed25] | 189 | } |
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| 190 | |
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[11c6677] | 191 | /* If any CPU IO wasn't initialized in reset.S, do it here... |
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| 192 | * This just provides a "C-level" IO init opportunity. |
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[dee5246] | 193 | */ |
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| 194 | void |
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[11c6677] | 195 | initCPUio(void) |
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[dee5246] | 196 | { |
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[a5f94c8] | 197 | ram_vector_install(); |
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[d77ed25] | 198 | |
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[82f6941] | 199 | // Enable the control module: |
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| 200 | CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2; |
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[b8ffb40] | 201 | |
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[82f6941] | 202 | // Enable clock for UART0: |
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| 203 | CM_WKUP_REG(CM_WKUP_UART0_CLKCTRL) |= 2; |
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[b8ffb40] | 204 | |
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[82f6941] | 205 | // Enable clock for GPIO1: |
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[b9f0b9e] | 206 | CM_PER_REG(CM_PER_GPIO1_CLKCTRL) |= 2; |
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[d77ed25] | 207 | |
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[0e24873] | 208 | /* Enable MMC0 clocks */ |
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| 209 | CM_PER_REG(CM_PER_MMC0_CLKCTRL) |= CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE; |
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| 210 | while (CM_PER_REG(CM_PER_MMC0_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST); |
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| 211 | |
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[82f6941] | 212 | pinMuxInit(); |
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[d77ed25] | 213 | |
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[82f6941] | 214 | InitUART(DEFAULT_BAUD_RATE); |
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[b8ffb40] | 215 | InitGPIO1(); |
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| 216 | |
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[82f6941] | 217 | // Set UART0 mode to 16x |
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| 218 | UART0_REG(UART_MDR1) &= ~7; |
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[b8ffb40] | 219 | } |
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| 220 | |
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| 221 | int |
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| 222 | led(int num, int on) |
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| 223 | { |
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| 224 | unsigned long bit; |
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| 225 | |
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| 226 | switch(num) { |
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| 227 | case 0: // D0 |
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| 228 | bit = USR0_LED; |
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| 229 | break; |
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| 230 | case 1: // D1 |
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| 231 | bit = USR1_LED; |
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| 232 | break; |
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| 233 | case 2: // D2 |
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| 234 | bit = USR2_LED; |
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| 235 | break; |
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| 236 | case 3: // D3 |
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| 237 | bit = USR3_LED; |
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| 238 | break; |
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| 239 | default: |
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| 240 | return(-1); |
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| 241 | } |
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| 242 | |
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[82f6941] | 243 | // GPIO21-24: |
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[b8ffb40] | 244 | if (on) |
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| 245 | GPIO1_REG(0x13c) |= bit; |
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| 246 | else |
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| 247 | GPIO1_REG(0x13c) &= ~bit; |
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| 248 | return(0); |
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| 249 | } |
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| 250 | |
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| 251 | void |
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| 252 | target_blinkled(void) |
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| 253 | { |
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| 254 | #if INCLUDE_BLINKLED |
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| 255 | static uint8_t ledstate; |
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| 256 | static struct elapsed_tmr tmr; |
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[d77ed25] | 257 | |
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[b8ffb40] | 258 | #define STATLED_ON() led(0,1) |
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| 259 | #define STATLED_OFF() led(0,0) |
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| 260 | #ifndef BLINKON_MSEC |
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| 261 | #define BLINKON_MSEC 10000 |
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| 262 | #define BLINKOFF_MSEC 10000 |
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| 263 | #endif |
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[d77ed25] | 264 | |
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[b8ffb40] | 265 | switch(ledstate) { |
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| 266 | case 0: |
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| 267 | startElapsedTimer(&tmr,BLINKON_MSEC); |
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| 268 | STATLED_ON(); |
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| 269 | ledstate = 1; |
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| 270 | break; |
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| 271 | case 1: |
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| 272 | if(msecElapsed(&tmr)) { |
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| 273 | STATLED_OFF(); |
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| 274 | ledstate = 2; |
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| 275 | startElapsedTimer(&tmr,BLINKOFF_MSEC); |
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| 276 | } |
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| 277 | break; |
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| 278 | case 2: |
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| 279 | if(msecElapsed(&tmr)) { |
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| 280 | STATLED_ON(); |
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| 281 | ledstate = 1; |
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| 282 | startElapsedTimer(&tmr,BLINKON_MSEC); |
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| 283 | } |
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| 284 | break; |
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| 285 | } |
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| 286 | #endif |
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[dee5246] | 287 | } |
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[273af8f] | 288 | |
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| 289 | void |
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| 290 | mpu_pll_init(void) |
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| 291 | { |
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| 292 | uint32_t cm_clkmode_dpll_mpu; |
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| 293 | uint32_t cm_clksel_dpll_mpu; |
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| 294 | uint32_t cm_div_m2_dpll_mpu; |
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| 295 | |
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| 296 | // Put MPU PLL in MN Bypass mode |
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| 297 | cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU); |
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| 298 | cm_clkmode_dpll_mpu &= ~0x00000007; |
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| 299 | cm_clkmode_dpll_mpu |= 0x00000004; |
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| 300 | CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu; |
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| 301 | // Wait for MPU PLL to enter MN Bypass mode |
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| 302 | while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000101) != 0x00000100); |
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| 303 | |
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| 304 | // Set the ARM core frequency to 1 GHz |
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[723a2e2] | 305 | cm_clksel_dpll_mpu = CM_WKUP_REG(CM_CLKSEL_DPLL_MPU); |
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[273af8f] | 306 | cm_clksel_dpll_mpu &= ~0x0007FF7F; |
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| 307 | cm_clksel_dpll_mpu |= 1000 << 8; |
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| 308 | cm_clksel_dpll_mpu |= 23; |
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| 309 | CM_WKUP_REG(CM_CLKSEL_DPLL_MPU) = cm_clksel_dpll_mpu; |
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| 310 | cm_div_m2_dpll_mpu = CM_WKUP_REG(CM_DIV_M2_DPLL_MPU); |
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| 311 | cm_div_m2_dpll_mpu &= ~0x0000001F; |
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| 312 | cm_div_m2_dpll_mpu |= 0x00000001; |
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| 313 | CM_WKUP_REG(CM_DIV_M2_DPLL_MPU) = cm_div_m2_dpll_mpu; |
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| 314 | |
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| 315 | // Lock MPU PLL |
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| 316 | cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU); |
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| 317 | cm_clkmode_dpll_mpu &= ~0x00000007; |
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| 318 | cm_clkmode_dpll_mpu |= 0x00000007; |
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| 319 | CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu; |
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| 320 | // Wait for MPU PLL to lock |
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| 321 | while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000001) != 0x00000001); |
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| 322 | } |
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| 323 | |
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| 324 | void |
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| 325 | core_pll_init(void) |
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| 326 | { |
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| 327 | uint32_t cm_clkmode_dpll_core; |
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| 328 | uint32_t cm_clksel_dpll_core; |
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| 329 | uint32_t cm_div_m4_dpll_core; |
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| 330 | uint32_t cm_div_m5_dpll_core; |
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| 331 | uint32_t cm_div_m6_dpll_core; |
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| 332 | |
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| 333 | // Put Core PLL in MN Bypass mode |
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| 334 | cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE); |
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| 335 | cm_clkmode_dpll_core &= ~0x00000007; |
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| 336 | cm_clkmode_dpll_core |= 0x00000004; |
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| 337 | CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core; |
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| 338 | // Wait for Core PLL to enter MN Bypass mode |
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| 339 | while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000101) != 0x00000100); |
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| 340 | |
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| 341 | // Configure the multiplier and divider |
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| 342 | cm_clksel_dpll_core = CM_WKUP_REG(CM_CLKSEL_DPLL_CORE); |
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| 343 | cm_clksel_dpll_core &= ~0x0007FF7F; |
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| 344 | cm_clksel_dpll_core |= 1000 << 8; |
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| 345 | cm_clksel_dpll_core |= 23; |
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| 346 | CM_WKUP_REG(CM_CLKSEL_DPLL_CORE) = cm_clksel_dpll_core; |
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| 347 | // Configure the M4, M5, and M6 dividers |
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| 348 | cm_div_m4_dpll_core = CM_WKUP_REG(CM_DIV_M4_DPLL_CORE); |
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| 349 | cm_div_m4_dpll_core &= ~0x0000001F; |
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| 350 | cm_div_m4_dpll_core |= 10; |
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| 351 | CM_WKUP_REG(CM_DIV_M4_DPLL_CORE) = cm_div_m4_dpll_core; |
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| 352 | cm_div_m5_dpll_core = CM_WKUP_REG(CM_DIV_M5_DPLL_CORE); |
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| 353 | cm_div_m5_dpll_core &= ~0x0000001F; |
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| 354 | cm_div_m5_dpll_core |= 8; |
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| 355 | CM_WKUP_REG(CM_DIV_M5_DPLL_CORE) = cm_div_m5_dpll_core; |
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| 356 | cm_div_m6_dpll_core = CM_WKUP_REG(CM_DIV_M6_DPLL_CORE); |
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| 357 | cm_div_m6_dpll_core &= ~0x0000001F; |
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| 358 | cm_div_m6_dpll_core |= 4; |
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| 359 | CM_WKUP_REG(CM_DIV_M6_DPLL_CORE) = cm_div_m6_dpll_core; |
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| 360 | |
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| 361 | // Lock Core PLL |
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| 362 | cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE); |
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| 363 | cm_clkmode_dpll_core &= ~0x00000007; |
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| 364 | cm_clkmode_dpll_core |= 0x00000007; |
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| 365 | CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core; |
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| 366 | // Wait for Core PLL to lock |
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| 367 | while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000001) != 0x00000001); |
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| 368 | } |
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| 369 | |
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| 370 | void |
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| 371 | ddr_pll_init(void) |
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| 372 | { |
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| 373 | uint32_t cm_clkmode_dpll_ddr; |
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| 374 | uint32_t cm_clksel_dpll_ddr; |
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| 375 | uint32_t cm_div_m2_dpll_ddr; |
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| 376 | |
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| 377 | // Put DDR PLL in MN Bypass mode |
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| 378 | cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR); |
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| 379 | cm_clkmode_dpll_ddr &= ~0x00000007; |
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| 380 | cm_clkmode_dpll_ddr |= 0x00000004; |
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| 381 | CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr; |
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| 382 | // Wait for DDR PLL to enter MN Bypass mode |
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| 383 | while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000101) != 0x00000100); |
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| 384 | |
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| 385 | // Set the DDR frequency to 400 MHz |
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| 386 | cm_clksel_dpll_ddr = CM_WKUP_REG(CM_CLKSEL_DPLL_DDR); |
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| 387 | cm_clksel_dpll_ddr &= ~0x0007FF7F; |
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| 388 | cm_clksel_dpll_ddr |= 400 << 8; |
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| 389 | cm_clksel_dpll_ddr |= 23; |
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| 390 | CM_WKUP_REG(CM_CLKSEL_DPLL_DDR) = cm_clksel_dpll_ddr; |
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| 391 | // Set M2 divider |
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| 392 | cm_div_m2_dpll_ddr = CM_WKUP_REG(CM_DIV_M2_DPLL_DDR); |
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| 393 | cm_div_m2_dpll_ddr &= ~0x0000001F; |
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| 394 | cm_div_m2_dpll_ddr |= 1; |
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| 395 | CM_WKUP_REG(CM_DIV_M2_DPLL_DDR) = cm_div_m2_dpll_ddr; |
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| 396 | |
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| 397 | // Lock the DDR PLL |
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| 398 | cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR); |
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| 399 | cm_clkmode_dpll_ddr &= ~0x00000007; |
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| 400 | cm_clkmode_dpll_ddr |= 0x00000007; |
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| 401 | CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr; |
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| 402 | // Wait for DDR PLL to lock |
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| 403 | while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x00000001); |
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| 404 | } |
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| 405 | |
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| 406 | void |
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| 407 | per_pll_init(void) |
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| 408 | { |
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| 409 | uint32_t cm_clkmode_dpll_per; |
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| 410 | uint32_t cm_clksel_dpll_per; |
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| 411 | uint32_t cm_div_m2_dpll_per; |
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| 412 | |
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| 413 | // Put Per PLL in MN Bypass mode |
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| 414 | cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER); |
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| 415 | cm_clkmode_dpll_per &= ~0x00000007; |
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| 416 | cm_clkmode_dpll_per |= 0x00000004; |
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| 417 | CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per; |
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| 418 | // Wait for Per PLL to enter MN Bypass mode |
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| 419 | while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000101) != 0x00000100); |
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| 420 | |
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| 421 | // Configure the multiplier and divider |
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| 422 | cm_clksel_dpll_per = CM_WKUP_REG(CM_CLKSEL_DPLL_PER); |
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| 423 | cm_clksel_dpll_per &= ~0xFF0FFFFF; |
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| 424 | cm_clksel_dpll_per |= CM_CLKSEL_DPLL_PER_DPLL_SD_DIV | CM_CLKSEL_DPLL_PER_DPLL_MULT | |
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| 425 | CM_CLKSEL_DPLL_PER_DPLL_DIV; |
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| 426 | CM_WKUP_REG(CM_CLKSEL_DPLL_PER) = cm_clksel_dpll_per; |
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| 427 | // Set M2 divider |
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| 428 | cm_div_m2_dpll_per = CM_WKUP_REG(CM_DIV_M2_DPLL_PER); |
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| 429 | cm_div_m2_dpll_per &= ~0x0000007F; |
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| 430 | cm_div_m2_dpll_per |= 5; |
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| 431 | CM_WKUP_REG(CM_DIV_M2_DPLL_PER) = cm_div_m2_dpll_per; |
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| 432 | |
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| 433 | // Lock the Per PLL |
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| 434 | cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER); |
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| 435 | cm_clkmode_dpll_per &= ~0x00000007; |
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| 436 | cm_clkmode_dpll_per |= 0x00000007; |
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| 437 | CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per; |
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| 438 | // Wait for Per PLL to lock |
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| 439 | while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000001) != 0x00000001); |
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| 440 | } |
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| 441 | |
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| 442 | void |
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| 443 | pll_init(void) |
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| 444 | { |
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| 445 | mpu_pll_init(); |
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| 446 | core_pll_init(); |
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| 447 | ddr_pll_init(); |
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| 448 | per_pll_init(); |
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| 449 | } |
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| 450 | |
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| 451 | void |
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| 452 | ddr_init(void) |
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| 453 | { |
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| 454 | uint32_t reg; |
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| 455 | |
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| 456 | // Enable the control module: |
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| 457 | CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2; |
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| 458 | |
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| 459 | // Enable EMIF module |
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| 460 | reg = CM_PER_REG(CM_PER_EMIF_CLKCTRL); |
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| 461 | reg &= ~3; |
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| 462 | reg |= 2; |
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| 463 | CM_PER_REG(CM_PER_EMIF_CLKCTRL) = reg; |
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| 464 | while ((CM_PER_REG(CM_PER_L3_CLKSTCTRL) & 0x00000004) != 0x00000004); |
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| 465 | |
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| 466 | // Configure VTP control |
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| 467 | CNTL_MODULE_REG(VTP_CTRL) |= 0x00000040; |
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| 468 | CNTL_MODULE_REG(VTP_CTRL) &= ~1; |
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| 469 | CNTL_MODULE_REG(VTP_CTRL) |= 1; |
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| 470 | // Wait for VTP control to be ready |
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| 471 | while ((CNTL_MODULE_REG(VTP_CTRL) & 0x00000020) != 0x00000020); |
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| 472 | |
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| 473 | // Configure the DDR PHY CMDx/DATAx registers |
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| 474 | DDR_PHY_REG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80; |
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| 475 | DDR_PHY_REG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0; |
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| 476 | DDR_PHY_REG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80; |
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| 477 | DDR_PHY_REG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0; |
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| 478 | DDR_PHY_REG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80; |
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| 479 | DDR_PHY_REG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0; |
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| 480 | |
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| 481 | DDR_PHY_REG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A; |
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| 482 | DDR_PHY_REG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45; |
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| 483 | DDR_PHY_REG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C; |
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| 484 | DDR_PHY_REG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96; |
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| 485 | |
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| 486 | DDR_PHY_REG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A; |
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| 487 | DDR_PHY_REG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45; |
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| 488 | DDR_PHY_REG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C; |
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| 489 | DDR_PHY_REG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96; |
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| 490 | |
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| 491 | CNTL_MODULE_REG(DDR_CMD0_IOCTRL) = 0x018B; |
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| 492 | CNTL_MODULE_REG(DDR_CMD1_IOCTRL) = 0x018B; |
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| 493 | CNTL_MODULE_REG(DDR_CMD2_IOCTRL) = 0x018B; |
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| 494 | CNTL_MODULE_REG(DDR_DATA0_IOCTRL) = 0x018B; |
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| 495 | CNTL_MODULE_REG(DDR_DATA1_IOCTRL) = 0x018B; |
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| 496 | |
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| 497 | CNTL_MODULE_REG(DDR_IO_CTRL) &= ~0x10000000; |
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| 498 | |
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| 499 | CNTL_MODULE_REG(DDR_CKE_CTRL) |= 0x00000001; |
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| 500 | |
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| 501 | // Enable dynamic power down when no read is being performed and set read latency |
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| 502 | // to CAS Latency + 2 - 1 |
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| 503 | EMIF0_REG(DDR_PHY_CTRL_1) = 0x00100007; |
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| 504 | EMIF0_REG(DDR_PHY_CTRL_1_SHDW) = 0x00100007; |
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| 505 | |
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| 506 | // Configure the AC timing characteristics |
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| 507 | EMIF0_REG(SDRAM_TIM_1) = 0x0AAAD4DB; |
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| 508 | EMIF0_REG(SDRAM_TIM_1_SHDW) = 0x0AAAD4DB; |
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| 509 | EMIF0_REG(SDRAM_TIM_2) = 0x266B7FDA; |
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| 510 | EMIF0_REG(SDRAM_TIM_2_SHDW) = 0x266B7FDA; |
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| 511 | EMIF0_REG(SDRAM_TIM_3) = 0x501F867F; |
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| 512 | EMIF0_REG(SDRAM_TIM_3_SHDW) = 0x501F867F; |
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| 513 | |
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| 514 | // Set the refresh rate, 400,000,000 * 7.8 * 10^-6 = 3120 = 0x0C30 |
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| 515 | EMIF0_REG(SDRAM_REF_CTRL) = 0x00000C30; |
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| 516 | // set the referesh rate shadow register to the same value as previous |
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| 517 | EMIF0_REG(SDRAM_REF_CTRL_SHDW) = 0x00000C30; |
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| 518 | |
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| 519 | // Configure the ZQ Calibration |
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| 520 | EMIF0_REG(ZQ_CONFIG) = 0x50074BE4; |
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| 521 | |
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| 522 | // Configure the SDRAM characteristics |
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| 523 | reg |= SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 | SDRAM_CONFIG_REG_IBANK_POS_0 | |
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| 524 | SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 | SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS | |
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| 525 | SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 | SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE | |
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| 526 | SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 | SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 | |
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| 527 | SDRAM_CONFIG_REG_NARROW_MODE_16BIT | SDRAM_CONFIG_REG_CAS_LATENCY_6 | |
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| 528 | SDRAM_CONFIG_REG_ROWSIZE_15BIT | SDRAM_CONFIG_REG_IBANK_8 | |
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| 529 | SDRAM_CONFIG_REG_EBANK_1 | SDRAM_CONFIG_REG_PAGESIZE_1024_WORD; |
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| 530 | EMIF0_REG(SDRAM_CONFIG) = reg; |
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| 531 | CNTL_MODULE_REG(CONTROL_EMIF_SDRAM_CONFIG) = reg; |
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| 532 | |
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| 533 | // Set the external bank position to 0 |
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| 534 | EMIF0_REG(SDRAM_CONFIG_2) |= SDRAM_CONFIG_2_REG_EBANK_POS_0; |
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| 535 | } |
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