| 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @brief AM335x Register Base Addresses and Offsets |
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| 5 | * |
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| 6 | * @ingroup am335x |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (C) 2015 Jarielle Catbagan <jcatbagan93@gmail.com> |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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| 14 | * http://www.apache.org/licenses/LICENSE-2.0 |
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| 15 | * |
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| 16 | * |
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| 17 | * Description: This file contains register base addresses and offsets as |
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| 18 | * well as access macros for the AM335x on-chip peripherals. Peripherals |
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| 19 | * not used by Umon have not been test (and may not be defined). Use |
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| 20 | * these defines with caution! |
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| 21 | */ |
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| 22 | |
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| 23 | #ifndef AM335X_H |
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| 24 | #define AM335X_H |
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| 25 | |
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| 26 | #include "bits.h" |
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| 27 | |
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| 28 | |
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| 29 | /*===========================================================================*/ |
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| 30 | /* AM335x device identification and feature enumeration */ |
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| 31 | /*===========================================================================*/ |
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| 32 | #define AM335X_DEVICE_IDENTIFICATION 0x44E10600 |
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| 33 | #define AM335X_DEVICE_FEATURE 0x44E10604 |
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| 34 | /*===========================================================================*/ |
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| 35 | |
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| 36 | |
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| 37 | /*===========================================================================*/ |
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| 38 | /* L3 and L4 Interconnects */ |
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| 39 | /*===========================================================================*/ |
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| 40 | #define L3F_CFG_REGS_BASE 0x44000000 |
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| 41 | #define L3S_CFG_REGS_BASE 0x44800000 |
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| 42 | #define L4_WKUP_BASE 0x44C00000 |
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| 43 | #define L4_PER_BASE 0x48000000 |
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| 44 | #define L4_FAST_BASE 0x4A000000 |
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| 45 | /*===========================================================================*/ |
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| 46 | |
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| 47 | |
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| 48 | /*===========================================================================*/ |
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| 49 | /* EMIF0 Configuration Registers */ |
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| 50 | /*===========================================================================*/ |
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| 51 | #define EMIF0_BASE 0x4C000000 |
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| 52 | #define EMIF0_REG(_x_) *(vulong *)(EMIF0_BASE + _x_) |
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| 53 | /*---------------------------------------------------------------------------*/ |
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| 54 | /* EMIFO Register offsets */ |
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| 55 | #define EMIF_MOD_ID_REV 0x0000 |
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| 56 | #define STATUS 0x0004 |
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| 57 | #define SDRAM_CONFIG 0x0008 |
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| 58 | #define SDRAM_CONFIG_2 0x000C |
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| 59 | #define SDRAM_REF_CTRL 0x0010 |
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| 60 | #define SDRAM_REF_CTRL_SHDW 0x0014 |
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| 61 | #define SDRAM_TIM_1 0x0018 |
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| 62 | #define SDRAM_TIM_1_SHDW 0x001C |
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| 63 | #define SDRAM_TIM_2 0x0020 |
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| 64 | #define SDRAM_TIM_2_SHDW 0x0024 |
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| 65 | #define SDRAM_TIM_3 0x0028 |
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| 66 | #define SDRAM_TIM_3_SHDW 0x002C |
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| 67 | #define PWR_MGMT_CTRL 0x0038 |
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| 68 | #define PWR_MGMT_CTRL_SHDW 0x003C |
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| 69 | #define INTERFACE_CONFIG 0x0054 |
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| 70 | #define INTERFACE_CONFIG_VAL_1 0x0058 |
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| 71 | #define INTERFACE_CONFIG_VAL_2 0x005C |
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| 72 | #define PERF_CNT_1 0x0080 |
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| 73 | #define PERF_CNT_2 0x0084 |
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| 74 | #define PERF_CNT_CFG 0x0088 |
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| 75 | #define PERF_CNT_SEL 0x008C |
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| 76 | #define PERF_CNT_TIM 0x0090 |
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| 77 | #define READ_IDLE_CTRL 0x0098 |
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| 78 | #define READ_IDLE_CTRL_SHDW 0x009C |
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| 79 | #define IRQSTATUS_RAW_SYS 0x00A4 |
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| 80 | #define IRQSTATUS_SYS 0x00AC |
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| 81 | #define IRQENABLE_SET_SYS 0x00B4 |
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| 82 | #define IRQENABLE_CLR_SYS 0x00BC |
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| 83 | #define ZQ_CONFIG 0x00C8 |
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| 84 | #define RW_LVL_RAMP_WNDW 0x00D4 |
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| 85 | #define RW_LVL_RAMP_CTRL 0x00D8 |
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| 86 | #define RW_LVL_CTRL 0x00DC |
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| 87 | #define DDR_PHY_CTRL_1 0x00E4 |
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| 88 | #define DDR_PHY_CTRL_1_SHDW 0x00E8 |
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| 89 | #define PRIORITY_TO_CLASS_SRVC_MAP 0x0100 |
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| 90 | #define CONN_ID_TO_CLASS_SRVC_1_MAP 0x0104 |
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| 91 | #define CONN_ID_TO_CLASS_SRVC_2_MAP 0x0108 |
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| 92 | #define RW_EXEC_THRESHOLD 0x0120 |
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| 93 | /* Register fields and values */ |
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| 94 | #define SDRAM_CONFIG_REG_SDRAM_TYPE 0xE0000000 |
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| 95 | #define SDRAM_CONFIG_REG_SDRAM_TYPE_DDR1 0x00000000 |
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| 96 | #define SDRAM_CONFIG_REG_SDRAM_TYPE_LPDDR1 0x20000000 |
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| 97 | #define SDRAM_CONFIG_REG_SDRAM_TYPE_DDR2 0x40000000 |
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| 98 | #define SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 0x60000000 |
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| 99 | #define SDRAM_CONFIG_REG_IBANK_POS 0x18000000 |
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| 100 | #define SDRAM_CONFIG_REG_IBANK_POS_0 0x00000000 |
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| 101 | #define SDRAM_CONFIG_REG_IBANK_POS_1 0x08000000 |
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| 102 | #define SDRAM_CONFIG_REG_IBANK_POS_2 0x10000000 |
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| 103 | #define SDRAM_CONFIG_REG_IBANK_POS_3 0x18000000 |
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| 104 | #define SDRAM_CONFIG_REG_DDR_TERM 0x07000000 |
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| 105 | #define SDRAM_CONFIG_REG_DDR_TERM_DISABLE 0x00000000 |
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| 106 | #define SDRAM_CONFIG_REG_DDR_TERM_DDR2_75OHM 0x01000000 |
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| 107 | #define SDRAM_CONFIG_REG_DDR_TERM_DDR2_150OHM 0x02000000 |
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| 108 | #define SDRAM_CONFIG_REG_DDR_TERM_DDR2_50OHM 0x03000000 |
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| 109 | #define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 0x01000000 |
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| 110 | #define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_2 0x02000000 |
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| 111 | #define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_6 0x03000000 |
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| 112 | #define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_12 0x04000000 |
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| 113 | #define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_8 0x05000000 |
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| 114 | #define SDRAM_CONFIG_REG_DDR2_DDQS 0x00800000 |
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| 115 | #define SDRAM_CONFIG_REG_DDR2_DDQS_SINGLE_DQS 0x00000000 |
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| 116 | #define SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS 0x00800000 |
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| 117 | #define SDRAM_CONFIG_REG_DYN_ODT 0x00600000 |
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| 118 | #define SDRAM_CONFIG_REG_DYN_ODT_DISABLE 0x00000000 |
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| 119 | #define SDRAM_CONFIG_REG_DYN_ODT_RZQ_4 0x00200000 |
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| 120 | #define SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 0x00400000 |
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| 121 | #define SDRAM_CONFIG_REG_DDR_DISABLE_DLL 0x00100000 |
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| 122 | #define SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE 0x00000000 |
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| 123 | #define SDRAM_CONFIG_REG_DDR_DISABLE_DLL_DISABLE 0x00100000 |
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| 124 | #define SDRAM_CONFIG_REG_SDRAM_DRIVE 0x000C0000 |
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| 125 | #define SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 0x00000000 |
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| 126 | #define SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_7 0x00040000 |
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| 127 | #define SDRAM_CONFIG_REG_CAS_WR_LATENCY 0x00030000 |
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| 128 | #define SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 0x00000000 |
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| 129 | #define SDRAM_CONFIG_REG_CAS_WR_LATENCY_6 0x00010000 |
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| 130 | #define SDRAM_CONFIG_REG_CAS_WR_LATENCY_7 0x00020000 |
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| 131 | #define SDRAM_CONFIG_REG_CAS_WR_LATENCY_8 0x00030000 |
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| 132 | #define SDRAM_CONFIG_REG_NARROW_MODE 0x0000C000 |
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| 133 | #define SDRAM_CONFIG_REG_NARROW_MODE_32BIT 0x00000000 |
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| 134 | #define SDRAM_CONFIG_REG_NARROW_MODE_16BIT 0x00004000 |
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| 135 | #define SDRAM_CONFIG_REG_CAS_LATENCY 0x00003C00 |
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| 136 | #define SDRAM_CONFIG_REG_CAS_LATENCY_5 0x00000800 |
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| 137 | #define SDRAM_CONFIG_REG_CAS_LATENCY_6 0x00001000 |
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| 138 | #define SDRAM_CONFIG_REG_CAS_LATENCY_7 0x00001800 |
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| 139 | #define SDRAM_CONFIG_REG_CAS_LATENCY_8 0x00002000 |
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| 140 | #define SDRAM_CONFIG_REG_CAS_LATENCY_9 0x00002800 |
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| 141 | #define SDRAM_CONFIG_REG_CAS_LATENCY_10 0x00003000 |
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| 142 | #define SDRAM_CONFIG_REG_CAS_LATENCY_11 0x00003800 |
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| 143 | #define SDRAM_CONFIG_REG_ROWSIZE 0x00000380 |
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| 144 | #define SDRAM_CONFIG_REG_ROWSIZE_9BIT 0x00000000 |
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| 145 | #define SDRAM_CONFIG_REG_ROWSIZE_10BIT 0x00000080 |
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| 146 | #define SDRAM_CONFIG_REG_ROWSIZE_11BIT 0x00000100 |
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| 147 | #define SDRAM_CONFIG_REG_ROWSIZE_12BIT 0x00000180 |
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| 148 | #define SDRAM_CONFIG_REG_ROWSIZE_13BIT 0x00000200 |
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| 149 | #define SDRAM_CONFIG_REG_ROWSIZE_14BIT 0x00000280 |
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| 150 | #define SDRAM_CONFIG_REG_ROWSIZE_15BIT 0x00000300 |
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| 151 | #define SDRAM_CONFIG_REG_ROWSIZE_16BIT 0x00000380 |
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| 152 | #define SDRAM_CONFIG_REG_IBANK 0x00000070 |
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| 153 | #define SDRAM_CONFIG_REG_IBANK_1 0x00000000 |
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| 154 | #define SDRAM_CONFIG_REG_IBANK_2 0x00000010 |
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| 155 | #define SDRAM_CONFIG_REG_IBANK_4 0x00000020 |
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| 156 | #define SDRAM_CONFIG_REG_IBANK_8 0x00000030 |
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| 157 | #define SDRAM_CONFIG_REG_EBANK 0x00000008 |
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| 158 | #define SDRAM_CONFIG_REG_EBANK_1 0x00000000 |
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| 159 | #define SDRAM_CONFIG_REG_PAGESIZE 0x00000007 |
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| 160 | #define SDRAM_CONFIG_REG_PAGESIZE_256_WORD 0x00000000 |
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| 161 | #define SDRAM_CONFIG_REG_PAGESIZE_512_WORD 0x00000001 |
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| 162 | #define SDRAM_CONFIG_REG_PAGESIZE_1024_WORD 0x00000002 |
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| 163 | #define SDRAM_CONFIG_REG_PAGESIZE_2048_WORD 0x00000003 |
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| 164 | #define SDRAM_CONFIG_2_REG_EBANK_POS 0x08000000 |
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| 165 | #define SDRAM_CONFIG_2_REG_EBANK_POS_0 0x00000000 |
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| 166 | #define SDRAM_CONFIG_2_REG_EBANK_POS_1 0x08000000 |
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| 167 | /*===========================================================================*/ |
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| 168 | |
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| 169 | |
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| 170 | /*===========================================================================*/ |
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| 171 | /* McASPx Data Registers */ |
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| 172 | /*===========================================================================*/ |
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| 173 | #define MCASP0_DATA_REGS_BASE 0x46000000 |
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| 174 | #define MCASP1_DATE_REGS_BASE 0x46400000 |
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| 175 | /*===========================================================================*/ |
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| 176 | |
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| 177 | |
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| 178 | /*===========================================================================*/ |
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| 179 | /* L4_WKUP Peripherals */ |
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| 180 | /*===========================================================================*/ |
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| 181 | /* Clock Module Peripheral Registers */ |
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| 182 | #define CM_PER_BASE (L4_WKUP_BASE + 0x00200000) |
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| 183 | #define CM_PER_REG(_x_) *(vulong *)(CM_PER_BASE + _x_) |
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| 184 | /* Clock Module Wakeup Registers */ |
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| 185 | #define CM_WKUP_BASE (L4_WKUP_BASE + 0x00200400) |
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| 186 | #define CM_WKUP_REG(_x_) *(vulong *)(CM_WKUP_BASE + _x_) |
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| 187 | /* Clock Module PLL Registers */ |
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| 188 | #define CM_DPLL_BASE (L4_WKUP_BASE + 0x00200500) |
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| 189 | #define CM_DPLL_REG(_x_) *(vulong *)(CM_DPLL_BASE + _x_) |
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| 190 | /* Clock Module MPU Registers */ |
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| 191 | #define CM_MPU_BASE (L4_WKUP_BASE + 0x00200600) |
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| 192 | #define CM_MPU_REG(_x_) *(vulong *)(CM_MPU_BASE + _x_) |
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| 193 | /* Clock Module Device Registers */ |
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| 194 | #define CM_DEVICE_BASE (L4_WKUP_BASE + 0x00200700) |
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| 195 | #define CM_DEVICE_REG(_x_) *(vulong *)(CM_DEVICE_BASE + _x_) |
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| 196 | /* Clock Module RTC Registers */ |
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| 197 | #define CM_RTC_BASE (L4_WKUP_BASE + 0x00200800) |
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| 198 | #define CM_RTC_REG(_x_) *(vulong *)(CM_RTC_BASE + _x_) |
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| 199 | /* Clock Module Graphics Controller Registers */ |
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| 200 | #define CM_GFX_BASE (L4_WKUP_BASE + 0x00200900) |
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| 201 | #define CM_GFX_REG(_x_) *(vulong *)(CM_GFX_BASE + _x_) |
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| 202 | /* Clock Module Efuse Registers */ |
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| 203 | #define CM_CEFUSE_BASE (L4_WKUP_BASE + 0x00200A00) |
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| 204 | #define CM_CEFUSE_REG(_x_) *(vulong *)(CM_CEFUSE_BASE + _x_) |
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| 205 | /* Power Reset Module Interrupt Registers */ |
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| 206 | #define PRM_IRQ_BASE (L4_WKUP_BASE + 0x00200B00) |
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| 207 | #define PRM_IRQ_REG(_x_) *(vulong *)(PRM_IRQ_BASE + _x_) |
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| 208 | /* Power Reset Module Peripheral Registers */ |
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| 209 | #define PRM_PER_BASE (L4_WKUP_BASE + 0x00200C00) |
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| 210 | #define PRM_PER_REG(_x_) *(vulong *)(PRM_PER_BASE + _x_) |
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| 211 | /* Power Reset Module Wakeup Registers */ |
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| 212 | #define PRM_WKUP_BASE (L4_WKUP_BASE + 0x00200D00) |
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| 213 | #define PRM_WKUP_REG(_x_) *(vulong *)(PRM_WKUP_BASE + _x_) |
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| 214 | /* Power Reset Module MPU Registers */ |
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| 215 | #define PRM_MPU_BASE (L4_WKUP_BASE + 0x00200E00) |
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| 216 | #define PRM_MPU_REG(_x_) *(vulong *)(PRM_MPU_BASE + _x_) |
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| 217 | /* Power Reset Module Device Registers */ |
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| 218 | #define PRM_DEV_BASE (L4_WKUP_BASE + 0x00200F00) |
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| 219 | #define PRM_DEV_REG(_x_) *(vulong *)(PRM_DEV_BASE + _x_) |
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| 220 | /* Power Reset Module RTC Registers */ |
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| 221 | #define PRM_RTC_BASE (L4_WKUP_BASE + 0x00201000) |
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| 222 | #define PRM_RTC_REG(_x_) *(vulong *)(PRM_RTC_BASE + _x_) |
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| 223 | /* Power Reset Module Graphics Controller Registers */ |
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| 224 | #define PRM_GFX_BASE (L4_WKUP_BASE + 0x00201100) |
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| 225 | #define PRM_GFX_REG(_x_) *(vulong *)(PRM_GFX_BASE + _x_) |
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| 226 | /* Power Reset Module Efuse Registers */ |
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| 227 | #define PRM_CEFUSE_BASE (L4_WKUP_BASE + 0x00201200) |
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| 228 | #define PRM_CEFUSE_REG(_x_) *(vulong *)(PRM_CEFUSE_BASE + _x_) |
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| 229 | /* DMTimer0 Registers */ |
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| 230 | #define DMTIMER0_BASE (L4_WKUP_BASE + 0x00205000) |
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| 231 | #define DMTIMER0_REG(_x_) *(vulong *)(DMTIMER0_BASE + _x_) |
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| 232 | /* UART0 Registers */ |
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| 233 | #define UART0_BASE (L4_WKUP_BASE + 0x00209000) |
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| 234 | #define UART0_REG(_x_) *(vulong *)(UART0_BASE + _x_) |
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| 235 | /* I2C0 Registers */ |
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| 236 | #define I2C0_BASE (L4_WKUP_BASE + 0x0020B000) |
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| 237 | #define I2C0_REG(_x_) *(vulong *)(I2C0_BASE + _x_) |
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| 238 | /* ADC_TSC Registers */ |
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| 239 | #define ADC_TSC_BASE (L4_WKUP_BASE + 0x0020D000) |
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| 240 | #define ADC_TSC_REG(_x_) *(vulong *)(ADC_TSC_BASE + _x_) |
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| 241 | /* Control Module */ |
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| 242 | #define CNTL_MODULE_BASE (L4_WKUP_BASE + 0x00210000) |
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| 243 | #define CNTL_MODULE_REG(_x_) *(vulong *)(CNTL_MODULE_BASE + _x_) |
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| 244 | /* DDR2/3/mDDR PHY Registers */ |
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| 245 | #define DDR_PHY_BASE (L4_WKUP_BASE + 0x00212000) |
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| 246 | #define DDR_PHY_REG(_x_) *(vulong *)(DDR_PHY_BASE + _x_) |
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| 247 | /* DMTimer1 1ms Registers */ |
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| 248 | #define DMTIMER1_1MS_BASE (L4_WKUP_BASE + 0x00231000) |
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| 249 | #define DMTIMER1_1MS_REG(_x_) *(vulong *)(DMTIMER1_1MS_BASE + _x_) |
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| 250 | /* L3 Registers */ |
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| 251 | #define SMARTREFLEX0_BASE (L4_WKUP_BASE + 0x00237000) |
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| 252 | #define SMARTREFLEX0_REG(_x_) *(vulong *)(SMARTREFLEX0_BASE + _x_) |
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| 253 | #define SMARTREFLEX1_BASE (L4_WKUP_BASE + 0x00239000) |
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| 254 | #define SMARTREFLEX1_REG(_x_) *(vulong *)(SMARTREFLEX1_BASE + _x_) |
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| 255 | /* RTC Registers */ |
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| 256 | #define RTCSS_BASE (L4_WKUP_BASE + 0x0023E000) |
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| 257 | #define RTCSS_REG(_x_) *(vulong *)(RTCSS_BASE + _x_) |
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| 258 | /* Debug Registers */ |
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| 259 | #define DEBUGSS_HWMSTR1_BASE (L4_WKUP_BASE + 0x00240000) |
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| 260 | #define DEBUGSS_HWMSTR1_REG(_x_) *(vulong *)(DEBUGSS_HWMSTR1_BASE + _x_) |
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| 261 | /*===========================================================================*/ |
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| 262 | |
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| 263 | |
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| 264 | /*===========================================================================*/ |
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| 265 | /* CM_PER Registers */ |
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| 266 | /*===========================================================================*/ |
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| 267 | #define CM_PER_L3_CLKSTCTRL 0x0C |
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| 268 | #define CM_PER_EMIF_CLKCTRL 0x28 |
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| 269 | #define CM_PER_MMC0_CLKCTRL 0x3C |
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| 270 | #define CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE 0x02 |
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| 271 | #define CM_PER_MMC0_CLKCTRL_IDLEST 0x00030000 |
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| 272 | #define CM_PER_GPIO1_CLKCTRL 0xAC |
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| 273 | #define CM_PER_MMC1_CLKCTRL 0xF4 |
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| 274 | #define CM_PER_MMC1_CLKCTRL_MODULEMODE_ENABLE 0x02 |
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| 275 | #define CM_PER_MMC1_CLKCTRL_IDLEST 0x00030000 |
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| 276 | /*===========================================================================*/ |
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| 277 | |
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| 278 | |
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| 279 | /*===========================================================================*/ |
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| 280 | /* CM_WKUP Registers */ |
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| 281 | /*===========================================================================*/ |
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| 282 | #define CM_WKUP_CLKSTCTRL 0x00 |
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| 283 | #define CM_WKUP_CONTROL_CLKCTRL 0x04 |
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| 284 | #define CM_WKUP_GPIO0_CLKCTRL 0x08 |
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| 285 | #define CM_WKUP_L4WKUP_CLKCTRL 0x0C |
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| 286 | #define CM_WKUP_TIMER0_CLKCTRL 0x10 |
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| 287 | #define CM_WKUP_DEBUGSS_CLKCTRL 0x14 |
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| 288 | #define CM_L3_AON_CLKSTCTRL 0x18 |
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| 289 | #define CM_AUTOIDLE_DPLL_MPU 0x1C |
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| 290 | #define CM_IDLEST_DPLL_MPU 0x20 |
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| 291 | #define CM_SSC_DELTAMSTEP_DPLL_MPU 0x24 |
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| 292 | #define CM_SSC_MODFREQDIV_DPLL_MPU 0x28 |
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| 293 | #define CM_CLKSEL_DPLL_MPU 0x2C |
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| 294 | #define CM_AUTOIDLE_DPLL_DDR 0x30 |
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| 295 | #define CM_IDLEST_DPLL_DDR 0x34 |
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| 296 | #define CM_SSC_DELTAMSTEP_DPLL_DDR 0x38 |
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| 297 | #define CM_SSC_MODFREQDIV_DPLL_DDR 0x3C |
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| 298 | #define CM_CLKSEL_DPLL_DDR 0x40 |
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| 299 | #define CM_AUTOIDLE_DPLL_DISP 0x44 |
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| 300 | #define CM_IDLEST_DPLL_DISP 0x48 |
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| 301 | #define CM_SSC_DELTAMSTEP_DPLL_DISP 0x4C |
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| 302 | #define CM_SSC_MODFREQDIV_DPLL_DISP 0x50 |
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| 303 | #define CM_CLKSEL_DPLL_DISP 0x54 |
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| 304 | #define CM_AUTOIDLE_DPLL_CORE 0x58 |
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| 305 | #define CM_IDLEST_DPLL_CORE 0x5C |
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| 306 | #define CM_SSC_DELTAMSTEP_DPLL_CORE 0x60 |
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| 307 | #define CM_SSC_MODFREQDIV_DPLL_CORE 0x64 |
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| 308 | #define CM_CLKSEL_DPLL_CORE 0x68 |
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| 309 | #define CM_AUTOIDLE_DPLL_PER 0x6C |
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| 310 | #define CM_IDLEST_DPLL_PER 0x70 |
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| 311 | #define CM_SSC_DELTAMSTEP_DPLL_PER 0x74 |
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| 312 | #define CM_SSC_MODFREQDIV_DPLL_PER 0x78 |
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| 313 | #define CM_CLKDCOLDO_DPLL_PER 0x7C |
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| 314 | #define CM_DIV_M4_DPLL_CORE 0x80 |
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| 315 | #define CM_DIV_M5_DPLL_CORE 0x84 |
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| 316 | #define CM_CLKMODE_DPLL_MPU 0x88 |
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| 317 | #define CM_CLKMODE_DPLL_PER 0x8C |
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| 318 | #define CM_CLKMODE_DPLL_CORE 0x90 |
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| 319 | #define CM_CLKMODE_DPLL_DDR 0x94 |
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| 320 | #define CM_CLKMODE_DPLL_DISP 0x98 |
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| 321 | #define CM_CLKSEL_DPLL_PER 0x9C |
|---|
| 322 | #define CM_DIV_M2_DPLL_DDR 0xA0 |
|---|
| 323 | #define CM_DIV_M2_DPLL_DISP 0xA4 |
|---|
| 324 | #define CM_DIV_M2_DPLL_MPU 0xA8 |
|---|
| 325 | #define CM_DIV_M2_DPLL_PER 0xAC |
|---|
| 326 | #define CM_WKUP_WKUP_M3_CLKCTRL 0xB0 |
|---|
| 327 | #define CM_WKUP_UART0_CLKCTRL 0xB4 |
|---|
| 328 | #define CM_WKUP_I2C0_CLKCTRL 0xB8 |
|---|
| 329 | #define CM_WKUP_ADC_TSC_CLKCTRL 0xBC |
|---|
| 330 | #define CM_WKUP_SMARTREFLEX0_CLKCT 0xC0 |
|---|
| 331 | #define CM_WKUP_TIMER1_CLKCTRL 0xC4 |
|---|
| 332 | #define CM_WKUP_SMARTREFLEX1_CLKCT 0xC8 |
|---|
| 333 | #define CM_L4_WKUP_AON_CLKSTCTRL 0xCC |
|---|
| 334 | #define CM_WKUP_WDT1_CLKCTRL 0xD4 |
|---|
| 335 | #define CM_DIV_M6_DPLL_CORE 0xD8 |
|---|
| 336 | /*===========================================================================*/ |
|---|
| 337 | |
|---|
| 338 | |
|---|
| 339 | #define CM_CLKSEL_DPLL_PER_DPLL_MULT (960 << 8) |
|---|
| 340 | #define CM_CLKSEL_DPLL_PER_DPLL_DIV (23) |
|---|
| 341 | #define CM_CLKSEL_DPLL_PER_DPLL_SD_DIV (4 << 24) |
|---|
| 342 | |
|---|
| 343 | |
|---|
| 344 | /*===========================================================================*/ |
|---|
| 345 | /* Control Module Registers */ |
|---|
| 346 | /*===========================================================================*/ |
|---|
| 347 | #define CONTROL_STATUS 0x0040 |
|---|
| 348 | #define CONTROL_EMIF_SDRAM_CONFIG 0x0110 |
|---|
| 349 | #define CONF_GPMC_AD0 0x0800 |
|---|
| 350 | #define CONF_GPMC_AD1 0x0804 |
|---|
| 351 | #define CONF_GPMC_AD2 0x0808 |
|---|
| 352 | #define CONF_GPMC_AD3 0x080C |
|---|
| 353 | #define CONF_GPMC_AD4 0x0810 |
|---|
| 354 | #define CONF_GPMC_AD5 0x0814 |
|---|
| 355 | #define CONF_GPMC_AD6 0x0818 |
|---|
| 356 | #define CONF_GPMC_AD7 0x081C |
|---|
| 357 | #define CONF_GPMC_A5 0x0854 |
|---|
| 358 | #define CONF_GPMC_A6 0x0858 |
|---|
| 359 | #define CONF_GPMC_A7 0x085c |
|---|
| 360 | #define CONF_GPMC_A8 0x0860 |
|---|
| 361 | #define CONF_GPMC_CSN1 0x0880 |
|---|
| 362 | #define CONF_GPMC_CSN2 0x0884 |
|---|
| 363 | #define CONF_MMC0_DAT3 0x08F0 |
|---|
| 364 | #define CONF_MMC0_DAT2 0x08F4 |
|---|
| 365 | #define CONF_MMC0_DAT1 0x08F8 |
|---|
| 366 | #define CONF_MMC0_DAT0 0x08FC |
|---|
| 367 | #define CONF_MMC0_CLK 0x0900 |
|---|
| 368 | #define CONF_MMC0_CMD 0x0904 |
|---|
| 369 | #define CONF_SPI0_CS1 0x0960 |
|---|
| 370 | #define CONF_UART0_RXD 0x0970 |
|---|
| 371 | #define CONF_UART0_TXD 0x0974 |
|---|
| 372 | #define DDR_IO_CTRL 0x0E04 |
|---|
| 373 | #define VTP_CTRL 0x0E0C |
|---|
| 374 | #define VREF_CTRL 0x0E14 |
|---|
| 375 | #define DDR_CKE_CTRL 0x131C |
|---|
| 376 | #define DDR_CMD0_IOCTRL 0x1404 |
|---|
| 377 | #define DDR_CMD1_IOCTRL 0x1408 |
|---|
| 378 | #define DDR_CMD2_IOCTRL 0x140C |
|---|
| 379 | #define DDR_DATA0_IOCTRL 0x1440 |
|---|
| 380 | #define DDR_DATA1_IOCTRL 0x1444 |
|---|
| 381 | /*===========================================================================*/ |
|---|
| 382 | |
|---|
| 383 | |
|---|
| 384 | /*===========================================================================*/ |
|---|
| 385 | /* DDR2/3/mDDR PHY Registers */ |
|---|
| 386 | /*===========================================================================*/ |
|---|
| 387 | #define CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 0x001C |
|---|
| 388 | #define CMD0_REG_PHY_DLL_LOCK_DIFF_0 0x0028 |
|---|
| 389 | #define CMD0_REG_PHY_INVERT_CLKOUT_0 0x002C |
|---|
| 390 | #define CMD1_REG_PHY_CTRL_SLAVE_RATIO_0 0x0050 |
|---|
| 391 | #define CMD1_REG_PHY_DLL_LOCK_DIFF_0 0x005C |
|---|
| 392 | #define CMD1_REG_PHY_INVERT_CLKOUT_0 0x0060 |
|---|
| 393 | #define CMD2_REG_PHY_CTRL_SLAVE_RATIO_0 0x0084 |
|---|
| 394 | #define CMD2_REG_PHY_DLL_LOCK_DIFF_0 0x0090 |
|---|
| 395 | #define CMD2_REG_PHY_INVERT_CLKOUT_0 0x0094 |
|---|
| 396 | #define DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0 0x00C8 |
|---|
| 397 | #define DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0 0x00DC |
|---|
| 398 | #define DATA0_REG_PHY_WRLVL_INIT_RATIO_0 0x00F0 |
|---|
| 399 | #define DATA0_REG_PHY_WRLVL_INIT_MODE_0 0x00F8 |
|---|
| 400 | #define DATA0_REG_PHY_GATELVL_INIT_RATIO_0 0x00FC |
|---|
| 401 | #define DATA0_REG_PHY_GATELVL_INIT_MODE_0 0x0104 |
|---|
| 402 | #define DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0 0x0108 |
|---|
| 403 | #define DATA0_REG_PHY_DQ_OFFSET_0 0x011C |
|---|
| 404 | #define DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0 0x0120 |
|---|
| 405 | #define DATA0_REG_PHY_USE_RANK0_DELAYS 0x0134 |
|---|
| 406 | #define DATA0_REG_PHY_LOCK_DIFF_0 0x0138 |
|---|
| 407 | #define DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0 0x016C |
|---|
| 408 | #define DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0 0x0180 |
|---|
| 409 | #define DATA1_REG_PHY_WRLVL_INIT_RATIO_0 0x0194 |
|---|
| 410 | #define DATA1_REG_PHY_WRLVL_INIT_MODE_0 0x019C |
|---|
| 411 | #define DATA1_REG_PHY_GATELVL_INIT_RATIO_0 0x01A0 |
|---|
| 412 | #define DATA1_REG_PHY_GATELVL_INIT_MODE_0 0x01A8 |
|---|
| 413 | #define DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0 0x01AC |
|---|
| 414 | #define DATA1_REG_PHY_DQ_OFFSET_0 0x01C0 |
|---|
| 415 | #define DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0 0x01C4 |
|---|
| 416 | #define DATA1_REG_PHY_USE_RANK0_DELAYS 0x01D8 |
|---|
| 417 | #define DATA1_REG_PHY_LOCK_DIFF_0 0x01DC |
|---|
| 418 | /*===========================================================================*/ |
|---|
| 419 | |
|---|
| 420 | |
|---|
| 421 | /*===========================================================================*/ |
|---|
| 422 | /* Pad control bits: */ |
|---|
| 423 | /*===========================================================================*/ |
|---|
| 424 | #define SLEWSLOW (1 << 6) |
|---|
| 425 | #define SLEWFAST 0 |
|---|
| 426 | #define RX_ON (1 << 5) |
|---|
| 427 | #define RX_OFF 0 |
|---|
| 428 | #define PULLUP (1 << 4) |
|---|
| 429 | #define PULLDOWN 0 |
|---|
| 430 | #define PULL_OFF (1 << 3) |
|---|
| 431 | #define PULL_ON 0 |
|---|
| 432 | #define MUXMODE_0 (0 & 7) |
|---|
| 433 | #define MUXMODE_1 (1 & 7) |
|---|
| 434 | #define MUXMODE_2 (2 & 7) |
|---|
| 435 | #define MUXMODE_3 (3 & 7) |
|---|
| 436 | #define MUXMODE_4 (4 & 7) |
|---|
| 437 | #define MUXMODE_5 (5 & 7) |
|---|
| 438 | #define MUXMODE_6 (6 & 7) |
|---|
| 439 | #define MUXMODE_7 (7 & 7) |
|---|
| 440 | /*===========================================================================*/ |
|---|
| 441 | |
|---|
| 442 | |
|---|
| 443 | /*===========================================================================*/ |
|---|
| 444 | /* L4_PER Peripherals */ |
|---|
| 445 | /*===========================================================================*/ |
|---|
| 446 | /* UART1 Registers */ |
|---|
| 447 | #define UART1_BASE (L4_PER_BASE + 0x00022000) |
|---|
| 448 | #define UART1_REG(_x_) *(vulong *)(UART1_BASE + _x_) |
|---|
| 449 | /* UART2 Registers */ |
|---|
| 450 | #define UART2_BASE (L4_PER_BASE + 0x00024000) |
|---|
| 451 | #define UART2_REG(_x_) *(vulong *)(UART2_BASE + _x_) |
|---|
| 452 | /* I2C1 Registers */ |
|---|
| 453 | #define I2C1_BASE (L4_PER_BASE + 0x0002A000) |
|---|
| 454 | #define I2C1_REG(_x_) *(vulong *)(I2C1_BASE + _x_) |
|---|
| 455 | /* McSPI0 Registers */ |
|---|
| 456 | #define MCSPI0_BASE (L4_PER_BASE + 0x00030000) |
|---|
| 457 | #define MCSPI0_REG(_x_) *(vulong *)(MCSPI0_BASE + _x_) |
|---|
| 458 | /* McASP0 CFG Registers */ |
|---|
| 459 | #define MCASP0_CFG_BASE (L4_PER_BASE + 0x00038000) |
|---|
| 460 | #define MCASP0_CFG_REG(_x_) *(vulong *)(MCASP0_CFG_BASE + _x_) |
|---|
| 461 | /* McASP1 CFG Registers */ |
|---|
| 462 | #define MCASP1_CFG_BASE (L4_PER_BASE + 0x0003C000) |
|---|
| 463 | #define MCASP1_CFG_REG(_x_) *(vulong *)(MCASP1_CFG_BASE + _x_) |
|---|
| 464 | /* DMTimer2 Registers */ |
|---|
| 465 | #define DMTIMER2_BASE (L4_PER_BASE + 0x00040000) |
|---|
| 466 | #define DMTIMER2_REG(_x_) *(vulong *)(DMTIMER2_BASE + _x_) |
|---|
| 467 | /* DMTimer3 Registers */ |
|---|
| 468 | #define DMTIMER3_BASE (L4_PER_BASE + 0x00042000) |
|---|
| 469 | #define DMTIMER3_REG(_x_) *(vulong *)(DMTIMER3_BASE + _x_) |
|---|
| 470 | /* DMTimer4 Registers */ |
|---|
| 471 | #define DMTIMER4_BASE (L4_PER_BASE + 0x00044000) |
|---|
| 472 | #define DMTIMER4_REG(_x_) *(vulong *)(DMTIMER4_BASE + _x_) |
|---|
| 473 | /* DMTimer5 Registers */ |
|---|
| 474 | #define DMTIMER5_BASE (L4_PER_BASE + 0x00046000) |
|---|
| 475 | #define DMTIMER5_REG(_x_) *(vulong *)(DMTIMER5_BASE + _x_) |
|---|
| 476 | /* DMTimer6 Registers */ |
|---|
| 477 | #define DMTIMER6_BASE (L4_PER_BASE + 0x00048000) |
|---|
| 478 | #define DMTIMER6_REG(_x_) *(vulong *)(DMTIMER6_BASE + _x_) |
|---|
| 479 | /* DMTimer7 Registers */ |
|---|
| 480 | #define DMTIMER7_BASE (L4_PER_BASE + 0x0004A000) |
|---|
| 481 | #define DMTIMER7_REG(_x_) *(vulong *)(DMTIMER7_BASE + _x_) |
|---|
| 482 | /* ELM Registers */ |
|---|
| 483 | #define ELM_BASE (L4_PER_BASE + 0x00080000) |
|---|
| 484 | #define ELM_REG(_x_) *(vulong *)(ELM_BASE + _x_) |
|---|
| 485 | /* Mailbox 0 Registers */ |
|---|
| 486 | #define MAILBOX0_BASE (L4_PER_BASE + 0x000C8000) |
|---|
| 487 | #define MAILBOX0_REG(_x_) *(vulong *)(MAILBOX0_BASE + _x_) |
|---|
| 488 | /* Spinlock Registers */ |
|---|
| 489 | #define SPINLOCK_BASE (L4_PER_BASE + 0x000CA000) |
|---|
| 490 | #define SPINLOCK_REG(_x_) *(vulong *)(SPINLOCK_BASE + _x_) |
|---|
| 491 | /* OCP Watchpoint Registers */ |
|---|
| 492 | #define OCP_WATCHPOINT_BASE (L4_PER_BASE + 0x0018C000) |
|---|
| 493 | #define OCP_WATCHPOINT_REG(_x_) *(vulong *)(OCP_WATCHPOINT_BASE + _x_) |
|---|
| 494 | /* I2C2 Registers */ |
|---|
| 495 | #define I2C2_BASE (L4_PER_BASE + 0x0019C000) |
|---|
| 496 | #define I2C2_REG(_x_) *(vulong *)(I2C2_BASE + _x_) |
|---|
| 497 | /* McSPI1 Registers */ |
|---|
| 498 | #define MCSPI1_BASE (L4_PER_BASE + 0x001A0000) |
|---|
| 499 | #define MCSPI1_REG(_x_) *(vulong *)(MSCPI1_BASE + _x_) |
|---|
| 500 | /* UART3 Registers */ |
|---|
| 501 | #define UART3_BASE (L4_PER_BASE + 0x001A6000) |
|---|
| 502 | #define UART3_REG(_x_) *(vulong *)(UART3_BASE + _x_) |
|---|
| 503 | /* UART4 Registers */ |
|---|
| 504 | #define UART4_BASE (L4_PER_BASE + 0x001A8000) |
|---|
| 505 | #define UART4_REG(_x_) *(vulong *)(UART4_BASE + _x_) |
|---|
| 506 | /* UART5 Registers */ |
|---|
| 507 | #define UART5_BASE (L4_PER_BASE + 0x001AA000) |
|---|
| 508 | #define UART5_REG(_x_) *(vulong *)(UART5_BASE + _x_) |
|---|
| 509 | /* DCAN0 Registers */ |
|---|
| 510 | #define DCAN0_BASE (L4_PER_BASE + 0x001CC000) |
|---|
| 511 | #define DCAN0_REG(_x_) *(vulong *)(DCAN0_BASE + _x_) |
|---|
| 512 | /* DCAN1 Registers */ |
|---|
| 513 | #define DCAN1_BASE (L4_PER_BASE + 0x001D0000) |
|---|
| 514 | #define DCAN1_REG(_x_) *(vulong *)(DCAN1_BASE + _x_) |
|---|
| 515 | /* Interrupt Controller Registers */ |
|---|
| 516 | #define INTCPS_BASE (L4_PER_BASE + 0x00200000) |
|---|
| 517 | #define INTCPS_REG(_x_) *(vulong *)(INTCPS_BASE + _x_) |
|---|
| 518 | /* MPUSS Config Register */ |
|---|
| 519 | #define MPUSS_BASE (L4_PER_BASE + 0x00240000) |
|---|
| 520 | #define MPUSS_REG(_x_) *(vulong *)(MPUSS_BASE + _x_) |
|---|
| 521 | /* PWMSS0 Configuration Registers */ |
|---|
| 522 | #define PWMSS0_BASE (L4_PER_BASE + 0x00300000) |
|---|
| 523 | #define PWMSS0_REG(_x_) *(vulong *)(PWMSS0_BASE + _x_) |
|---|
| 524 | /* PWMSS eCAP0 Registers */ |
|---|
| 525 | #define ECAP0_BASE (L4_PER_BASE + 0x00300100) |
|---|
| 526 | #define ECAP0_REG(_x_) *(vulong *)(ECAP0_BASE + _x_) |
|---|
| 527 | /* PWMSS eQEP0 Registers */ |
|---|
| 528 | #define EQEP0_BASE (L4_PER_BASE + 0x00300180) |
|---|
| 529 | #define EQEP0_REG(_x_) *(vulong *)(EQEP0_BASE + _x_) |
|---|
| 530 | /* PWMSS ePWM0 Registers */ |
|---|
| 531 | #define EPWM0_BASE (L4_PER_BASE + 0x00300200) |
|---|
| 532 | #define EPWM0_REG(_x_) *(vulong *)(EPWM0_BASE + _x_) |
|---|
| 533 | /* PWMSS1 Configuration Registers */ |
|---|
| 534 | #define PWMSS1_BASE (L4_PER_BASE + 0x00302000) |
|---|
| 535 | #define PWMSS1_REG(_x_) *(vulong *)(PWMSS1_BASE + _x_) |
|---|
| 536 | /* PWMSS eCAP1 Registers */ |
|---|
| 537 | #define ECAP1_BASE (L4_PER_BASE + 0x00302100) |
|---|
| 538 | #define ECAP1_REG(_x_) *(vulong *)(ECAP1_BASE + _x_) |
|---|
| 539 | /* PWMSS eQEP1 Registers */ |
|---|
| 540 | #define EQEP1_BASE (L4_PER_BASE + 0x00302180) |
|---|
| 541 | #define EQEP1_REG(_x_) *(vulong *)(EQEP1_BASE + _x_) |
|---|
| 542 | /* PWMSS ePWM1 Registers */ |
|---|
| 543 | #define EPWM1_BASE (L4_PER_BASE + 0x00302200) |
|---|
| 544 | #define EPWM1_REG(_x_) *(vulong *)(EPwM_BASE + _x_) |
|---|
| 545 | /* PWMSS2 Configuration Registers */ |
|---|
| 546 | #define PWMSS2_BASE (L4_PER_BASE + 0x00304000) |
|---|
| 547 | #define PWMSS2_REG(_x_) *(vulong *)(PWMSS2_BASE + _x_) |
|---|
| 548 | /* PWMSS eCAP2 Registers */ |
|---|
| 549 | #define ECAP2_BASE (L4_PER_BASE + 0x00304100) |
|---|
| 550 | #define ECAP2_REG(_x_) *(vulong *)(ECAP2_BASE + _x_) |
|---|
| 551 | /* PWMSS eQEP2 Registers */ |
|---|
| 552 | #define EQEP2_BASE (L4_PER_BASE + 0x00304180) |
|---|
| 553 | #define EQEP2_REG(_x_) *(vulong *)(EQEP2_BASE + _x_) |
|---|
| 554 | /* PWMSS ePWM2 Registers */ |
|---|
| 555 | #define EPWM2_BASE (L4_PER_BASE + 0x00304200) |
|---|
| 556 | #define EPWM2_REG(_x_) *(vulong *)(EPWM2_BASE + _x_) |
|---|
| 557 | /* LCD Contoller Registers */ |
|---|
| 558 | #define LCD_CNTLR_BASE (L4_PER_BASE + 0x0030E000) |
|---|
| 559 | #define LCD_CNTLR_REG(_x_) *(vulong *)(LCD_CNTLR_BASE + _x_) |
|---|
| 560 | /*===========================================================================*/ |
|---|
| 561 | |
|---|
| 562 | |
|---|
| 563 | /*===========================================================================*/ |
|---|
| 564 | /* L4_FAST Peripherals */ |
|---|
| 565 | /*===========================================================================*/ |
|---|
| 566 | #define L4_FAST_BASE 0x4A000000 |
|---|
| 567 | /* Ethernet Switch Subsystem Registers */ |
|---|
| 568 | #define CPSW_SS_BASE (LF_FAST_BASE + 0x00100000) |
|---|
| 569 | #define CPSW_SS_REG(_x_) *(vulong *)(CPSW_SS_BASE + _x_) |
|---|
| 570 | /* Ethernet Switch Port Control Registers */ |
|---|
| 571 | #define CPSW_PORT_BASE (LF_FAST_BASE + 0x00100100) |
|---|
| 572 | #define CPSW_PORT_REG(_x_) *(vulong *)(CPSW_PORT_BASE + _x_) |
|---|
| 573 | /* CPPI DMA Controller Module Registers */ |
|---|
| 574 | #define CPSW_CPDMA_BASE (LF_FAST_BASE + 0x00100800) |
|---|
| 575 | #define CPSW_CPDMA_REG(_x_) *(vulong *)(CPSW_CPDMA_BASE + _x_) |
|---|
| 576 | /* Ethernet Statistics Registers */ |
|---|
| 577 | #define CPSW_STATS_BASE (LF_FAST_BASE + 0x00100900) |
|---|
| 578 | #define CPSW_STATS_REG(_x_) *(vulong *)(CPSW_STATS_BASE + _x_) |
|---|
| 579 | /* CPPI DMA State RAM Registers */ |
|---|
| 580 | #define CPSW_STATERAM_BASE (LF_FAST_BASE + 0x00100A00) |
|---|
| 581 | #define CPSW_STATERAM_REG(_x_) *(vulong *)(CPSW_STATERAM_BASE + _x_) |
|---|
| 582 | /* Ethenet Time Sync Module Registers */ |
|---|
| 583 | #define CPSW_CPTS_BASE (LF_FAST_BASE + 0x00100C00) |
|---|
| 584 | #define CPSW_CPTS_REG(_x_) *(vulong *)(CPSW_CPTS_BASE + _x_) |
|---|
| 585 | /* Ethernet Address Lookup Engine Registers */ |
|---|
| 586 | #define CPSW_ALE_BASE (LF_FAST_BASE + 0x00100D00) |
|---|
| 587 | #define CPSW_ALE_REG(_x_) *(vulong *)(CPSW_ALE_BASE + _x_) |
|---|
| 588 | /* Ethernet Silver for Port 1 Registers */ |
|---|
| 589 | #define CPSW_SL1_BASE (LF_FAST_BASE + 0x00100D80) |
|---|
| 590 | #define CPSW_SL1_REG(_x_) *(vulong *)(CPSW_SL1_BASE + _x_) |
|---|
| 591 | /* Ethernet Silver for Port 2 Registers */ |
|---|
| 592 | #define CPSW_SL2_BASE (LF_FAST_BASE + 0x00100DC0) |
|---|
| 593 | #define CPSW_SL2_REG(_x_) *(vulong *)(CPSW_SL2_BASE + _x_) |
|---|
| 594 | /* Ethernet MDIO Controller Registers */ |
|---|
| 595 | #define MDIO_BASE (LF_FAST_BASE + 0x00101000) |
|---|
| 596 | #define MDIO_REG(_x_) *(vulong *)(MDIO_BASE + _x_) |
|---|
| 597 | /* Ethernet Subsystem Wrapper for RMII/RGMII Registers */ |
|---|
| 598 | #define CPSW_WR_BASE (LF_FAST_BASE + 0x00101200) |
|---|
| 599 | #define CPSW_WR_REG(_x_) *(vulong *)(CPSW_WR_BASE + _x_) |
|---|
| 600 | /*===========================================================================*/ |
|---|
| 601 | |
|---|
| 602 | |
|---|
| 603 | /*===========================================================================*/ |
|---|
| 604 | /* UART Register offsets */ |
|---|
| 605 | /*===========================================================================*/ |
|---|
| 606 | /* Transmit Holding Register (write only) */ |
|---|
| 607 | #define UART_THR 0x00 |
|---|
| 608 | /* Receive Holding Register (read only) */ |
|---|
| 609 | #define UART_RHR 0x00 |
|---|
| 610 | /* Baud divisor lower byte (read/write) */ |
|---|
| 611 | #define UART_DLL 0x00 |
|---|
| 612 | /* Interrupt Enable Register (read/write) */ |
|---|
| 613 | #define UART_IER 0x04 |
|---|
| 614 | /* Baud divisor higher byte (read/write) */ |
|---|
| 615 | #define UART_DLH 0x04 |
|---|
| 616 | /* Enhanced Feature Register */ |
|---|
| 617 | #define UART_EFR 0x08 |
|---|
| 618 | /* Interrupt Identification Register (read only) */ |
|---|
| 619 | #define UART_IIR 0x08 |
|---|
| 620 | /* FIFO Control Register (write only) */ |
|---|
| 621 | #define UART_FCR 0x08 |
|---|
| 622 | /* Line Control Register (read/write) */ |
|---|
| 623 | #define UART_LCR 0x0C |
|---|
| 624 | /* Modem Control Register (read/write) */ |
|---|
| 625 | #define UART_MCR 0x10 |
|---|
| 626 | /* XON1/ADDR1 Register */ |
|---|
| 627 | #define UART_XON1_ADDR1 0x10 |
|---|
| 628 | /* XON2/ADDR2 Register */ |
|---|
| 629 | #define UART_XON2_ADDR2 0x14 |
|---|
| 630 | /* Line Status Register (read only) */ |
|---|
| 631 | #define UART_LSR 0x14 |
|---|
| 632 | /* Transmission Control Register */ |
|---|
| 633 | #define UART_TCR 0x18 |
|---|
| 634 | /* Modem Status Register (read only) */ |
|---|
| 635 | #define UART_MSR 0x18 |
|---|
| 636 | /* XOFF1 Register */ |
|---|
| 637 | #define UART_XOFF1 0x18 |
|---|
| 638 | /* Scratch Pad Register (read/write) */ |
|---|
| 639 | #define UART_SPR 0x1C |
|---|
| 640 | /* Trigger Level Register */ |
|---|
| 641 | #define UART_TLR 0x1C |
|---|
| 642 | /* XOFF2 Register */ |
|---|
| 643 | #define UART_XOFF2 0x1C |
|---|
| 644 | /* Mode Definition Register 1 */ |
|---|
| 645 | #define UART_MDR1 0x20 |
|---|
| 646 | /* Mode Definition Register 2 */ |
|---|
| 647 | #define UART_MDR2 0x24 |
|---|
| 648 | /* Transmit Frame Length Register Low (IrDA modes only) */ |
|---|
| 649 | #define UART_TXFLL 0x28 |
|---|
| 650 | /* Status FIFO Line Status Register (IrDA modes only) */ |
|---|
| 651 | #define UART_SFLSR 0x28 |
|---|
| 652 | /* Resume Register (IR-IrDA and IR-CIR modes only) */ |
|---|
| 653 | #define UART_RESUME 0x2C |
|---|
| 654 | /* Transmit Frame Length Register High (IrDA modes only) */ |
|---|
| 655 | #define UART_TXFLH 0x2C |
|---|
| 656 | /* Receive Frame Length Register Low (IrDA modes only) */ |
|---|
| 657 | #define UART_RXFLL 0x30 |
|---|
| 658 | /* Status FIFO Register Low (IrDA modes only) */ |
|---|
| 659 | #define UART_SFREGL 0x30 |
|---|
| 660 | /* Status FIFO Register High (IrDA modes only) */ |
|---|
| 661 | #define UART_SFREGH 0x34 |
|---|
| 662 | /* Receive Frame Length Register High (IrDA modes only) */ |
|---|
| 663 | #define UART_RXFLH 0x34 |
|---|
| 664 | /* BOF Control Register (IrDA modes only_ */ |
|---|
| 665 | #define UART_BLR 0x38 |
|---|
| 666 | /* UART Autobauding Status Register (UART autobauding |
|---|
| 667 | mode only */ |
|---|
| 668 | #define UART_UASR 0x38 |
|---|
| 669 | /* Auxiliary Control Register (IrDA-CIR modes only) */ |
|---|
| 670 | #define UART_ACREG 0x3C |
|---|
| 671 | /* Supplementary Control Register */ |
|---|
| 672 | #define UART_SCR 0x40 |
|---|
| 673 | /* Supplementary Status Register */ |
|---|
| 674 | #define UART_SSR 0x44 |
|---|
| 675 | /* BOF Length Register (IR-IrDA and IR-CIR modes only) */ |
|---|
| 676 | #define UART_EBLR 0x48 |
|---|
| 677 | /* Module Version Register */ |
|---|
| 678 | #define UART_MVR 0x50 |
|---|
| 679 | /* System Configuration Register */ |
|---|
| 680 | #define UART_SYSC 0x54 |
|---|
| 681 | /* System Status Register */ |
|---|
| 682 | #define UART_SYSS 0x58 |
|---|
| 683 | /* Wake-up Enable Register */ |
|---|
| 684 | #define UART_WER 0x5C |
|---|
| 685 | /* Carrier Frequency Prescalar Register */ |
|---|
| 686 | #define UART_CFPS 0x60 |
|---|
| 687 | /* Received FIFO Level Register */ |
|---|
| 688 | #define UART_RXFIFO_LVL 0x64 |
|---|
| 689 | /* Transmit FIFO Level Register */ |
|---|
| 690 | #define UART_TXFIFO_LVL 0x68 |
|---|
| 691 | /* IER2 Register */ |
|---|
| 692 | #define UART_IER2 0x6C |
|---|
| 693 | /* ISR2 Register */ |
|---|
| 694 | #define UART_ISR2 0x70 |
|---|
| 695 | /* FREQ_SEL Register */ |
|---|
| 696 | #define UART_FREQ_SEL 0x74 |
|---|
| 697 | /* Mode Definition Register 3 */ |
|---|
| 698 | #define UART_MDR3 0x80 |
|---|
| 699 | /* TX DMA Threshold Register */ |
|---|
| 700 | #define UART_TX_DMA_THRESHOLD 0x84 |
|---|
| 701 | /*===========================================================================*/ |
|---|
| 702 | |
|---|
| 703 | |
|---|
| 704 | /*===========================================================================*/ |
|---|
| 705 | /* USB */ |
|---|
| 706 | /*===========================================================================*/ |
|---|
| 707 | #define USB_SUBSYS_BASE_ADDR 0x47400000 |
|---|
| 708 | /*---------------------------------------------------------------------------*/ |
|---|
| 709 | /* USB Subsystem Registers offset */ |
|---|
| 710 | #define USBSS_BASE_REG_OFFSET 0x0000 |
|---|
| 711 | #define USBSS_REVREG 0x0000 |
|---|
| 712 | #define USBSS_SYSCONFIG 0x0010 |
|---|
| 713 | #define USBSS_IRQSTATRAW 0x0024 |
|---|
| 714 | #define USBSS_IRQSTAT 0x0028 |
|---|
| 715 | #define USBSS_IRQENABLER 0x002C |
|---|
| 716 | #define USBSS_IRQCLEARR 0x0030 |
|---|
| 717 | #define USBSS_IRQDMATHOLDTX00 0x0100 |
|---|
| 718 | #define USBSS_IRQDMATHOLDTX01 0x0104 |
|---|
| 719 | #define USBSS_IRQDMATHOLDTX02 0x0108 |
|---|
| 720 | #define USBSS_IRQDMATHOLDTX03 0x010C |
|---|
| 721 | #define USBSS_IRQDMATHOLDRX00 0x0110 |
|---|
| 722 | #define USBSS_IRQDMATHOLDRX01 0x0114 |
|---|
| 723 | #define USBSS_IRQDMATHOLDRX02 0x0118 |
|---|
| 724 | #define USBSS_IRQDMATHOLDRX03 0x011C |
|---|
| 725 | #define USBSS_IRQDMATHOLDTX10 0x0120 |
|---|
| 726 | #define USBSS_IRQDMATHOLDTX11 0x0124 |
|---|
| 727 | #define USBSS_IRQDMATHOLDTX12 0x0128 |
|---|
| 728 | #define USBSS_IRQDMATHOLDTX13 0x012C |
|---|
| 729 | #define USBSS_IRQDMATHOLDRX10 0x0130 |
|---|
| 730 | #define USBSS_IRQDMATHOLDRX11 0x0134 |
|---|
| 731 | #define USBSS_IRQDMATHOLDRX12 0x0138 |
|---|
| 732 | #define USBSS_IRQDMATHOLDRX13 0x013C |
|---|
| 733 | #define USBSS_IRQDMAENABLE0 0x0140 |
|---|
| 734 | #define USBSS_IRQDMAENABLE1 0x0144 |
|---|
| 735 | #define USBSS_IRQFRAMETHOLDTX00 0x0200 |
|---|
| 736 | #define USBSS_IRQFRAMETHOLDTX01 0x0204 |
|---|
| 737 | #define USBSS_IRQFRAMETHOLDTX02 0x0208 |
|---|
| 738 | #define USBSS_IRQFRAMETHOLDTX03 0x020C |
|---|
| 739 | #define USBSS_IRQFRAMETHOLDRX00 0x0210 |
|---|
| 740 | #define USBSS_IRQFRAMETHOLDRX01 0x0214 |
|---|
| 741 | #define USBSS_IRQFRAMETHOLDRX02 0x0218 |
|---|
| 742 | #define USBSS_IRQFRAMETHOLDRX03 0x021C |
|---|
| 743 | #define USBSS_IRQFRAMETHOLDTX10 0x0220 |
|---|
| 744 | #define USBSS_IRQFRAMETHOLDTX11 0x0224 |
|---|
| 745 | #define USBSS_IRQFRAMETHOLDTX12 0x0228 |
|---|
| 746 | #define USBSS_IRQFRAMETHOLDTX13 0x022C |
|---|
| 747 | #define USBSS_IRQFRAMETHOLDRX10 0x0230 |
|---|
| 748 | #define USBSS_IRQFRAMETHOLDRX11 0x0234 |
|---|
| 749 | #define USBSS_IRQFRAMETHOLDRX12 0x0238 |
|---|
| 750 | #define USBSS_IRQFRAMETHOLDRX13 0x023C |
|---|
| 751 | #define USBSS_IRQFRAMEENABLE0 0x0240 |
|---|
| 752 | #define USBSS_IRQFRAMEENABLE1 0x0244 |
|---|
| 753 | /*---------------------------------------------------------------------------*/ |
|---|
| 754 | /* USB Controller Registers offset */ |
|---|
| 755 | #define USBCNTLR_USB0_BASE_REG_OFFSET 0x1000 /* USB0 */ |
|---|
| 756 | #define USBCNTLR_USB1_BASE_REG_OFFSET 0x1800 /* USB1 */ |
|---|
| 757 | #define USBCNTLR_REV 0x0000 |
|---|
| 758 | #define USBCNTLR_CTRL 0x0014 |
|---|
| 759 | #define USBCNTLR_STAT 0x0018 |
|---|
| 760 | #define USBCNTLR_IRQMSTAT 0x0020 |
|---|
| 761 | #define USBCNTLR_IRQSTATRAW0 0x0028 |
|---|
| 762 | #define USBCNTLR_IRQSTATRAW1 0x002C |
|---|
| 763 | #define USBCNTLR_IRQSTAT0 0x0030 |
|---|
| 764 | #define USBCNTLR_IRQSTAT1 0x0034 |
|---|
| 765 | #define USBCNTLR_IRQENABLESET0 0x0038 |
|---|
| 766 | #define USBCNTLR_IRQENABLESET1 0x003C |
|---|
| 767 | #define USBCNTLR_IRQENABLECLR0 0x0040 |
|---|
| 768 | #define USBCNTLR_IRQENABLECLR1 0x0044 |
|---|
| 769 | #define USBCNTLR_TXMODE 0x0070 |
|---|
| 770 | #define USBCNTLR_RXMODE 0x0074 |
|---|
| 771 | #define USBCNTLR_GENRNDISEP1 0x0080 |
|---|
| 772 | #define USBCNTLR_GENRNDISEP2 0x0084 |
|---|
| 773 | #define USBCNTLR_GENRNDISEP3 0x0088 |
|---|
| 774 | #define USBCNTLR_GENRNDISEP4 0x008C |
|---|
| 775 | #define USBCNTLR_GENRNDISEP5 0x0090 |
|---|
| 776 | #define USBCNTLR_GENRNDISEP6 0x0094 |
|---|
| 777 | #define USBCNTLR_GENRNDISEP7 0x0098 |
|---|
| 778 | #define USBCNTLR_GENRNDISEP8 0x009C |
|---|
| 779 | #define USBCNTLR_GENRNDISEP9 0x00A0 |
|---|
| 780 | #define USBCNTLR_GENRNDISEP10 0x00A4 |
|---|
| 781 | #define USBCNTLR_GENRNDISEP11 0x00A8 |
|---|
| 782 | #define USBCNTLR_GENRNDISEP12 0x00AC |
|---|
| 783 | #define USBCNTLR_GENRNDISEP13 0x00B0 |
|---|
| 784 | #define USBCNTLR_GENRNDISEP14 0x00B4 |
|---|
| 785 | #define USBCNTLR_GENRNDISEP15 0x00B8 |
|---|
| 786 | #define USBCNTLR_AUTOREQ 0x00D0 |
|---|
| 787 | #define USBCNTLR_SRPFIXTIME 0x00D4 |
|---|
| 788 | #define USBCNTLR_TDOWN 0x00D8 |
|---|
| 789 | #define USBCNTLR_UTMI 0x00E0 |
|---|
| 790 | #define USBCNTLR_MGCUTMILB 0x00E4 |
|---|
| 791 | #define USBCNTLR_MODE 0x00E8 |
|---|
| 792 | /*---------------------------------------------------------------------------*/ |
|---|
| 793 | /* USB PHY Registers offset */ |
|---|
| 794 | #define USBPHY_USB0_BASE_REG_OFFSET 0x1300 /* USB0 */ |
|---|
| 795 | #define USBPHY_USB1_BASE_REG_OFFSET 0x1B00 /* USB1 */ |
|---|
| 796 | #define USBPHY_TERMINATION_CNTL 0x0000 |
|---|
| 797 | #define USBPHY_RX_CALIB 0x0004 |
|---|
| 798 | #define USBPHY_DLLHS_2 0x0008 |
|---|
| 799 | #define USBPHY_RX_TEST_2 0x000C |
|---|
| 800 | #define USBPHY_CHRG_DET 0x0014 |
|---|
| 801 | #define USBPHY_PWR_CNTL 0x0018 |
|---|
| 802 | #define USBPHY_UTMI_INTERFACE_CNTL_1 0x001C |
|---|
| 803 | #define USBPHY_UTMI_INTERFACE_CNTL_2 0x0020 |
|---|
| 804 | #define USBPHY_BIST 0x0024 |
|---|
| 805 | #define USBPHY_BIST_CRC 0x0028 |
|---|
| 806 | #define USBPHY_CDR_BIST2 0x002C |
|---|
| 807 | #define USBPHY_GPIO 0x0030 |
|---|
| 808 | #define USBPHY_DLLHS 0x0034 |
|---|
| 809 | #define USBPHY_USB2PHYCM_CONFIG 0x003C |
|---|
| 810 | #define USBPHY_AD_INTERFACE_REG1 0x0044 |
|---|
| 811 | #define USBPHY_AD_INTERFACE_REG2 0x0048 |
|---|
| 812 | #define USBPHY_AD_INTERFACE_REG3 0x004C |
|---|
| 813 | #define USBPHY_ANA_CONFIG2 0x0054 |
|---|
| 814 | /*---------------------------------------------------------------------------*/ |
|---|
| 815 | /* USB Core Registers offset */ |
|---|
| 816 | #define USBCORE_USB0_BASE_REG_OFFSET 0x1400 |
|---|
| 817 | #define USBCORE_USB1_BASE_REG_OFFSET 0x1C00 |
|---|
| 818 | /*---------------------------------------------------------------------------*/ |
|---|
| 819 | /* USB CPPI DMA Controller Registers offset */ |
|---|
| 820 | #define USBCPPIDMACNTLR_BASE_REG_OFFSET 0x2000 |
|---|
| 821 | #define USBCPPIDMACNTLR_DMAREVID 0x0000 |
|---|
| 822 | #define USBCPPIDMACNTLR_TDFDQ 0x0004 |
|---|
| 823 | #define USBCPPIDMACNTLR_DMAEMU 0x0008 |
|---|
| 824 | #define USBCPPIDMACNTLR_TXGCR0 0x0800 |
|---|
| 825 | #define USBCPPIDMACNTLR_RXGCR0 0x0808 |
|---|
| 826 | #define USBCPPIDMACNTLR_RXHPCRA0 0x080C |
|---|
| 827 | #define USBCPPIDMACNTLR_RXHPCRB0 0x0810 |
|---|
| 828 | #define USBCPPIDMACNTLR_TXGCR1 0x0820 |
|---|
| 829 | #define USBCPPIDMACNTLR_RXGCR1 0x0828 |
|---|
| 830 | #define USBCPPIDMACNTLR_RXHPCRA1 0x082C |
|---|
| 831 | #define USBCPPIDMACNTLR_RXHPCRB1 0x0830 |
|---|
| 832 | #define USBCPPIDMACNTLR_TXGCR2 0x0840 |
|---|
| 833 | #define USBCPPIDMACNTLR_RXGCR2 0x0848 |
|---|
| 834 | #define USBCPPIDMACNTLR_RXHPCRA2 0x084C |
|---|
| 835 | #define USBCPPIDMACNTLR_RXHPCRB2 0x0850 |
|---|
| 836 | #define USBCPPIDMACNTLR_TXGCR3 0x0860 |
|---|
| 837 | #define USBCPPIDMACNTLR_RXGCR3 0x0868 |
|---|
| 838 | #define USBCPPIDMACNTLR_RXHPCRA3 0x086C |
|---|
| 839 | #define USBCPPIDMACNTLR_RXHPCRB3 0x0870 |
|---|
| 840 | #define USBCPPIDMACNTLR_TXGCR4 0x0880 |
|---|
| 841 | #define USBCPPIDMACNTLR_RXGCR4 0x0888 |
|---|
| 842 | #define USBCPPIDMACNTLR_RXHPCRA4 0x088C |
|---|
| 843 | #define USBCPPIDMACNTLR_RXHPCRB4 0x0890 |
|---|
| 844 | #define USBCPPIDMACNTLR_TXGCR5 0x08A0 |
|---|
| 845 | #define USBCPPIDMACNTLR_RXGCR5 0x08A8 |
|---|
| 846 | #define USBCPPIDMACNTLR_RXHPCRA5 0x08AC |
|---|
| 847 | #define USBCPPIDMACNTLR_RXHPCRB5 0x08B0 |
|---|
| 848 | #define USBCPPIDMACNTLR_TXGCR6 0x08C0 |
|---|
| 849 | #define USBCPPIDMACNTLR_RXGCR6 0x08C8 |
|---|
| 850 | #define USBCPPIDMACNTLR_RXHPCRA6 0x08CC |
|---|
| 851 | #define USBCPPIDMACNTLR_RXHPCRB6 0x08D0 |
|---|
| 852 | #define USBCPPIDMACNTLR_TXGCR7 0x08E0 |
|---|
| 853 | #define USBCPPIDMACNTLR_RXGCR7 0x08E8 |
|---|
| 854 | #define USBCPPIDMACNTLR_RXHPCRA7 0x08EC |
|---|
| 855 | #define USBCPPIDMACNTLR_RXHPCRB7 0x08F0 |
|---|
| 856 | #define USBCPPIDMACNTLR_TXGCR8 0x0900 |
|---|
| 857 | #define USBCPPIDMACNTLR_RXGCR8 0x0908 |
|---|
| 858 | #define USBCPPIDMACNTLR_RXHPCRA8 0x090C |
|---|
| 859 | #define USBCPPIDMACNTLR_RXHPCRB8 0x0910 |
|---|
| 860 | #define USBCPPIDMACNTLR_TXGCR9 0x0920 |
|---|
| 861 | #define USBCPPIDMACNTLR_RXGCR9 0x0928 |
|---|
| 862 | #define USBCPPIDMACNTLR_RXHPCRA9 0x092C |
|---|
| 863 | #define USBCPPIDMACNTLR_RXHPCRB9 0x0930 |
|---|
| 864 | #define USBCPPIDMACNTLR_TXGCR10 0x0940 |
|---|
| 865 | #define USBCPPIDMACNTLR_RXGCR10 0x0948 |
|---|
| 866 | #define USBCPPIDMACNTLR_RXHPCRA10 0x094C |
|---|
| 867 | #define USBCPPIDMACNTLR_RXHPCRB10 0x0950 |
|---|
| 868 | #define USBCPPIDMACNTLR_TXGCR11 0x0960 |
|---|
| 869 | #define USBCPPIDMACNTLR_RXGCR11 0x0968 |
|---|
| 870 | #define USBCPPIDMACNTLR_RXHPCRA11 0x096C |
|---|
| 871 | #define USBCPPIDMACNTLR_RXHPCRB11 0x0970 |
|---|
| 872 | #define USBCPPIDMACNTLR_TXGCR12 0x0980 |
|---|
| 873 | #define USBCPPIDMACNTLR_RXGCR12 0x0988 |
|---|
| 874 | #define USBCPPIDMACNTLR_RXHPCRA12 0x098C |
|---|
| 875 | #define USBCPPIDMACNTLR_RXHPCRB12 0x0990 |
|---|
| 876 | #define USBCPPIDMACNTLR_TXGCR13 0x09A0 |
|---|
| 877 | #define USBCPPIDMACNTLR_RXGCR13 0x09A8 |
|---|
| 878 | #define USBCPPIDMACNTLR_RXHPCRA13 0x09AC |
|---|
| 879 | #define USBCPPIDMACNTLR_RXHPCRB13 0x09B0 |
|---|
| 880 | #define USBCPPIDMACNTLR_TXGCR14 0x09C0 |
|---|
| 881 | #define USBCPPIDMACNTLR_RXGCR14 0x09C8 |
|---|
| 882 | #define USBCPPIDMACNTLR_RXHPCRA14 0x09CC |
|---|
| 883 | #define USBCPPIDMACNTLR_RXHPCRB14 0x09D0 |
|---|
| 884 | #define USBCPPIDMACNTLR_TXGCR15 0x09E0 |
|---|
| 885 | #define USBCPPIDMACNTLR_RXGCR15 0x09E8 |
|---|
| 886 | #define USBCPPIDMACNTLR_RXHPCRA15 0x09EC |
|---|
| 887 | #define USBCPPIDMACNTLR_RXHPCRB15 0x09F0 |
|---|
| 888 | #define USBCPPIDMACNTLR_TXGCR16 0x0A00 |
|---|
| 889 | #define USBCPPIDMACNTLR_RXGCR16 0x0A08 |
|---|
| 890 | #define USBCPPIDMACNTLR_RXHPCRA16 0x0A0C |
|---|
| 891 | #define USBCPPIDMACNTLR_RXHPCRB16 0x0A10 |
|---|
| 892 | #define USBCPPIDMACNTLR_TXGCR17 0x0A20 |
|---|
| 893 | #define USBCPPIDMACNTLR_RXGCR17 0x0A28 |
|---|
| 894 | #define USBCPPIDMACNTLR_RXHPCRA17 0x0A2C |
|---|
| 895 | #define USBCPPIDMACNTLR_RXHPCRB17 0x0A30 |
|---|
| 896 | #define USBCPPIDMACNTLR_TXGCR18 0x0A40 |
|---|
| 897 | #define USBCPPIDMACNTLR_RXGCR18 0x0A48 |
|---|
| 898 | #define USBCPPIDMACNTLR_RXHPCRA18 0x0A4C |
|---|
| 899 | #define USBCPPIDMACNTLR_RXHPCRB18 0x0A50 |
|---|
| 900 | #define USBCPPIDMACNTLR_TXGCR19 0x0A60 |
|---|
| 901 | #define USBCPPIDMACNTLR_RXGCR19 0x0A68 |
|---|
| 902 | #define USBCPPIDMACNTLR_RXHPCRA19 0x0A6C |
|---|
| 903 | #define USBCPPIDMACNTLR_RXHPCRB19 0x0A70 |
|---|
| 904 | #define USBCPPIDMACNTLR_TXGCR20 0x0A80 |
|---|
| 905 | #define USBCPPIDMACNTLR_RXGCR20 0x0A88 |
|---|
| 906 | #define USBCPPIDMACNTLR_RXHPCRA20 0x0A8C |
|---|
| 907 | #define USBCPPIDMACNTLR_RXHPCRB20 0x0A90 |
|---|
| 908 | #define USBCPPIDMACNTLR_TXGCR21 0x0AA0 |
|---|
| 909 | #define USBCPPIDMACNTLR_RXGCR21 0x0AA8 |
|---|
| 910 | #define USBCPPIDMACNTLR_RXHPCRA21 0x0AAC |
|---|
| 911 | #define USBCPPIDMACNTLR_RXHPCRB21 0x0AB0 |
|---|
| 912 | #define USBCPPIDMACNTLR_TXGCR22 0x0AC0 |
|---|
| 913 | #define USBCPPIDMACNTLR_RXGCR22 0x0AC8 |
|---|
| 914 | #define USBCPPIDMACNTLR_RXHPCRA22 0x0ACC |
|---|
| 915 | #define USBCPPIDMACNTLR_RXHPCRB22 0x0AD0 |
|---|
| 916 | #define USBCPPIDMACNTLR_TXGCR23 0x0AE0 |
|---|
| 917 | #define USBCPPIDMACNTLR_RXGCR23 0x0AE8 |
|---|
| 918 | #define USBCPPIDMACNTLR_RXHPCRA23 0x0AEC |
|---|
| 919 | #define USBCPPIDMACNTLR_RXHPCRB23 0x0AF0 |
|---|
| 920 | #define USBCPPIDMACNTLR_TXGCR24 0x0B00 |
|---|
| 921 | #define USBCPPIDMACNTLR_RXGCR24 0x0B08 |
|---|
| 922 | #define USBCPPIDMACNTLR_RXHPCRA24 0x0B0C |
|---|
| 923 | #define USBCPPIDMACNTLR_RXHPCRB24 0x0B10 |
|---|
| 924 | #define USBCPPIDMACNTLR_TXGCR25 0x0B20 |
|---|
| 925 | #define USBCPPIDMACNTLR_RXGCR25 0x0B28 |
|---|
| 926 | #define USBCPPIDMACNTLR_RXHPCRA25 0x0B2C |
|---|
| 927 | #define USBCPPIDMACNTLR_RXHPCRB25 0x0B30 |
|---|
| 928 | #define USBCPPIDMACNTLR_TXGCR26 0x0B40 |
|---|
| 929 | #define USBCPPIDMACNTLR_RXGCR26 0x0B48 |
|---|
| 930 | #define USBCPPIDMACNTLR_RXHPCRA26 0x0B4C |
|---|
| 931 | #define USBCPPIDMACNTLR_RXHPCRB26 0x0B50 |
|---|
| 932 | #define USBCPPIDMACNTLR_TXGCR27 0x0B60 |
|---|
| 933 | #define USBCPPIDMACNTLR_RXGCR27 0x0B68 |
|---|
| 934 | #define USBCPPIDMACNTLR_RXHPCRA27 0x0B6C |
|---|
| 935 | #define USBCPPIDMACNTLR_RXHPCRB27 0x0B70 |
|---|
| 936 | #define USBCPPIDMACNTLR_TXGCR28 0x0B80 |
|---|
| 937 | #define USBCPPIDMACNTLR_RXGCR28 0x0B88 |
|---|
| 938 | #define USBCPPIDMACNTLR_RXHPCRA28 0x0B8C |
|---|
| 939 | #define USBCPPIDMACNTLR_RXHPCRB28 0x0B90 |
|---|
| 940 | #define USBCPPIDMACNTLR_TXGCR29 0x0BA0 |
|---|
| 941 | #define USBCPPIDMACNTLR_RXGCR29 0x0BA8 |
|---|
| 942 | #define USBCPPIDMACNTLR_RXHPCRA29 0x0BAC |
|---|
| 943 | #define USBCPPIDMACNTLR_RXHPCRB29 0x0BB0 |
|---|
| 944 | /*---------------------------------------------------------------------------*/ |
|---|
| 945 | /* USB CPPI DMA Scheduler Registers offset */ |
|---|
| 946 | #define USBCPPIDMASCHED_BASE_REG_OFFSET 0x3000 |
|---|
| 947 | #define USBCPPIDMASCHED_CNTL 0x0000 |
|---|
| 948 | /*---------------------------------------------------------------------------*/ |
|---|
| 949 | /* USB Queue Manager Registers offset */ |
|---|
| 950 | #define USBQUEUEMNGER_BASEREG_OFFSET 0x4000 |
|---|
| 951 | #define USBQUEUEMNGER_QMGRREVID 0x0000 |
|---|
| 952 | #define USBQUEUEMNGER_QMGRRST 0x0008 |
|---|
| 953 | #define USBQUEUEMNGER_FDNSCO 0x0020 |
|---|
| 954 | #define USBQUEUEMNGER_FDNSC1 0x0024 |
|---|
| 955 | #define USBQUEUEMNGER_FDNSC2 0x0028 |
|---|
| 956 | #define USBQUEUEMNGER_FDNSC3 0x002C |
|---|
| 957 | #define USBQUEUEMNGER_FDNSC4 0x0030 |
|---|
| 958 | #define USBQUEUEMNGER_FDNSC5 0x0034 |
|---|
| 959 | #define USBQUEUEMNGER_FDNSC6 0x0038 |
|---|
| 960 | #define USBQUEUEMNGER_FDNSC7 0x003C |
|---|
| 961 | #define USBQUEUEMNGER_LRAM0BASE 0x0080 |
|---|
| 962 | #define USBQUEUEMNGER_LRAM0SIZE 0x0084 |
|---|
| 963 | #define USBQUEUEMNGER_LRAM1BASE 0x0088 |
|---|
| 964 | #define USBQUEUEMNGER_PEND0 0x0090 |
|---|
| 965 | #define USBQUEUEMNGER_PEND1 0x0094 |
|---|
| 966 | #define USBQUEUEMNGER_PEND2 0x0098 |
|---|
| 967 | #define USBQUEUEMNGER_PEND3 0x009C |
|---|
| 968 | #define USBQUEUEMNGER_PEND4 0x00A0 |
|---|
| 969 | #define USBQUEUEMNGER_QMEMRBASE0 0x1000 |
|---|
| 970 | #define USBQUEUEMNGER_QMEMCNTL0 0x1004 |
|---|
| 971 | #define USBQUEUEMNGER_QMEMRBASE1 0x1010 |
|---|
| 972 | #define USBQUEUEMNGER_QMEMCNTL1 0x1014 |
|---|
| 973 | #define USBQUEUEMNGER_QMEMRBASE2 0x1020 |
|---|
| 974 | #define USBQUEUEMNGER_QMEMCNTL2 0x1024 |
|---|
| 975 | #define USBQUEUEMNGER_QMEMRBASE3 0x1030 |
|---|
| 976 | #define USBQUEUEMNGER_QMEMCNTL3 0x1034 |
|---|
| 977 | #define USBQUEUEMNGER_QMEMRBASE4 0x1040 |
|---|
| 978 | #define USBQUEUEMNGER_QMEMCNTL4 0x1044 |
|---|
| 979 | #define USBQUEUEMNGER_QMEMRBASE5 0x1050 |
|---|
| 980 | #define USBQUEUEMNGER_QMEMCNTL5 0x1054 |
|---|
| 981 | #define USBQUEUEMNGER_QMEMRBASE6 0x1060 |
|---|
| 982 | #define USBQUEUEMNGER_QMEMCNTL6 0x1064 |
|---|
| 983 | #define USBQUEUEMNGER_QMEMRBASE7 0x1070 |
|---|
| 984 | #define USBQUEUEMNGER_QMEMCNTL7 0x1074 |
|---|
| 985 | /*===========================================================================*/ |
|---|
| 986 | |
|---|
| 987 | |
|---|
| 988 | /*===========================================================================*/ |
|---|
| 989 | /* SPI */ |
|---|
| 990 | /*===========================================================================*/ |
|---|
| 991 | /* Revision Register */ |
|---|
| 992 | #define MCSPI_REVISION 0x0000 |
|---|
| 993 | /* System Configuration Register */ |
|---|
| 994 | #define MCSPI_SYSCONFIG 0x0110 |
|---|
| 995 | /* System Status Register */ |
|---|
| 996 | #define MCSPI_SYSSTATUS 0x0114 |
|---|
| 997 | /* Interrupt Status Register offset */ |
|---|
| 998 | #define MCSPI_IRQSTATUS 0x0118 |
|---|
| 999 | /*---------------------------------------------------------------------------*/ |
|---|
| 1000 | /* Interrupt Status Register bit defines */ |
|---|
| 1001 | #define MCSPI_IRQSTATUS_RX3_FULL BIT14 |
|---|
| 1002 | #define MCSPI_IRQSTATUS_TX3_UNDERFLOW BIT13 |
|---|
| 1003 | #define MCSPI_IRQSTATUS_TX3_EMPTY BIT12 |
|---|
| 1004 | #define MCSPI_IRQSTATUS_RX2_FULL BIT10 |
|---|
| 1005 | #define MCSPI_IRQSTATUS_TX2_UNDERFLOW BIT9 |
|---|
| 1006 | #define MCSPI_IRQSTATUS_TX2_EMPTY BIT8 |
|---|
| 1007 | #define MCSPI_IRQSTATUS_RX1_FULL BIT6 |
|---|
| 1008 | #define MCSPI_IRQSTATUS_TX1_UNDERFLOW BIT5 |
|---|
| 1009 | #define MCSPI_IRQSTATUS_TX1_EMPTY BIT4 |
|---|
| 1010 | #define MCSPI_IRQSTATUS_RX0_OVERFLOW BIT3 |
|---|
| 1011 | #define MCSPI_IRQSTATUS_RX0_FULL BIT2 |
|---|
| 1012 | #define MCSPI_IRQSTATUS_TX0_UNDERFLOW BIT1 |
|---|
| 1013 | #define MCSPI_IRQSTATUS_TX0_EMPTY BIT0 |
|---|
| 1014 | /* Interrupt Enable Register offset */ |
|---|
| 1015 | #define MCSPI_IRQENABLE 0x011C |
|---|
| 1016 | /* System Register offset */ |
|---|
| 1017 | #define MCSPI_SYST 0x0124 |
|---|
| 1018 | /* Module Control Register offset */ |
|---|
| 1019 | #define MCSPI_MODULCTRL 0x0128 |
|---|
| 1020 | /*---------------------------------------------------------------------------*/ |
|---|
| 1021 | /* Configuration Registers offset */ |
|---|
| 1022 | |
|---|
| 1023 | /* Channel 0 Configuration Register offset */ |
|---|
| 1024 | #define MCSPI_CH0CONF 0x012C |
|---|
| 1025 | /* Channel 1 Configuration Register offset */ |
|---|
| 1026 | #define MCSPI_CH1CONF 0x0140 |
|---|
| 1027 | /* Channel 2 Configuration Register offset */ |
|---|
| 1028 | #define MCSPI_CH2CONF 0x0154 |
|---|
| 1029 | /* Channel 3 Configuration Register offset */ |
|---|
| 1030 | #define MCSPI_CH3CONF 0x0168 |
|---|
| 1031 | |
|---|
| 1032 | |
|---|
| 1033 | /* Configuration Register bit defines */ |
|---|
| 1034 | |
|---|
| 1035 | /* 1 = One clock cycle granularity */ |
|---|
| 1036 | #define MCSPI_CHXCONF_CLKG BIT29 |
|---|
| 1037 | /* 1 = FIFO buffer is used to Receive data */ |
|---|
| 1038 | #define MCSPI_CHXCONF_FFER BIT28 |
|---|
| 1039 | /* 1 = FIFO buffer is used to Transmit data */ |
|---|
| 1040 | #define MCSPI_CHXCONF_FFEW BIT27 |
|---|
| 1041 | /* 0.5 clock cycles between CS toggling and first (or last) edge |
|---|
| 1042 | of SPI clock */ |
|---|
| 1043 | #define MCSPI_CHXCONF_TCS_0_5 (0x00 << 25) |
|---|
| 1044 | /* 1.5 clock cycles between CS toggling and first (or last) edge |
|---|
| 1045 | of SPI clock */ |
|---|
| 1046 | #define MCSPI_CHXCONF_TCS_1_5 (0x01 << 25) |
|---|
| 1047 | /* 2.5 clock cycles between CS toggling and first (or last) edge |
|---|
| 1048 | of SPI clock */ |
|---|
| 1049 | #define MCSPI_CHXCONF_TCS_2_5 (0x02 << 25) |
|---|
| 1050 | /* 3.5 clock cycles between CS toggling and first (or last) edge |
|---|
| 1051 | of SPI clock */ |
|---|
| 1052 | #define MCSPI_CHXCONF_TCS_3_5 (0x03 << 25) |
|---|
| 1053 | /* 1 = Start bit polarity is held to 1 during SPI transfer */ |
|---|
| 1054 | #define MCSPI_CHXCONF_SBPOL BIT24 |
|---|
| 1055 | /* 1 = Start bit added before SPI transfer |
|---|
| 1056 | 0 = default length specified by WL */ |
|---|
| 1057 | #define MCSPI_CHXCONF_SBE BIT23 |
|---|
| 1058 | /* Slave select detection enabled on CS0 */ |
|---|
| 1059 | #define MCSPI_CHXCONF_SPIENSLV_0 (0x00 << 21) |
|---|
| 1060 | /* Slave select detection enabled on CS1 */ |
|---|
| 1061 | #define MCSPI_CHXCONF_SPIENSLV_1 (0x01 << 21) |
|---|
| 1062 | /* Slave select detection enabled on CS2 */ |
|---|
| 1063 | #define MCSPI_CHXCONF_SPIENSLV_2 (0x02 << 21) |
|---|
| 1064 | /* Slave select detection enabled on CS3 */ |
|---|
| 1065 | #define MCSPI_CHXCONF_SPIENSLV_3 (0x03 << 21) |
|---|
| 1066 | /* 1 = CSx high when EPOL is 0 and low whel EPOL is 1 */ |
|---|
| 1067 | #define MCSPI_CHXCONF_FORCE BIT20 |
|---|
| 1068 | /* Turbo is activated */ |
|---|
| 1069 | #define MCSPI_CHXCONF_TURBO BIT19 |
|---|
| 1070 | /* 1 = spim_simo selected for reception |
|---|
| 1071 | 0 = spim_somi selected for reception */ |
|---|
| 1072 | #define MCSPI_CHXCONF_IS BIT18 |
|---|
| 1073 | /* 1 = no transmission on spim_simo |
|---|
| 1074 | 0 = spim_simo selected for transmission */ |
|---|
| 1075 | #define MCSPI_CHXCONF_DPE1 BIT17 |
|---|
| 1076 | /* 1 = no transmission on spim_somi |
|---|
| 1077 | 0 = spim_somi selected for transmission */ |
|---|
| 1078 | #define MCSPI_CHXCONF_DPE0 BIT16 |
|---|
| 1079 | /* 1 = DMA read request enabled */ |
|---|
| 1080 | #define MCSPI_CHXCONF_DMAR BIT15 |
|---|
| 1081 | /* 1 = DMA write request enabled */ |
|---|
| 1082 | #define MCSPI_CHXCONF_DMAW BIT14 |
|---|
| 1083 | /* Transmit and receive mode */ |
|---|
| 1084 | #define MCSPI_CHXCONF_TRM_TR (0x00 << 12) |
|---|
| 1085 | /* Receive-only mode */ |
|---|
| 1086 | #define MCSPI_CHXCONF_TRM_RO (0x01 << 12) |
|---|
| 1087 | /* Transmit-only mode */ |
|---|
| 1088 | #define MCSPI_CHXCONF_TRM_TO (0x02 << 12) |
|---|
| 1089 | /* SPI word length, 0x7 = 8-bit */ |
|---|
| 1090 | #define MCSPI_CHXCONF_WL(_x_) ((_x_ & 0x1f) << 7) |
|---|
| 1091 | /* 1 = SPIM_CSx is low during active state, |
|---|
| 1092 | 0 = high during active state */ |
|---|
| 1093 | #define MCSPI_CHxCONF_EPOL BIT6 |
|---|
| 1094 | /* Frequency divider for spim_clk */ |
|---|
| 1095 | #define MCSPI_CHXCONF_CLKD(_x_) ((_x_ & 0xf) << 2) |
|---|
| 1096 | /* 1 = spim_clk is low during active state |
|---|
| 1097 | 0 = high during active state */ |
|---|
| 1098 | #define MCSPI_CHXCONF_POL BIT1 |
|---|
| 1099 | /* 1 = data latched on even-numbered edges |
|---|
| 1100 | 0 = data latched on odd-numbered edges */ |
|---|
| 1101 | #define MCSPI_CHXCONF_PHA BIT0 |
|---|
| 1102 | /*---------------------------------------------------------------------------*/ |
|---|
| 1103 | /* Status Registers offset */ |
|---|
| 1104 | #define MCSPI_CH0STAT 0x0130 // Channel 0 Status Register |
|---|
| 1105 | #define MCSPI_CH1STAT 0x0144 // Channel 1 Status Register |
|---|
| 1106 | #define MCSPI_CH2STAT 0x0158 // Channel 2 Status Register |
|---|
| 1107 | #define MCSPI_CH3STAT 0x016C // Channel 3 Status Register |
|---|
| 1108 | /* Status Register bit defines */ |
|---|
| 1109 | #define MCSPI_CHXSAT_RXF_FULL BIT6 |
|---|
| 1110 | #define MCSPI_CHXSAT_RXF_EMPTY BIT5 |
|---|
| 1111 | #define MCSPI_CHXSAT_TXF_FULL BIT4 |
|---|
| 1112 | #define MCSPI_CHXSAT_TXF_EMPTY BIT3 |
|---|
| 1113 | #define MCSPI_CHXSAT_EOT BIT2 |
|---|
| 1114 | #define MCSPI_CHXSAT_TX0_EMPTY BIT1 |
|---|
| 1115 | #define MCSPI_CHXSAT_RX0_FULL BIT0 |
|---|
| 1116 | /*---------------------------------------------------------------------------*/ |
|---|
| 1117 | /* Control Registers offset */ |
|---|
| 1118 | #define MCSPI_CH0CTRL 0x0134 // Channel 0 Control Register offset |
|---|
| 1119 | #define MCSPI_CH1CTRL 0x0148 // Channel 1 Control Register offset |
|---|
| 1120 | #define MCSPI_CH2CTRL 0x015C // Channel 2 Control Register offset |
|---|
| 1121 | #define MCSPI_CH3CTRL 0x0170 // Channel 3 Control Register offset |
|---|
| 1122 | /*---------------------------------------------------------------------------*/ |
|---|
| 1123 | /* FIFO Buffer Registers offset */ |
|---|
| 1124 | |
|---|
| 1125 | /* Channel 0 FIFO Transmit Buffer Register offset */ |
|---|
| 1126 | #define MCSPI_TX0 0x0138 |
|---|
| 1127 | /* Channel 0 FIFO Receive Buffer Register offset */ |
|---|
| 1128 | #define MCSPI_RX0 0x013C |
|---|
| 1129 | /* Channel 1 FIFO Transmit Buffer Register offset */ |
|---|
| 1130 | #define MCSPI_TX1 0x014C |
|---|
| 1131 | /* Channel 1 FIFO Receive Buffer Register offset */ |
|---|
| 1132 | #define MCSPI_RX1 0x0150 |
|---|
| 1133 | /* Channel 2 FIFO Transmit Buffer Register offset */ |
|---|
| 1134 | #define MCSPI_TX2 0x0160 |
|---|
| 1135 | /* Channel 2 FIFO Receive Buffer Register offset */ |
|---|
| 1136 | #define MCSPI_RX2 0x0164 |
|---|
| 1137 | /* Channel 3 FIFO Transmit Buffer Register offset */ |
|---|
| 1138 | #define MCSPI_TX3 0x0174 |
|---|
| 1139 | /* Channel 3 FIFO Receive Buffer Register offset */ |
|---|
| 1140 | #define MCSPI_RX3 0x0178 |
|---|
| 1141 | /*---------------------------------------------------------------------------*/ |
|---|
| 1142 | /* Transfer Levels Register */ |
|---|
| 1143 | #define MCSPI_XFERLEVEL 0x017C |
|---|
| 1144 | /* DMA Address Aligned FIFO Transmitter Register */ |
|---|
| 1145 | #define MCSPI_DAFTX 0x0180 |
|---|
| 1146 | /* DMA Address Aligned FIFO Receiver Register */ |
|---|
| 1147 | #define MCSPI_DAFRX 0x01A0 |
|---|
| 1148 | /*===========================================================================*/ |
|---|
| 1149 | |
|---|
| 1150 | |
|---|
| 1151 | /*===========================================================================*/ |
|---|
| 1152 | /* General Purpose I/O */ |
|---|
| 1153 | /*===========================================================================*/ |
|---|
| 1154 | /* GPIO0 Registers */ |
|---|
| 1155 | #define GPIO0_BASE (L4_WKUP_BASE + 0x00207000) |
|---|
| 1156 | #define GPIO0_REG(_x_) *(vulong *)(GPIO0_BASE + _x_) |
|---|
| 1157 | /* GPIO1 Registers */ |
|---|
| 1158 | #define GPIO1_BASE (L4_PER_BASE + 0x0004C000) |
|---|
| 1159 | #define GPIO1_REG(_x_) *(vulong *)(GPIO1_BASE + _x_) |
|---|
| 1160 | /* GPIO2 Registers */ |
|---|
| 1161 | #define GPIO2_BASE (L4_PER_BASE + 0x001AC000) |
|---|
| 1162 | #define GPIO2_REG(_x_) *(vulong *)(GPIO2_BASE + _x_) |
|---|
| 1163 | /* GPIO3 Registers */ |
|---|
| 1164 | #define GPIO3_BASE (L4_PER_BASE + 0x001AE000) |
|---|
| 1165 | #define GPIO3_REG(_x_) *(vulong *)(GPIO3_BASE + _x_) |
|---|
| 1166 | /*---------------------------------------------------------------------------*/ |
|---|
| 1167 | /* GPIOx Register offsets */ |
|---|
| 1168 | #define GPIOX_REVISION 0x0000 |
|---|
| 1169 | #define GPIOX_SYSCONFIG 0x0010 |
|---|
| 1170 | #define GPIOX_EOI 0x0020 |
|---|
| 1171 | #define GPIOX_IRQSTATUS_RAW_0 0x0024 |
|---|
| 1172 | #define GPIOX_IRQSTATUS_RAW_1 0x0028 |
|---|
| 1173 | #define GPIOX_IRQSTATUS_0 0x002C |
|---|
| 1174 | #define GPIOX_IRQSTATUS_1 0x0030 |
|---|
| 1175 | #define GPIOX_IRQSTATUS_SET_0 0x0034 |
|---|
| 1176 | #define GPIOX_IRQSTATUS_SET_1 0x0038 |
|---|
| 1177 | #define GPIOX_IRQSTATUS_CLR_0 0x003C |
|---|
| 1178 | #define GPIOX_IRQSTATUS_CLR_1 0x0040 |
|---|
| 1179 | #define GPIOX_IRQWAKEN_0 0x0044 |
|---|
| 1180 | #define GPIOX_IRQWAKEN_1 0x0048 |
|---|
| 1181 | #define GPIOX_SYSSTATUS 0x0114 |
|---|
| 1182 | #define GPIOX_CTRL 0x0130 |
|---|
| 1183 | #define GPIOX_OE 0x0134 |
|---|
| 1184 | #define GPIOX_DATAIN 0x0138 |
|---|
| 1185 | #define GPIOX_DATAOUT 0x013C |
|---|
| 1186 | #define GPIOX_LEVELDETECT0 0x0140 |
|---|
| 1187 | #define GPIOX_LEVELDETECT1 0x0144 |
|---|
| 1188 | #define GPIOX_RISINGDETECT 0x0148 |
|---|
| 1189 | #define GPIOX_FALLINGDETECT 0x014C |
|---|
| 1190 | #define GPIOX_DEBOUNCEENABLE 0x0150 |
|---|
| 1191 | #define GPIOX_DEBOUNCINGTIME 0x0154 |
|---|
| 1192 | #define GPIOX_CLEARDATAOUT 0x0190 |
|---|
| 1193 | #define GPIOX_SETDATAOUT 0x0194 |
|---|
| 1194 | /*===========================================================================*/ |
|---|
| 1195 | |
|---|
| 1196 | |
|---|
| 1197 | /*===========================================================================*/ |
|---|
| 1198 | /* Watchdog Timer */ |
|---|
| 1199 | /*===========================================================================*/ |
|---|
| 1200 | /* Watchdog Timer Registers offset*/ |
|---|
| 1201 | #define WDT1_BASE (L4_WKUP_BASE + 0x00235000) |
|---|
| 1202 | #define WDT1_REG(_x_) *(vulong *)(WDT1_BASE + _x_) |
|---|
| 1203 | /*---------------------------------------------------------------------------*/ |
|---|
| 1204 | /* WatchDog Timer Register offsets */ |
|---|
| 1205 | |
|---|
| 1206 | /* Watchdow Identification Register */ |
|---|
| 1207 | #define WDT1_WIDR 0x00 |
|---|
| 1208 | /* Watchdog System Control Register */ |
|---|
| 1209 | #define WDT1_WDSC 0x10 |
|---|
| 1210 | /* Watchdog Status Register */ |
|---|
| 1211 | #define WDT1_WDST 0x14 |
|---|
| 1212 | /* Watchdog Interrupt Status Register */ |
|---|
| 1213 | #define WDT1_WISR 0x18 |
|---|
| 1214 | /* Watchdog Interrupt Enable Register */ |
|---|
| 1215 | #define WDT1_WIER 0x1C |
|---|
| 1216 | /* Watchdog Control Register */ |
|---|
| 1217 | #define WDT1_WCLR 0x24 |
|---|
| 1218 | /* Watchdog Counter Register */ |
|---|
| 1219 | #define WDT1_WCRR 0x28 |
|---|
| 1220 | /* Watchdog Load Register */ |
|---|
| 1221 | #define WDT1_WLDR 0x2C |
|---|
| 1222 | /* Watchdog Trigger Register */ |
|---|
| 1223 | #define WDT1_WTGR 0x30 |
|---|
| 1224 | /* Watchdog Write Posting Bits Register */ |
|---|
| 1225 | #define WDT1_WWPS 0x34 |
|---|
| 1226 | /* Watchdog Delay Configuration Register */ |
|---|
| 1227 | #define WDT1_WDLY 0x44 |
|---|
| 1228 | /* Watchdog Start/Stop Register */ |
|---|
| 1229 | #define WDT1_WSPR 0x48 |
|---|
| 1230 | /* Watchdog Raw Interrupt Status Register */ |
|---|
| 1231 | #define WDT1_WIRQSTATRAW 0x54 |
|---|
| 1232 | /* Watchdog Interrupt Status Register */ |
|---|
| 1233 | #define WDT1_WIRQSTAT 0x58 |
|---|
| 1234 | /* Watchdog Interrupt Enable Set Register */ |
|---|
| 1235 | #define WDT1_WIRQENSET 0x5C |
|---|
| 1236 | /* Watchdog Interrupt Enable Clear Register */ |
|---|
| 1237 | #define WDT1_WIRQENCLR 0x60 |
|---|
| 1238 | /*===========================================================================*/ |
|---|
| 1239 | |
|---|
| 1240 | |
|---|
| 1241 | /*===========================================================================*/ |
|---|
| 1242 | /* MMC */ |
|---|
| 1243 | /*===========================================================================*/ |
|---|
| 1244 | /* MMCHS0 Registers base */ |
|---|
| 1245 | #define MMCHS0_BASE (L4_PER_BASE + 0x00060000) |
|---|
| 1246 | #define MMCHS0_REG(_x_) *(vulong *)(MMCHS0_BASE + _x_) |
|---|
| 1247 | /* MMC Registers base */ |
|---|
| 1248 | #define MMC1_BASE (L4_PER_BASE + 0x001D8000) |
|---|
| 1249 | #define MMC1_REG(_x_) *(vulong *)(MMC1_BASE + _x_) |
|---|
| 1250 | /*---------------------------------------------------------------------------*/ |
|---|
| 1251 | /* MMC Register offsets */ |
|---|
| 1252 | |
|---|
| 1253 | /* System Configuration */ |
|---|
| 1254 | #define SD_SYSCONFIG 0x0110 |
|---|
| 1255 | #define SD_SYSCONFIG_CLOCKACTIVITY 0x00000300 |
|---|
| 1256 | #define SD_SYSCONFIG_SIDLEMODE 0x00000018 |
|---|
| 1257 | #define SD_SYSCONFIG_SIDLEMODE_IDLE 0x00000000 |
|---|
| 1258 | #define SD_SYSCONFIG_SIDLEMODE_IGNORE 0x00000008 |
|---|
| 1259 | #define SD_SYSCONFIG_SIDLEMODE_WKUP 0x00000010 |
|---|
| 1260 | #define SD_SYSCONFIG_ENAWAKEUP 0x00000004 |
|---|
| 1261 | #define SD_SYSCONFIG_ENAWAKEUP_DISABLE 0x00000000 |
|---|
| 1262 | #define SD_SYSCONFIG_ENAWAKEUP_ENABLE 0x00000004 |
|---|
| 1263 | #define SD_SYSCONFIG_SOFTRESET 0x00000002 |
|---|
| 1264 | #define SD_SYSCONFIG_AUTOIDLE 0x00000001 |
|---|
| 1265 | #define SD_SYSCONFIG_AUTOIDLE_AUTOGATE 0x00000001 |
|---|
| 1266 | /* System Status */ |
|---|
| 1267 | #define SD_SYSSTATUS 0x0114 |
|---|
| 1268 | #define SD_SYSSTATUS_RESETDONE 0x00000001 |
|---|
| 1269 | /* Card Status Response Error */ |
|---|
| 1270 | #define SD_CSRE 0x0124 |
|---|
| 1271 | /* System Test */ |
|---|
| 1272 | #define SD_SYSTEST 0x0128 |
|---|
| 1273 | /* Configuration */ |
|---|
| 1274 | #define SD_CON 0x012C |
|---|
| 1275 | #define SD_CON_SDMA_LNE 0x00200000 |
|---|
| 1276 | #define SD_CON_DMA_MNS 0x00100000 |
|---|
| 1277 | #define SD_CON_DDR 0x00080000 |
|---|
| 1278 | #define SD_CON_BOOT_CF0 0x00040000 |
|---|
| 1279 | #define SD_CON_BOOT_ACK 0x00020000 |
|---|
| 1280 | #define SD_CON_CLKEXTFREE 0x00010000 |
|---|
| 1281 | #define SD_CON_PADEN 0x00008000 |
|---|
| 1282 | #define SD_CON_CEATA 0x00001000 |
|---|
| 1283 | #define SD_CON_CTPL 0x00000800 |
|---|
| 1284 | #define SD_CON_DVAL 0x00000600 |
|---|
| 1285 | #define SD_CON_DVAL_33US 0x00000000 |
|---|
| 1286 | #define SD_CON_DVAL_231US 0x00000200 |
|---|
| 1287 | #define SD_CON_DVAL_1MS 0x00000400 |
|---|
| 1288 | #define SD_CON_DVAL_840US 0x00000600 |
|---|
| 1289 | #define SD_CON_WPP 0x00000100 |
|---|
| 1290 | #define SD_CON_CDP 0x00000080 |
|---|
| 1291 | #define SD_CON_CDP_ACTIVE_LOW 0x00000080 |
|---|
| 1292 | #define SD_CON_CDP_ACTIVE_HIGH 0x00000000 |
|---|
| 1293 | #define SD_CON_MIT 0x00000040 |
|---|
| 1294 | #define SD_CON_DW8 0x00000020 |
|---|
| 1295 | #define SD_CON_DW8_1BIT_OR_4BIT 0x00000000 |
|---|
| 1296 | #define SD_CON_DW8_8BIT 0x00000020 |
|---|
| 1297 | #define SD_CON_MODE 0x00000010 |
|---|
| 1298 | #define SD_CON_MODE_SYSTEST 0x00000010 |
|---|
| 1299 | #define SD_CON_MODE_NORMAL 0x00000000 |
|---|
| 1300 | #define SD_CON_STR 0x00000008 |
|---|
| 1301 | #define SD_CON_HR 0x00000004 |
|---|
| 1302 | #define SD_CON_INIT 0x00000002 |
|---|
| 1303 | #define SD_CON_INIT_START 0x00000002 |
|---|
| 1304 | #define SD_CON_INIT_END 0x00000000 |
|---|
| 1305 | #define SD_CON_OD 0x00000001 |
|---|
| 1306 | #define SD_CON_OD_ENABLE 0x00000001 |
|---|
| 1307 | #define SD_CON_OD_DISABLE 0x00000000 |
|---|
| 1308 | /* Power Counter */ |
|---|
| 1309 | #define SD_PWCNT 0x0130 |
|---|
| 1310 | /* SDMA System Address */ |
|---|
| 1311 | #define SD_SDMASA 0x0200 |
|---|
| 1312 | /* Transfer Length Configuration */ |
|---|
| 1313 | #define SD_BLK 0x0204 |
|---|
| 1314 | #define SD_BLK_512_BYTES 0x00000200 |
|---|
| 1315 | /* Command Argument */ |
|---|
| 1316 | #define SD_ARG 0x0208 |
|---|
| 1317 | /* Command and Transfer Mode */ |
|---|
| 1318 | #define SD_CMD 0x020C |
|---|
| 1319 | #define SD_CMD_CMD0_GO_IDLE_STATE 0x00000000 |
|---|
| 1320 | #define SD_CMD_CMD0_GO_PRE_IDLE_STATE 0x00000000 |
|---|
| 1321 | #define SD_CMD_CMD0_BOOT_INITIATION 0x00000000 |
|---|
| 1322 | #define SD_CMD_CMD1_SEND_OP_COND 0x01000000 |
|---|
| 1323 | #define SD_CMD_CMD2_ALL_SEND_CID 0x02000000 |
|---|
| 1324 | #define SD_CMD_CMD3_SEND_RELATIVE_ADDR 0x03000000 |
|---|
| 1325 | #define SD_CMD_CMD3_SET_RELATIVE_ADDR 0x03000000 |
|---|
| 1326 | #define SD_CMD_CMD4_SET_DSR 0x04000000 |
|---|
| 1327 | #define SD_CMD_CMD5_SLEEP_AWAKE 0x05000000 |
|---|
| 1328 | #define SD_CMD_CMD6_SWITCH_FUNC 0x06000000 |
|---|
| 1329 | #define SD_CMD_CMD6_SWITCH 0x06000000 |
|---|
| 1330 | #define SD_CMD_CMD7_SELECT_DESELECT_CARD 0x07000000 |
|---|
| 1331 | #define SD_CMD_CMD8_SEND_IF_COND 0x08000000 |
|---|
| 1332 | #define SD_CMD_CMD8_SEND_EXT_CSD 0x08000000 |
|---|
| 1333 | #define SD_CMD_CMD9_SEND_CSD 0x09000000 |
|---|
| 1334 | #define SD_CMD_CMD10_SEND_CID 0x0A000000 |
|---|
| 1335 | #define SD_CMD_CMD11_READ_DAT 0x0B000000 |
|---|
| 1336 | #define SD_CMD_CMD12_STOP_TRANSMISSION 0x0C000000 |
|---|
| 1337 | #define SD_CMD_CMD13_SEND_STATUS 0x0D000000 |
|---|
| 1338 | #define SD_CMD_CMD14_BUSTEST_R 0x0E000000 |
|---|
| 1339 | #define SD_CMD_CMD15_GO_INACTIVE_STATE 0x0F000000 |
|---|
| 1340 | #define SD_CMD_CMD16_SET_BLOCKLEN 0x10000000 |
|---|
| 1341 | #define SD_CMD_CMD17_READ_SINGLE_BLOCK 0x11000000 |
|---|
| 1342 | #define SD_CMD_CMD18_READ_MULTIPLE_BLOCK 0x12000000 |
|---|
| 1343 | #define SD_CMD_CMD19_BUSTEST_W 0x13000000 |
|---|
| 1344 | #define SD_CMD_CMD20_WRITE_DAT_UNTIL_STOP 0x14000000 |
|---|
| 1345 | #define SD_CMD_CMD24_WRITE_BLOCK 0x18000000 |
|---|
| 1346 | #define SD_CMD_CMD25_WRITE_MULTIPLE_BLOCK 0x19000000 |
|---|
| 1347 | #define SD_CMD_CMD26_PROGRAM_CID 0x1A000000 |
|---|
| 1348 | #define SD_CMD_CMD27_PROGRAM_CSD 0x1B000000 |
|---|
| 1349 | #define SD_CMD_CMD28_SET_WRITE_PROT 0x1C000000 |
|---|
| 1350 | #define SD_CMD_CMD29_CLR_WRITE_PROT 0x1D000000 |
|---|
| 1351 | #define SD_CMD_CMD30_SEND_WRITE_PROT 0x1E000000 |
|---|
| 1352 | #define SD_CMD_CMD31_SEND_WRITE_PROT_TYPE 0x1F000000 |
|---|
| 1353 | #define SD_CMD_CMD32_ERASE_WR_BLK_START 0x20000000 |
|---|
| 1354 | #define SD_CMD_CMD33_ERASE_WR_BLK_END 0x21000000 |
|---|
| 1355 | #define SD_CMD_CMD35_ERASE_GROUP_START 0x23000000 |
|---|
| 1356 | #define SD_CMD_CMD36_ERASE_GROUP_END 0x24000000 |
|---|
| 1357 | #define SD_CMD_CMD38_ERASE 0x26000000 |
|---|
| 1358 | #define SD_CMD_CMD39_FAST_IO 0x27000000 |
|---|
| 1359 | #define SD_CMD_CMD40_GO_IRQ_STATE 0x28000000 |
|---|
| 1360 | #define SD_CMD_CMD42_LOCK_UNLOCK 0x2A000000 |
|---|
| 1361 | #define SD_CMD_CMD55_APP_CMD 0x37000000 |
|---|
| 1362 | #define SD_CMD_CMD56_GEN_CMD 0x38000000 |
|---|
| 1363 | |
|---|
| 1364 | #define SD_CMD_ACMD6_SET_BUS_WIDTH 0x06000000 |
|---|
| 1365 | #define SD_CMD_ACMD13_SD_STATUS 0x0D000000 |
|---|
| 1366 | #define SD_CMD_ACMD22_SEND_NUM_WR_BLOCKS 0x16000000 |
|---|
| 1367 | #define SD_CMD_ACMD23_SET_WR_BLK_ERASE_COUNT 0x17000000 |
|---|
| 1368 | #define SD_CMD_ACMD41_SD_SEND_OP_COND 0x29000000 |
|---|
| 1369 | #define SD_CMD_ACMD42_SET_CLR_CARD_DETECT 0x2A000000 |
|---|
| 1370 | #define SD_CMD_ACMD51_SEND_SCR 0x33000000 |
|---|
| 1371 | |
|---|
| 1372 | #define SD_CMD_CMD_TYPE_NORMAL 0x00000000 |
|---|
| 1373 | #define SD_CMD_CMD_TYPE_SUSPEND 0x00400000 |
|---|
| 1374 | #define SD_CMD_CMD_TYPE_RESUME 0x00800000 |
|---|
| 1375 | #define SD_CMD_CMD_TYPE_ABORT 0x00C00000 |
|---|
| 1376 | |
|---|
| 1377 | #define SD_CMD_DP_NO_DATA_PRESENT 0x00000000 |
|---|
| 1378 | #define SD_CMD_DP_DATA_PRESENT 0x00200000 |
|---|
| 1379 | |
|---|
| 1380 | #define SD_CMD_CICE_DISABLE 0x00000000 |
|---|
| 1381 | #define SD_CMD_CICE_ENABLE 0x00100000 |
|---|
| 1382 | |
|---|
| 1383 | #define SD_CMD_CCCE_DISABLE 0x00000000 |
|---|
| 1384 | #define SD_CMD_CCCE_ENABLE 0x00080000 |
|---|
| 1385 | |
|---|
| 1386 | #define RSP_TYPE_NO_RESPONSE 0x00000000 |
|---|
| 1387 | #define RSP_TYPE_136 0x00010000 |
|---|
| 1388 | #define RSP_TYPE_48 0x00020000 |
|---|
| 1389 | #define RSP_TYPE_48_WITH_BUSY 0x00030000 |
|---|
| 1390 | #define SD_CMD_RSP_TYPE_NO_RESPONSE RSP_TYPE_NO_RESPONSE |
|---|
| 1391 | #define SD_CMD_RSP_TYPE_R1 RSP_TYPE_48 |
|---|
| 1392 | #define SD_CMD_RSP_TYPE_R1B RSP_TYPE_48_WITH_BUSY |
|---|
| 1393 | #define SD_CMD_RSP_TYPE_R2 RSP_TYPE_136 |
|---|
| 1394 | #define SD_CMD_RSP_TYPE_R3 RSP_TYPE_48 |
|---|
| 1395 | #define SD_CMD_RSP_TYPE_R4 RSP_TYPE_48 |
|---|
| 1396 | #define SD_CMD_RSP_TYPE_R5 RSP_TYPE_48 |
|---|
| 1397 | #define SD_CMD_RSP_TYPE_R5B RSP_TYPE_48_WITH_BUSY |
|---|
| 1398 | #define SD_CMD_RSP_TYPE_R6 RSP_TYPE_48 |
|---|
| 1399 | #define SD_CMD_RSP_TYPE_R7 RSP_TYPE_48 |
|---|
| 1400 | |
|---|
| 1401 | #define SD_CMD_MSBS_SINGLE 0x00000000 |
|---|
| 1402 | #define SD_CMD_MSBS_MULTIPLE 0x00000020 |
|---|
| 1403 | |
|---|
| 1404 | #define SD_CMD_DDIR_WRITE 0x00000000 |
|---|
| 1405 | #define SD_CMD_DDIR_READ 0x00000010 |
|---|
| 1406 | |
|---|
| 1407 | #define SD_CMD_ACEN_DISABLE 0x00000000 |
|---|
| 1408 | #define SD_CMD_ACEN_CMD12_ENABLE 0x00000004 |
|---|
| 1409 | |
|---|
| 1410 | #define SD_CMD_BCE_DISABLE 0x00000000 |
|---|
| 1411 | #define SD_CMD_BCE_ENABLE 0x00000002 |
|---|
| 1412 | |
|---|
| 1413 | #define SD_CMD_DE_DISABLE 0x00000000 |
|---|
| 1414 | #define SD_CMD_DE_ENABLE 0x00000001 |
|---|
| 1415 | |
|---|
| 1416 | /* Command Response 0 and 1 */ |
|---|
| 1417 | #define SD_RSP10 0x0210 |
|---|
| 1418 | #define SD_RSP10_R1_CURRENT_STATE 0x00001E00 |
|---|
| 1419 | #define SD_RSP10_R1_CURRENT_STATE_IDLE 0x00000000 |
|---|
| 1420 | #define SD_RSP10_R1_CURRENT_STATE_READY 0x00000200 |
|---|
| 1421 | #define SD_RSP10_R1_CURRENT_STATE_IDENTIFICATION 0x00000400 |
|---|
| 1422 | #define SD_RSP10_R1_CURRENT_STATE_STANDBY 0x00000600 |
|---|
| 1423 | #define SD_RSP10_R1_CURRENT_STATE_TRANSFER 0x00000800 |
|---|
| 1424 | #define SD_RSP10_R1_CURRENT_STATE_SENDING_DATA 0x00000A00 |
|---|
| 1425 | #define SD_RSP10_R1_CURRENT_STATE_RECEIVE_DATA 0x00000C00 |
|---|
| 1426 | #define SD_RSP10_R1_CURRENT_STATE_PROGRAMMING 0x00000E00 |
|---|
| 1427 | #define SD_RSP10_R1_CURRENT_STATE_DISCONNECT 0x00001000 |
|---|
| 1428 | #define SD_RSP10_R3_CARD_CAPACITY_STATUS 0x40000000 |
|---|
| 1429 | #define SD_RSP10_R3_CARD_POWER_UP_STATUS 0x80000000 |
|---|
| 1430 | /* Command Response 2 and 3 */ |
|---|
| 1431 | #define SD_RSP32 0x0214 |
|---|
| 1432 | /* Command Response 4 and 5 */ |
|---|
| 1433 | #define SD_RSP54 0x0218 |
|---|
| 1434 | /* Command Response 6 and 7 */ |
|---|
| 1435 | #define SD_RSP76 0x021C |
|---|
| 1436 | /* Data */ |
|---|
| 1437 | #define SD_DATA 0x0220 |
|---|
| 1438 | /* Present State */ |
|---|
| 1439 | #define SD_PSTATE 0x0224 |
|---|
| 1440 | #define SD_PSTATE_CLEV 0x01000000 |
|---|
| 1441 | #define SD_PSTATE_DLEV 0x00F00000 |
|---|
| 1442 | #define SD_PSTATE_DLEV_DAT0 0x00100000 |
|---|
| 1443 | #define SD_PSTATE_WP 0x00080000 |
|---|
| 1444 | #define SD_PSTATE_CDPL 0x00040000 |
|---|
| 1445 | #define SD_PSTATE_CSS 0x00020000 |
|---|
| 1446 | #define SD_PSTATE_CINS 0x00010000 |
|---|
| 1447 | #define SD_PSTATE_BRE 0x00000800 |
|---|
| 1448 | #define SD_PSTATE_BWE 0x00000400 |
|---|
| 1449 | #define SD_PSTATE_RTA 0x00000200 |
|---|
| 1450 | #define SD_PSTATE_WTA 0x00000100 |
|---|
| 1451 | #define SD_PSTATE_DLA 0x00000004 |
|---|
| 1452 | #define SD_PSTATE_DATI 0x00000002 |
|---|
| 1453 | #define SD_PSTATE_CMDI 0x00000001 |
|---|
| 1454 | /* Host Control */ |
|---|
| 1455 | #define SD_HCTL 0x0228 |
|---|
| 1456 | #define SD_HCTL_SDVS 0x00000E00 |
|---|
| 1457 | #define SD_HCTL_SDVS_VS18 0x00000A00 |
|---|
| 1458 | #define SD_HCTL_SDVS_VS30 0x00000C00 |
|---|
| 1459 | #define SD_HCTL_SDVS_VS33 0x00000E00 |
|---|
| 1460 | #define SD_HCTL_SDBP 0x00000100 |
|---|
| 1461 | #define SD_HCTL_DMAS 0x00000180 |
|---|
| 1462 | #define SD_HCTL_DMAS_32BIT_ADDR_ADMA2 0x00000010 |
|---|
| 1463 | #define SD_HCTL_DTW 0x00000002 |
|---|
| 1464 | #define SD_HCTL_DTW_1BIT 0x00000000 |
|---|
| 1465 | #define SD_HCTL_DTW_4BIT 0x00000002 |
|---|
| 1466 | /* SD System Control */ |
|---|
| 1467 | #define SD_SYSCTL 0x022C |
|---|
| 1468 | #define SD_SYSCTL_SRC 0x02000000 |
|---|
| 1469 | #define SD_SYSCTL_SRA 0x01000000 |
|---|
| 1470 | #define SD_SYSCTL_DTO 0x000F0000 |
|---|
| 1471 | #define SD_SYSCTL_DTO_TCF_2_13 0x00000000 |
|---|
| 1472 | #define SD_SYSCTL_DTO_TCF_2_14 0x00010000 |
|---|
| 1473 | #define SD_SYSCTL_DTO_TCF_2_27 0x000E0000 |
|---|
| 1474 | #define SD_SYSCTL_CLKD 0x0000FFC0 |
|---|
| 1475 | #define SD_SYSCTL_CEN 0x00000004 |
|---|
| 1476 | #define SD_SYSCTL_CEN_ENABLE 0x00000004 |
|---|
| 1477 | #define SD_SYSCTL_ICS 0x00000002 |
|---|
| 1478 | #define SD_SYSCTL_ICE 0x00000001 |
|---|
| 1479 | #define SD_SYSCTL_ICE_ENABLE 0x00000001 |
|---|
| 1480 | /* SD Interrupt Status */ |
|---|
| 1481 | #define SD_STAT 0x0230 |
|---|
| 1482 | #define SD_STAT_BADA 0x20000000 |
|---|
| 1483 | #define SD_STAT_CERR 0x10000000 |
|---|
| 1484 | #define SD_STAT_ADMAE 0x02000000 |
|---|
| 1485 | #define SD_STAT_ACE 0x01000000 |
|---|
| 1486 | #define SD_STAT_DEB 0x00400000 |
|---|
| 1487 | #define SD_STAT_DCRC 0x00200000 |
|---|
| 1488 | #define SD_STAT_DTO 0x00100000 |
|---|
| 1489 | #define SD_STAT_CIE 0x00080000 |
|---|
| 1490 | #define SD_STAT_CEB 0x00040000 |
|---|
| 1491 | #define SD_STAT_CCRC 0x00020000 |
|---|
| 1492 | #define SD_STAT_CTO 0x00010000 |
|---|
| 1493 | #define SD_STAT_ERRI 0x00008000 |
|---|
| 1494 | #define SD_STAT_BSR 0x00000400 |
|---|
| 1495 | #define SD_STAT_OBI 0x00000200 |
|---|
| 1496 | #define SD_STAT_CIRQ 0x00000100 |
|---|
| 1497 | #define SD_STAT_CREM 0x00000080 |
|---|
| 1498 | #define SD_STAT_CINS 0x00000040 |
|---|
| 1499 | #define SD_STAT_BRR 0x00000020 |
|---|
| 1500 | #define SD_STAT_BWR 0x00000010 |
|---|
| 1501 | #define SD_STAT_DMA 0x00000008 |
|---|
| 1502 | #define SD_STAT_BGE 0x00000004 |
|---|
| 1503 | #define SD_STAT_TC 0x00000002 |
|---|
| 1504 | #define SD_STAT_CC 0x00000001 |
|---|
| 1505 | /* SD Interrupt Enable */ |
|---|
| 1506 | #define SD_IE 0x0234 |
|---|
| 1507 | #define SD_IE_BADA_ENABLE 0x20000000 |
|---|
| 1508 | #define SD_IE_CERR_ENABLE 0x10000000 |
|---|
| 1509 | #define SD_IE_ADMA_ENABLE 0x02000000 |
|---|
| 1510 | #define SD_IE_ACE_ENABLE 0x01000000 |
|---|
| 1511 | #define SD_IE_DEB_ENABLE 0x00400000 |
|---|
| 1512 | #define SD_IE_DCRC_ENABLE 0x00200000 |
|---|
| 1513 | #define SD_IE_DTO_ENABLE 0x00100000 |
|---|
| 1514 | #define SD_IE_CIE_ENABLE 0x00080000 |
|---|
| 1515 | #define SD_IE_CEB_ENABLE 0x00040000 |
|---|
| 1516 | #define SD_IE_CCRC_ENABLE 0x00020000 |
|---|
| 1517 | #define SD_IE_CTO_ENABLE 0x00010000 |
|---|
| 1518 | #define SD_IE_BSR_ENABLE 0x00000400 |
|---|
| 1519 | #define SD_IE_OBI_ENABLE 0x00000200 |
|---|
| 1520 | #define SD_IE_CIRQ_ENABLE 0x00000100 |
|---|
| 1521 | #define SD_IE_CREM_ENABLE 0x00000080 |
|---|
| 1522 | #define SD_IE_CINS_ENABLE 0x00000040 |
|---|
| 1523 | #define SD_IE_BRR_ENABLE 0x00000020 |
|---|
| 1524 | #define SD_IE_BWR_ENABLE 0x00000010 |
|---|
| 1525 | #define SD_IE_DMA_ENABLE 0x00000008 |
|---|
| 1526 | #define SD_IE_BGE_ENABLE 0x00000004 |
|---|
| 1527 | #define SD_IE_TC_ENABLE 0x00000002 |
|---|
| 1528 | #define SD_IE_CC_ENABLE 0x00000001 |
|---|
| 1529 | /* SD Interrupt Enable Set */ |
|---|
| 1530 | #define SD_ISE 0x0238 |
|---|
| 1531 | /* Auto CMD12 Error Status */ |
|---|
| 1532 | #define SD_AC12 0x023C |
|---|
| 1533 | /* Capabilities */ |
|---|
| 1534 | #define SD_CAPA 0x0240 |
|---|
| 1535 | #define SD_CAPA_VS18 0x04000000 |
|---|
| 1536 | #define SD_CAPA_VS30 0x02000000 |
|---|
| 1537 | #define SD_CAPA_VS33 0x01000000 |
|---|
| 1538 | /* Maximum Current Capabilities */ |
|---|
| 1539 | #define SD_CUR_CAPA 0x0148 |
|---|
| 1540 | /* Force Event */ |
|---|
| 1541 | #define SD_FE 0x0250 |
|---|
| 1542 | /* ADMA Error Status */ |
|---|
| 1543 | #define SD_ADMAES 0x0254 |
|---|
| 1544 | /* ADMA System Address Low bits */ |
|---|
| 1545 | #define SD_ADMASAL 0x0258 |
|---|
| 1546 | /* ADMA System Address High bits */ |
|---|
| 1547 | #define SD_ADMASAH 0x025C |
|---|
| 1548 | /* Versions */ |
|---|
| 1549 | #define SD_REV 0x02FC |
|---|
| 1550 | /*===========================================================================*/ |
|---|
| 1551 | |
|---|
| 1552 | #endif /* AM335X_H */ |
|---|
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