1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief AM335x Register Base Addresses and Offsets |
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5 | * |
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6 | * @ingroup am335x |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (C) 2015 Jarielle Catbagan <jcatbagan93@gmail.com> |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.apache.org/licenses/LICENSE-2.0 |
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15 | * |
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16 | * |
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17 | * Description: This file contains register base addresses and offsets as |
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18 | * well as access macros for the AM335x on-chip peripherals. Peripherals |
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19 | * not used by Umon have not been test (and may not be defined). Use |
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20 | * these defines with caution! |
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21 | */ |
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22 | |
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23 | #ifndef AM335X_H |
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24 | #define AM335X_H |
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25 | |
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26 | #include "bits.h" |
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27 | |
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28 | |
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29 | /*===========================================================================*/ |
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30 | /* AM335x device identification and feature enumeration */ |
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31 | /*===========================================================================*/ |
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32 | #define AM335X_DEVICE_IDENTIFICATION 0x44E10600 |
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33 | #define AM335X_DEVICE_FEATURE 0x44E10604 |
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34 | /*===========================================================================*/ |
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35 | |
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36 | |
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37 | /*===========================================================================*/ |
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38 | /* L3 and L4 Interconnects */ |
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39 | /*===========================================================================*/ |
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40 | #define L3F_CFG_REGS_BASE 0x44000000 |
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41 | #define L3S_CFG_REGS_BASE 0x44800000 |
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42 | #define L4_WKUP_BASE 0x44C00000 |
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43 | #define L4_PER_BASE 0x48000000 |
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44 | #define L4_FAST_BASE 0x4A000000 |
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45 | /*===========================================================================*/ |
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46 | |
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47 | |
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48 | /*===========================================================================*/ |
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49 | /* EMIF0 Configuration Registers */ |
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50 | /*===========================================================================*/ |
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51 | #define EMIF0_BASE 0x4C000000 |
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52 | #define EMIFO_REG(_x_) *(vulong *)(EMIFO_BASE + _x_) |
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53 | /*---------------------------------------------------------------------------*/ |
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54 | /* EMIFO Register offsets */ |
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55 | #define EMIF_MOD_ID_REV 0x0000 |
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56 | #define STATUS 0x0004 |
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57 | #define SDRAM_CONFIG 0x0008 |
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58 | #define SDRAM_CONFIG_2 0x000C |
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59 | #define SDRAM_REF_CTRL 0x0010 |
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60 | #define SDRAM_REF_CTRL_SHOW 0x0014 |
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61 | #define SDRAM_TIM_1 0x0018 |
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62 | #define SDRAM_TIM_1_SHDW 0x001C |
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63 | #define SDRAM_TIM_2 0x0020 |
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64 | #define SDRAM_TIM_2_SHDW 0x0024 |
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65 | #define SDRAM_TIM_3 0x0028 |
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66 | #define SDRAM_TIM_3_SHDW 0x002C |
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67 | #define PWR_MGMT_CTRL 0x0038 |
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68 | #define PWR_MGMT_CTRL_SHDW 0x003C |
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69 | #define INTERFACE_CONFIG 0x0054 |
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70 | #define INTERFACE_CONFIG_VAL_1 0x0058 |
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71 | #define INTERFACE_CONFIG_VAL_2 0x005C |
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72 | #define PERF_CNT_1 0x0080 |
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73 | #define PERF_CNT_2 0x0084 |
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74 | #define PERF_CNT_CFG 0x0088 |
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75 | #define PERF_CNT_SEL 0x008C |
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76 | #define PERF_CNT_TIM 0x0090 |
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77 | #define READ_IDLE_CTRL 0x0098 |
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78 | #define READ_IDLE_CTRL_SHDW 0x009C |
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79 | #define IRQSTATUS_RAW_SYS 0x00A4 |
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80 | #define IRQSTATUS_SYS 0x00AC |
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81 | #define IRQENABLE_SET_SYS 0x00B4 |
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82 | #define IRQENABLE_CLR_SYS 0x00BC |
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83 | #define ZQ_CONFIG 0x00C8 |
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84 | #define RW_LVL_RAMP_WNDW 0x00D4 |
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85 | #define RW_LVL_RAMP_CTRL 0x00D8 |
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86 | #define RW_LVL_CTRL 0x00DC |
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87 | #define DDR_PHY_CTRL_1 0x00E4 |
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88 | #define DDR_PHY_CTRL_1_SHDW 0x00E8 |
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89 | #define PRIORITY_TO_CLASS_SRVC_MAP 0x0100 |
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90 | #define CONN_ID_TO_CLASS_SRVC_1_MAP 0x0104 |
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91 | #define CONN_ID_TO_CLASS_SRVC_2_MAP 0x0108 |
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92 | #define RW_EXEC_THRESHOLD 0x0120 |
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93 | /*===========================================================================*/ |
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94 | |
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95 | |
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96 | /*===========================================================================*/ |
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97 | /* McASPx Data Registers */ |
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98 | /*===========================================================================*/ |
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99 | #define MCASP0_DATA_REGS_BASE 0x46000000 |
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100 | #define MCASP1_DATE_REGS_BASE 0x46400000 |
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101 | /*===========================================================================*/ |
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102 | |
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103 | |
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104 | /*===========================================================================*/ |
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105 | /* L4_WKUP Peripherals */ |
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106 | /*===========================================================================*/ |
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107 | /* Clock Module Peripheral Registers */ |
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108 | #define CM_PER_BASE (L4_WKUP_BASE + 0x00200000) |
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109 | #define CM_PER_REG(_x_) *(vulong *)(CM_PER_BASE + _x_) |
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110 | /* Clock Module Wakeup Registers */ |
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111 | #define CM_WKUP_BASE (L4_WKUP_BASE + 0x00200400) |
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112 | #define CM_WKUP_REG(_x_) *(vulong *)(CM_WKUP_BASE + _x_) |
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113 | /* Clock Module PLL Registers */ |
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114 | #define CM_DPLL_BASE (L4_WKUP_BASE + 0x00200500) |
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115 | #define CM_DPLL_REG(_x_) *(vulong *)(CM_DPLL_BASE + _x_) |
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116 | /* Clock Module MPU Registers */ |
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117 | #define CM_MPU_BASE (L4_WKUP_BASE + 0x00200600) |
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118 | #define CM_MPU_REG(_x_) *(vulong *)(CM_MPU_BASE + _x_) |
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119 | /* Clock Module Device Registers */ |
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120 | #define CM_DEVICE_BASE (L4_WKUP_BASE + 0x00200700) |
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121 | #define CM_DEVICE_REG(_x_) *(vulong *)(CM_DEVICE_BASE + _x_) |
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122 | /* Clock Module RTC Registers */ |
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123 | #define CM_RTC_BASE (L4_WKUP_BASE + 0x00200800) |
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124 | #define CM_RTC_REG(_x_) *(vulong *)(CM_RTC_BASE + _x_) |
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125 | /* Clock Module Graphics Controller Registers */ |
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126 | #define CM_GFX_BASE (L4_WKUP_BASE + 0x00200900) |
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127 | #define CM_GFX_REG(_x_) *(vulong *)(CM_GFX_BASE + _x_) |
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128 | /* Clock Module Efuse Registers */ |
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129 | #define CM_CEFUSE_BASE (L4_WKUP_BASE + 0x00200A00) |
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130 | #define CM_CEFUSE_REG(_x_) *(vulong *)(CM_CEFUSE_BASE + _x_) |
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131 | /* Power Reset Module Interrupt Registers */ |
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132 | #define PRM_IRQ_BASE (L4_WKUP_BASE + 0x00200B00) |
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133 | #define PRM_IRQ_REG(_x_) *(vulong *)(PRM_IRQ_BASE + _x_) |
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134 | /* Power Reset Module Peripheral Registers */ |
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135 | #define PRM_PER_BASE (L4_WKUP_BASE + 0x00200C00) |
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136 | #define PRM_PER_REG(_x_) *(vulong *)(PRM_PER_BASE + _x_) |
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137 | /* Power Reset Module Wakeup Registers */ |
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138 | #define PRM_WKUP_BASE (L4_WKUP_BASE + 0x00200D00) |
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139 | #define PRM_WKUP_REG(_x_) *(vulong *)(PRM_WKUP_BASE + _x_) |
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140 | /* Power Reset Module MPU Registers */ |
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141 | #define PRM_MPU_BASE (L4_WKUP_BASE + 0x00200E00) |
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142 | #define PRM_MPU_REG(_x_) *(vulong *)(PRM_MPU_BASE + _x_) |
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143 | /* Power Reset Module Device Registers */ |
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144 | #define PRM_DEV_BASE (L4_WKUP_BASE + 0x00200F00) |
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145 | #define PRM_DEV_REG(_x_) *(vulong *)(PRM_DEV_BASE + _x_) |
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146 | /* Power Reset Module RTC Registers */ |
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147 | #define PRM_RTC_BASE (L4_WKUP_BASE + 0x00201000) |
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148 | #define PRM_RTC_REG(_x_) *(vulong *)(PRM_RTC_BASE + _x_) |
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149 | /* Power Reset Module Graphics Controller Registers */ |
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150 | #define PRM_GFX_BASE (L4_WKUP_BASE + 0x00201100) |
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151 | #define PRM_GFX_REG(_x_) *(vulong *)(PRM_GFX_BASE + _x_) |
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152 | /* Power Reset Module Efuse Registers */ |
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153 | #define PRM_CEFUSE_BASE (L4_WKUP_BASE + 0x00201200) |
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154 | #define PRM_CEFUSE_REG(_x_) *(vulong *)(PRM_CEFUSE_BASE + _x_) |
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155 | /* DMTimer0 Registers */ |
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156 | #define DMTIMER0_BASE (L4_WKUP_BASE + 0x00205000) |
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157 | #define DMTIMER0_REG(_x_) *(vulong *)(DMTIMER0_BASE + _x_) |
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158 | /* UART0 Registers */ |
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159 | #define UART0_BASE (L4_WKUP_BASE + 0x00209000) |
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160 | #define UART0_REG(_x_) *(vulong *)(UART0_BASE + _x_) |
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161 | /* I2C0 Registers */ |
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162 | #define I2C0_BASE (L4_WKUP_BASE + 0x0020B000) |
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163 | #define I2C0_REG(_x_) *(vulong *)(I2C0_BASE + _x_) |
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164 | /* ADC_TSC Registers */ |
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165 | #define ADC_TSC_BASE (L4_WKUP_BASE + 0x0020D000) |
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166 | #define ADC_TSC_REG(_x_) *(vulong *)(ADC_TSC_BASE + _x_) |
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167 | /* Control Module */ |
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168 | #define CNTL_MODULE_BASE (L4_WKUP_BASE + 0x00210000) |
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169 | #define CNTL_MODULE_REG(_x_) *(vulong *)(CNTL_MODULE_BASE + _x_) |
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170 | /* DDR2/3/mDDR PHY Registers */ |
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171 | #define DDR_PHY_BASE (L4_WKUP_BASE + 0x00212000) |
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172 | #define DDR_PHY_REG(_x_) *(vulong *)(DDR_PHY_BASE + _x_) |
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173 | /* DMTimer1 1ms Registers */ |
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174 | #define DMTIMER1_1MS_BASE (L4_WKUP_BASE + 0x00231000) |
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175 | #define DMTIMER1_1MS_REG(_x_) *(vulong *)(DMTIMER1_1MS_BASE + _x_) |
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176 | /* L3 Registers */ |
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177 | #define SMARTREFLEX0_BASE (L4_WKUP_BASE + 0x00237000) |
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178 | #define SMARTREFLEX0_REG(_x_) *(vulong *)(SMARTREFLEX0_BASE + _x_) |
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179 | #define SMARTREFLEX1_BASE (L4_WKUP_BASE + 0x00239000) |
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180 | #define SMARTREFLEX1_REG(_x_) *(vulong *)(SMARTREFLEX1_BASE + _x_) |
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181 | /* RTC Registers */ |
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182 | #define RTCSS_BASE (L4_WKUP_BASE + 0x0023E000) |
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183 | #define RTCSS_REG(_x_) *(vulong *)(RTCSS_BASE + _x_) |
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184 | /* Debug Registers */ |
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185 | #define DEBUGSS_HWMSTR1_BASE (L4_WKUP_BASE + 0x00240000) |
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186 | #define DEBUGSS_HWMSTR1_REG(_x_) *(vulong *)(DEBUGSS_HWMSTR1_BASE + _x_) |
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187 | /*===========================================================================*/ |
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188 | |
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189 | |
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190 | /*===========================================================================*/ |
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191 | /* CM_WKUP Registers */ |
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192 | /*===========================================================================*/ |
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193 | #define CM_WKUP_CLKSTCTRL 0x00 |
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194 | #define CM_WKUP_CONTROL_CLKCTRL 0x04 |
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195 | #define CM_WKUP_GPIO0_CLKCTRL 0x08 |
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196 | #define CM_WKUP_L4WKUP_CLKCTRL 0x0C |
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197 | #define CM_WKUP_TIMER0_CLKCTRL 0x10 |
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198 | #define CM_WKUP_DEBUGSS_CLKCTRL 0x14 |
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199 | #define CM_L3_AON_CLKSTCTRL 0x18 |
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200 | #define CM_AUTOIDLE_DPLL_MPU 0x1C |
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201 | #define CM_IDLEST_DPLL_MPU 0x20 |
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202 | #define CM_SSC_DELTAMSTEP_DPLL_MPU 0x24 |
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203 | #define CM_SSC_MODFREQDIV_DPLL_MPU 0x28 |
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204 | #define CM_CLKSEL_DPLL_MPU 0x2C |
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205 | #define CM_AUTOIDLE_DPLL_DDR 0x30 |
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206 | #define CM_IDLEST_DPLL_DDR 0x34 |
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207 | #define CM_SSC_DELTAMSTEP_DPLL_DDR 0x38 |
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208 | #define CM_SSC_MODFREQDIV_DPLL_DDR 0x3C |
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209 | #define CM_CLKSEL_DPLL_DDR 0x40 |
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210 | #define CM_AUTOIDLE_DPLL_DISP 0x44 |
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211 | #define CM_IDLEST_DPLL_DISP 0x48 |
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212 | #define CM_SSC_DELTAMSTEP_DPLL_DISP 0x4C |
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213 | #define CM_SSC_MODFREQDIV_DPLL_DISP 0x50 |
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214 | #define CM_CLKSEL_DPLL_DISP 0x54 |
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215 | #define CM_AUTOIDLE_DPLL_CORE 0x58 |
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216 | #define CM_IDLEST_DPLL_CORE 0x5C |
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217 | #define CM_SSC_DELTAMSTEP_DPLL_CORE 0x60 |
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218 | #define CM_SSC_MODFREQDIV_DPLL_CORE 0x64 |
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219 | #define CM_CLKSEL_DPLL_CORE 0x68 |
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220 | #define CM_AUTOIDLE_DPLL_PER 0x6C |
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221 | #define CM_IDLEST_DPLL_PER 0x70 |
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222 | #define CM_SSC_DELTAMSTEP_DPLL_PER 0x74 |
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223 | #define CM_SSC_MODFREQDIV_DPLL_PER 0x78 |
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224 | #define CM_CLKDCOLDO_DPLL_PER 0x7C |
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225 | #define CM_DIV_M4_DPLL_CORE 0x80 |
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226 | #define CM_DIV_M5_DPLL_CORE 0x84 |
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227 | #define CM_CLKMODE_DPLL_MPU 0x88 |
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228 | #define CM_CLKMODE_DPLL_PER 0x8C |
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229 | #define CM_CLKMODE_DPLL_CORE 0x90 |
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230 | #define CM_CLKMODE_DPLL_DDR 0x94 |
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231 | #define CM_CLKMODE_DPLL_DISP 0x98 |
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232 | #define CM_CLKSEL_DPLL_PERIPH 0x9C |
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233 | #define CM_DIV_M2_DPLL_DDR 0xA0 |
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234 | #define CM_DIV_M3_DPLL_DISP 0xA4 |
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235 | #define CM_DIV_M3_DPLL_MPU 0xA8 |
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236 | #define CM_DIV_M3_DPLL_PER 0xAC |
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237 | #define CM_WKUP_WKUP_M3_CLKCTRL 0xB0 |
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238 | #define CM_WKUP_UART0_CLKCTRL 0xB4 |
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239 | #define CM_WKUP_I2C0_CLKCTRL 0xB8 |
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240 | #define CM_WKUP_ADC_TSC_CLKCTRL 0xBC |
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241 | #define CM_WKUP_SMARTREFLEX0_CLKCT 0xC0 |
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242 | #define CM_WKUP_TIMER1_CLKCTRL 0xC4 |
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243 | #define CM_WKUP_SMARTREFLEX1_CLKCT 0xC8 |
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244 | #define CM_L4_WKUP_AON_CLKSTCTRL 0xCC |
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245 | #define CM_WKUP_WDT1_CLKCTRL 0xD4 |
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246 | #define CM_DIV_M6_DPLL_CORE 0xD8 |
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247 | /*===========================================================================*/ |
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248 | |
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249 | |
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250 | /*===========================================================================*/ |
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251 | /* Control Module Registers */ |
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252 | /*===========================================================================*/ |
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253 | #define CONF_UART0_RXD 0x0970 |
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254 | #define CONF_UART0_TXD 0x0974 |
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255 | /*===========================================================================*/ |
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256 | |
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257 | |
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258 | /*===========================================================================*/ |
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259 | /* Pad control bits: */ |
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260 | /*===========================================================================*/ |
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261 | #define SLEWSLOW (1 << 6) |
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262 | #define SLEWFAST 0 |
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263 | #define RX_ON (1 << 5) |
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264 | #define RX_OFF 0 |
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265 | #define PULLUP (1 << 4) |
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266 | #define PULLDOWN 0 |
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267 | #define PULL_OFF (1 << 3) |
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268 | #define PULL_ON 0 |
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269 | #define MUXMODE_0 (0 & 7) |
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270 | #define MUXMODE_1 (1 & 7) |
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271 | #define MUXMODE_2 (2 & 7) |
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272 | #define MUXMODE_3 (3 & 7) |
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273 | #define MUXMODE_4 (4 & 7) |
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274 | #define MUXMODE_5 (5 & 7) |
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275 | #define MUXMODE_6 (6 & 7) |
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276 | #define MUXMODE_7 (7 & 7) |
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277 | /*===========================================================================*/ |
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278 | |
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279 | |
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280 | /*===========================================================================*/ |
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281 | /* L4_PER Peripherals */ |
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282 | /*===========================================================================*/ |
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283 | /* UART1 Registers */ |
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284 | #define UART1_BASE (L4_PER_BASE + 0x00022000) |
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285 | #define UART1_REG(_x_) *(vulong *)(UART1_BASE + _x_) |
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286 | /* UART2 Registers */ |
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287 | #define UART2_BASE (L4_PER_BASE + 0x00024000) |
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288 | #define UART2_REG(_x_) *(vulong *)(UART2_BASE + _x_) |
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289 | /* I2C1 Registers */ |
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290 | #define I2C1_BASE (L4_PER_BASE + 0x0002A000) |
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291 | #define I2C1_REG(_x_) *(vulong *)(I2C1_BASE + _x_) |
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292 | /* McSPI0 Registers */ |
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293 | #define MCSPI0_BASE (L4_PER_BASE + 0x00030000) |
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294 | #define MCSPI0_REG(_x_) *(vulong *)(MCSPI0_BASE + _x_) |
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295 | /* McASP0 CFG Registers */ |
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296 | #define MCASP0_CFG_BASE (L4_PER_BASE + 0x00038000) |
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297 | #define MCASP0_CFG_REG(_x_) *(vulong *)(MCASP0_CFG_BASE + _x_) |
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298 | /* McASP1 CFG Registers */ |
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299 | #define MCASP1_CFG_BASE (L4_PER_BASE + 0x0003C000) |
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300 | #define MCASP1_CFG_REG(_x_) *(vulong *)(MCASP1_CFG_BASE + _x_) |
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301 | /* DMTimer2 Registers */ |
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302 | #define DMTIMER2_BASE (L4_PER_BASE + 0x00040000) |
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303 | #define DMTIMER2_REG(_x_) *(vulong *)(DMTIMER2_BASE + _x_) |
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304 | /* DMTimer3 Registers */ |
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305 | #define DMTIMER3_BASE (L4_PER_BASE + 0x00042000) |
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306 | #define DMTIMER3_REG(_x_) *(vulong *)(DMTIMER3_BASE + _x_) |
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307 | /* DMTimer4 Registers */ |
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308 | #define DMTIMER4_BASE (L4_PER_BASE + 0x00044000) |
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309 | #define DMTIMER4_REG(_x_) *(vulong *)(DMTIMER4_BASE + _x_) |
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310 | /* DMTimer5 Registers */ |
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311 | #define DMTIMER5_BASE (L4_PER_BASE + 0x00046000) |
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312 | #define DMTIMER5_REG(_x_) *(vulong *)(DMTIMER5_BASE + _x_) |
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313 | /* DMTimer6 Registers */ |
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314 | #define DMTIMER6_BASE (L4_PER_BASE + 0x00048000) |
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315 | #define DMTIMER6_REG(_x_) *(vulong *)(DMTIMER6_BASE + _x_) |
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316 | /* DMTimer7 Registers */ |
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317 | #define DMTIMER7_BASE (L4_PER_BASE + 0x0004A000) |
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318 | #define DMTIMER7_REG(_x_) *(vulong *)(DMTIMER7_BASE + _x_) |
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319 | /* MMCHS0 Registers */ |
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320 | #define MMCHS0_BASE (L4_PER_BASE + 0x00060000) |
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321 | #define MMCHS0_REG(_x_) *(vulong *)(MMCHS0_BASE + _x_) |
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322 | /* ELM Registers */ |
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323 | #define ELM_BASE (L4_PER_BASE + 0x00080000) |
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324 | #define ELM_REG(_x_) *(vulong *)(ELM_BASE + _x_) |
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325 | /* Mailbox 0 Registers */ |
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326 | #define MAILBOX0_BASE (L4_PER_BASE + 0x000C8000) |
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327 | #define MAILBOX0_REG(_x_) *(vulong *)(MAILBOX0_BASE + _x_) |
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328 | /* Spinlock Registers */ |
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329 | #define SPINLOCK_BASE (L4_PER_BASE + 0x000CA000) |
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330 | #define SPINLOCK_REG(_x_) *(vulong *)(SPINLOCK_BASE + _x_) |
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331 | /* OCP Watchpoint Registers */ |
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332 | #define OCP_WATCHPOINT_BASE (L4_PER_BASE + 0x0018C000) |
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333 | #define OCP_WATCHPOINT_REG(_x_) *(vulong *)(OCP_WATCHPOINT_BASE + _x_) |
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334 | /* I2C2 Registers */ |
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335 | #define I2C2_BASE (L4_PER_BASE + 0x0019C000) |
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336 | #define I2C2_REG(_x_) *(vulong *)(I2C2_BASE + _x_) |
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337 | /* McSPI1 Registers */ |
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338 | #define MCSPI1_BASE (L4_PER_BASE + 0x001A0000) |
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339 | #define MCSPI1_REG(_x_) *(vulong *)(MSCPI1_BASE + _x_) |
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340 | /* UART3 Registers */ |
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341 | #define UART3_BASE (L4_PER_BASE + 0x001A6000) |
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342 | #define UART3_REG(_x_) *(vulong *)(UART3_BASE + _x_) |
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343 | /* UART4 Registers */ |
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344 | #define UART4_BASE (L4_PER_BASE + 0x001A8000) |
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345 | #define UART4_REG(_x_) *(vulong *)(UART4_BASE + _x_) |
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346 | /* UART5 Registers */ |
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347 | #define UART5_BASE (L4_PER_BASE + 0x001AA000) |
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348 | #define UART5_REG(_x_) *(vulong *)(UART5_BASE + _x_) |
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349 | /* DCAN0 Registers */ |
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350 | #define DCAN0_BASE (L4_PER_BASE + 0x001CC000) |
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351 | #define DCAN0_REG(_x_) *(vulong *)(DCAN0_BASE + _x_) |
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352 | /* DCAN1 Registers */ |
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353 | #define DCAN1_BASE (L4_PER_BASE + 0x001D0000) |
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354 | #define DCAN1_REG(_x_) *(vulong *)(DCAN1_BASE + _x_) |
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355 | /* Interrupt Controller Registers */ |
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356 | #define INTCPS_BASE (L4_PER_BASE + 0x00200000) |
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357 | #define INTCPS_REG(_x_) *(vulong *)(INTCPS_BASE + _x_) |
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358 | /* MPUSS Config Register */ |
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359 | #define MPUSS_BASE (L4_PER_BASE + 0x00240000) |
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360 | #define MPUSS_REG(_x_) *(vulong *)(MPUSS_BASE + _x_) |
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361 | /* PWMSS0 Configuration Registers */ |
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362 | #define PWMSS0_BASE (L4_PER_BASE + 0x00300000) |
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363 | #define PWMSS0_REG(_x_) *(vulong *)(PWMSS0_BASE + _x_) |
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364 | /* PWMSS eCAP0 Registers */ |
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365 | #define ECAP0_BASE (L4_PER_BASE + 0x00300100) |
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366 | #define ECAP0_REG(_x_) *(vulong *)(ECAP0_BASE + _x_) |
---|
367 | /* PWMSS eQEP0 Registers */ |
---|
368 | #define EQEP0_BASE (L4_PER_BASE + 0x00300180) |
---|
369 | #define EQEP0_REG(_x_) *(vulong *)(EQEP0_BASE + _x_) |
---|
370 | /* PWMSS ePWM0 Registers */ |
---|
371 | #define EPWM0_BASE (L4_PER_BASE + 0x00300200) |
---|
372 | #define EPWM0_REG(_x_) *(vulong *)(EPWM0_BASE + _x_) |
---|
373 | /* PWMSS1 Configuration Registers */ |
---|
374 | #define PWMSS1_BASE (L4_PER_BASE + 0x00302000) |
---|
375 | #define PWMSS1_REG(_x_) *(vulong *)(PWMSS1_BASE + _x_) |
---|
376 | /* PWMSS eCAP1 Registers */ |
---|
377 | #define ECAP1_BASE (L4_PER_BASE + 0x00302100) |
---|
378 | #define ECAP1_REG(_x_) *(vulong *)(ECAP1_BASE + _x_) |
---|
379 | /* PWMSS eQEP1 Registers */ |
---|
380 | #define EQEP1_BASE (L4_PER_BASE + 0x00302180) |
---|
381 | #define EQEP1_REG(_x_) *(vulong *)(EQEP1_BASE + _x_) |
---|
382 | /* PWMSS ePWM1 Registers */ |
---|
383 | #define EPWM1_BASE (L4_PER_BASE + 0x00302200) |
---|
384 | #define EPWM1_REG(_x_) *(vulong *)(EPwM_BASE + _x_) |
---|
385 | /* PWMSS2 Configuration Registers */ |
---|
386 | #define PWMSS2_BASE (L4_PER_BASE + 0x00304000) |
---|
387 | #define PWMSS2_REG(_x_) *(vulong *)(PWMSS2_BASE + _x_) |
---|
388 | /* PWMSS eCAP2 Registers */ |
---|
389 | #define ECAP2_BASE (L4_PER_BASE + 0x00304100) |
---|
390 | #define ECAP2_REG(_x_) *(vulong *)(ECAP2_BASE + _x_) |
---|
391 | /* PWMSS eQEP2 Registers */ |
---|
392 | #define EQEP2_BASE (L4_PER_BASE + 0x00304180) |
---|
393 | #define EQEP2_REG(_x_) *(vulong *)(EQEP2_BASE + _x_) |
---|
394 | /* PWMSS ePWM2 Registers */ |
---|
395 | #define EPWM2_BASE (L4_PER_BASE + 0x00304200) |
---|
396 | #define EPWM2_REG(_x_) *(vulong *)(EPWM2_BASE + _x_) |
---|
397 | /* LCD Contoller Registers */ |
---|
398 | #define LCD_CNTLR_BASE (L4_PER_BASE + 0x0030E000) |
---|
399 | #define LCD_CNTLR_REG(_x_) *(vulong *)(LCD_CNTLR_BASE + _x_) |
---|
400 | /*===========================================================================*/ |
---|
401 | |
---|
402 | |
---|
403 | /*===========================================================================*/ |
---|
404 | /* L4_FAST Peripherals */ |
---|
405 | /*===========================================================================*/ |
---|
406 | #define L4_FAST_BASE 0x4A000000 |
---|
407 | /* Ethernet Switch Subsystem Registers */ |
---|
408 | #define CPSW_SS_BASE (LF_FAST_BASE + 0x00100000) |
---|
409 | #define CPSW_SS_REG(_x_) *(vulong *)(CPSW_SS_BASE + _x_) |
---|
410 | /* Ethernet Switch Port Control Registers */ |
---|
411 | #define CPSW_PORT_BASE (LF_FAST_BASE + 0x00100100) |
---|
412 | #define CPSW_PORT_REG(_x_) *(vulong *)(CPSW_PORT_BASE + _x_) |
---|
413 | /* CPPI DMA Controller Module Registers */ |
---|
414 | #define CPSW_CPDMA_BASE (LF_FAST_BASE + 0x00100800) |
---|
415 | #define CPSW_CPDMA_REG(_x_) *(vulong *)(CPSW_CPDMA_BASE + _x_) |
---|
416 | /* Ethernet Statistics Registers */ |
---|
417 | #define CPSW_STATS_BASE (LF_FAST_BASE + 0x00100900) |
---|
418 | #define CPSW_STATS_REG(_x_) *(vulong *)(CPSW_STATS_BASE + _x_) |
---|
419 | /* CPPI DMA State RAM Registers */ |
---|
420 | #define CPSW_STATERAM_BASE (LF_FAST_BASE + 0x00100A00) |
---|
421 | #define CPSW_STATERAM_REG(_x_) *(vulong *)(CPSW_STATERAM_BASE + _x_) |
---|
422 | /* Ethenet Time Sync Module Registers */ |
---|
423 | #define CPSW_CPTS_BASE (LF_FAST_BASE + 0x00100C00) |
---|
424 | #define CPSW_CPTS_REG(_x_) *(vulong *)(CPSW_CPTS_BASE + _x_) |
---|
425 | /* Ethernet Address Lookup Engine Registers */ |
---|
426 | #define CPSW_ALE_BASE (LF_FAST_BASE + 0x00100D00) |
---|
427 | #define CPSW_ALE_REG(_x_) *(vulong *)(CPSW_ALE_BASE + _x_) |
---|
428 | /* Ethernet Silver for Port 1 Registers */ |
---|
429 | #define CPSW_SL1_BASE (LF_FAST_BASE + 0x00100D80) |
---|
430 | #define CPSW_SL1_REG(_x_) *(vulong *)(CPSW_SL1_BASE + _x_) |
---|
431 | /* Ethernet Silver for Port 2 Registers */ |
---|
432 | #define CPSW_SL2_BASE (LF_FAST_BASE + 0x00100DC0) |
---|
433 | #define CPSW_SL2_REG(_x_) *(vulong *)(CPSW_SL2_BASE + _x_) |
---|
434 | /* Ethernet MDIO Controller Registers */ |
---|
435 | #define MDIO_BASE (LF_FAST_BASE + 0x00101000) |
---|
436 | #define MDIO_REG(_x_) *(vulong *)(MDIO_BASE + _x_) |
---|
437 | /* Ethernet Subsystem Wrapper for RMII/RGMII Registers */ |
---|
438 | #define CPSW_WR_BASE (LF_FAST_BASE + 0x00101200) |
---|
439 | #define CPSW_WR_REG(_x_) *(vulong *)(CPSW_WR_BASE + _x_) |
---|
440 | /*===========================================================================*/ |
---|
441 | |
---|
442 | |
---|
443 | /*===========================================================================*/ |
---|
444 | /* UART Register offsets */ |
---|
445 | /*===========================================================================*/ |
---|
446 | /* Transmit Holding Register (write only) */ |
---|
447 | #define UART_THR 0x00 |
---|
448 | /* Receive Holding Register (read only) */ |
---|
449 | #define UART_RHR 0x00 |
---|
450 | /* Baud divisor lower byte (read/write) */ |
---|
451 | #define UART_DLL 0x00 |
---|
452 | /* Interrupt Enable Register (read/write) */ |
---|
453 | #define UART_IER 0x04 |
---|
454 | /* Baud divisor higher byte (read/write) */ |
---|
455 | #define UART_DLH 0x04 |
---|
456 | /* Enhanced Feature Register */ |
---|
457 | #define UART_EFR 0x08 |
---|
458 | /* Interrupt Identification Register (read only) */ |
---|
459 | #define UART_IIR 0x08 |
---|
460 | /* FIFO Control Register (write only) */ |
---|
461 | #define UART_FCR 0x08 |
---|
462 | /* Line Control Register (read/write) */ |
---|
463 | #define UART_LCR 0x0C |
---|
464 | /* Modem Control Register (read/write) */ |
---|
465 | #define UART_MCR 0x10 |
---|
466 | /* XON1/ADDR1 Register */ |
---|
467 | #define UART_XON1_ADDR1 0x10 |
---|
468 | /* XON2/ADDR2 Register */ |
---|
469 | #define UART_XON2_ADDR2 0x14 |
---|
470 | /* Line Status Register (read only) */ |
---|
471 | #define UART_LSR 0x14 |
---|
472 | /* Transmission Control Register */ |
---|
473 | #define UART_TCR 0x18 |
---|
474 | /* Modem Status Register (read only) */ |
---|
475 | #define UART_MSR 0x18 |
---|
476 | /* XOFF1 Register */ |
---|
477 | #define UART_XOFF1 0x18 |
---|
478 | /* Scratch Pad Register (read/write) */ |
---|
479 | #define UART_SPR 0x1C |
---|
480 | /* Trigger Level Register */ |
---|
481 | #define UART_TLR 0x1C |
---|
482 | /* XOFF2 Register */ |
---|
483 | #define UART_XOFF2 0x1C |
---|
484 | /* Mode Definition Register 1 */ |
---|
485 | #define UART_MDR1 0x20 |
---|
486 | /* Mode Definition Register 2 */ |
---|
487 | #define UART_MDR2 0x24 |
---|
488 | /* Transmit Frame Length Register Low (IrDA modes only) */ |
---|
489 | #define UART_TXFLL 0x28 |
---|
490 | /* Status FIFO Line Status Register (IrDA modes only) */ |
---|
491 | #define UART_SFLSR 0x28 |
---|
492 | /* Resume Register (IR-IrDA and IR-CIR modes only) */ |
---|
493 | #define UART_RESUME 0x2C |
---|
494 | /* Transmit Frame Length Register High (IrDA modes only) */ |
---|
495 | #define UART_TXFLH 0x2C |
---|
496 | /* Receive Frame Length Register Low (IrDA modes only) */ |
---|
497 | #define UART_RXFLL 0x30 |
---|
498 | /* Status FIFO Register Low (IrDA modes only) */ |
---|
499 | #define UART_SFREGL 0x30 |
---|
500 | /* Status FIFO Register High (IrDA modes only) */ |
---|
501 | #define UART_SFREGH 0x34 |
---|
502 | /* Receive Frame Length Register High (IrDA modes only) */ |
---|
503 | #define UART_RXFLH 0x34 |
---|
504 | /* BOF Control Register (IrDA modes only_ */ |
---|
505 | #define UART_BLR 0x38 |
---|
506 | /* UART Autobauding Status Register (UART autobauding |
---|
507 | mode only */ |
---|
508 | #define UART_UASR 0x38 |
---|
509 | /* Auxiliary Control Register (IrDA-CIR modes only) */ |
---|
510 | #define UART_ACREG 0x3C |
---|
511 | /* Supplementary Control Register */ |
---|
512 | #define UART_SCR 0x40 |
---|
513 | /* Supplementary Status Register */ |
---|
514 | #define UART_SSR 0x44 |
---|
515 | /* BOF Length Register (IR-IrDA and IR-CIR modes only) */ |
---|
516 | #define UART_EBLR 0x48 |
---|
517 | /* Module Version Register */ |
---|
518 | #define UART_MVR 0x50 |
---|
519 | /* System Configuration Register */ |
---|
520 | #define UART_SYSC 0x54 |
---|
521 | /* System Status Register */ |
---|
522 | #define UART_SYSS 0x58 |
---|
523 | /* Wake-up Enable Register */ |
---|
524 | #define UART_WER 0x5C |
---|
525 | /* Carrier Frequency Prescalar Register */ |
---|
526 | #define UART_CFPS 0x60 |
---|
527 | /* Received FIFO Level Register */ |
---|
528 | #define UART_RXFIFO_LVL 0x64 |
---|
529 | /* Transmit FIFO Level Register */ |
---|
530 | #define UART_TXFIFO_LVL 0x68 |
---|
531 | /* IER2 Register */ |
---|
532 | #define UART_IER2 0x6C |
---|
533 | /* ISR2 Register */ |
---|
534 | #define UART_ISR2 0x70 |
---|
535 | /* FREQ_SEL Register */ |
---|
536 | #define UART_FREQ_SEL 0x74 |
---|
537 | /* Mode Definition Register 3 */ |
---|
538 | #define UART_MDR3 0x80 |
---|
539 | /* TX DMA Threshold Register */ |
---|
540 | #define UART_TX_DMA_THRESHOLD 0x84 |
---|
541 | /*===========================================================================*/ |
---|
542 | |
---|
543 | |
---|
544 | /*===========================================================================*/ |
---|
545 | /* USB */ |
---|
546 | /*===========================================================================*/ |
---|
547 | #define USB_SUBSYS_BASE_ADDR 0x47400000 |
---|
548 | /*---------------------------------------------------------------------------*/ |
---|
549 | /* USB Subsystem Registers offset */ |
---|
550 | #define USBSS_BASE_REG_OFFSET 0x0000 |
---|
551 | #define USBSS_REVREG 0x0000 |
---|
552 | #define USBSS_SYSCONFIG 0x0010 |
---|
553 | #define USBSS_IRQSTATRAW 0x0024 |
---|
554 | #define USBSS_IRQSTAT 0x0028 |
---|
555 | #define USBSS_IRQENABLER 0x002C |
---|
556 | #define USBSS_IRQCLEARR 0x0030 |
---|
557 | #define USBSS_IRQDMATHOLDTX00 0x0100 |
---|
558 | #define USBSS_IRQDMATHOLDTX01 0x0104 |
---|
559 | #define USBSS_IRQDMATHOLDTX02 0x0108 |
---|
560 | #define USBSS_IRQDMATHOLDTX03 0x010C |
---|
561 | #define USBSS_IRQDMATHOLDRX00 0x0110 |
---|
562 | #define USBSS_IRQDMATHOLDRX01 0x0114 |
---|
563 | #define USBSS_IRQDMATHOLDRX02 0x0118 |
---|
564 | #define USBSS_IRQDMATHOLDRX03 0x011C |
---|
565 | #define USBSS_IRQDMATHOLDTX10 0x0120 |
---|
566 | #define USBSS_IRQDMATHOLDTX11 0x0124 |
---|
567 | #define USBSS_IRQDMATHOLDTX12 0x0128 |
---|
568 | #define USBSS_IRQDMATHOLDTX13 0x012C |
---|
569 | #define USBSS_IRQDMATHOLDRX10 0x0130 |
---|
570 | #define USBSS_IRQDMATHOLDRX11 0x0134 |
---|
571 | #define USBSS_IRQDMATHOLDRX12 0x0138 |
---|
572 | #define USBSS_IRQDMATHOLDRX13 0x013C |
---|
573 | #define USBSS_IRQDMAENABLE0 0x0140 |
---|
574 | #define USBSS_IRQDMAENABLE1 0x0144 |
---|
575 | #define USBSS_IRQFRAMETHOLDTX00 0x0200 |
---|
576 | #define USBSS_IRQFRAMETHOLDTX01 0x0204 |
---|
577 | #define USBSS_IRQFRAMETHOLDTX02 0x0208 |
---|
578 | #define USBSS_IRQFRAMETHOLDTX03 0x020C |
---|
579 | #define USBSS_IRQFRAMETHOLDRX00 0x0210 |
---|
580 | #define USBSS_IRQFRAMETHOLDRX01 0x0214 |
---|
581 | #define USBSS_IRQFRAMETHOLDRX02 0x0218 |
---|
582 | #define USBSS_IRQFRAMETHOLDRX03 0x021C |
---|
583 | #define USBSS_IRQFRAMETHOLDTX10 0x0220 |
---|
584 | #define USBSS_IRQFRAMETHOLDTX11 0x0224 |
---|
585 | #define USBSS_IRQFRAMETHOLDTX12 0x0228 |
---|
586 | #define USBSS_IRQFRAMETHOLDTX13 0x022C |
---|
587 | #define USBSS_IRQFRAMETHOLDRX10 0x0230 |
---|
588 | #define USBSS_IRQFRAMETHOLDRX11 0x0234 |
---|
589 | #define USBSS_IRQFRAMETHOLDRX12 0x0238 |
---|
590 | #define USBSS_IRQFRAMETHOLDRX13 0x023C |
---|
591 | #define USBSS_IRQFRAMEENABLE0 0x0240 |
---|
592 | #define USBSS_IRQFRAMEENABLE1 0x0244 |
---|
593 | /*---------------------------------------------------------------------------*/ |
---|
594 | /* USB Controller Registers offset */ |
---|
595 | #define USBCNTLR_USB0_BASE_REG_OFFSET 0x1000 /* USB0 */ |
---|
596 | #define USBCNTLR_USB1_BASE_REG_OFFSET 0x1800 /* USB1 */ |
---|
597 | #define USBCNTLR_REV 0x0000 |
---|
598 | #define USBCNTLR_CTRL 0x0014 |
---|
599 | #define USBCNTLR_STAT 0x0018 |
---|
600 | #define USBCNTLR_IRQMSTAT 0x0020 |
---|
601 | #define USBCNTLR_IRQSTATRAW0 0x0028 |
---|
602 | #define USBCNTLR_IRQSTATRAW1 0x002C |
---|
603 | #define USBCNTLR_IRQSTAT0 0x0030 |
---|
604 | #define USBCNTLR_IRQSTAT1 0x0034 |
---|
605 | #define USBCNTLR_IRQENABLESET0 0x0038 |
---|
606 | #define USBCNTLR_IRQENABLESET1 0x003C |
---|
607 | #define USBCNTLR_IRQENABLECLR0 0x0040 |
---|
608 | #define USBCNTLR_IRQENABLECLR1 0x0044 |
---|
609 | #define USBCNTLR_TXMODE 0x0070 |
---|
610 | #define USBCNTLR_RXMODE 0x0074 |
---|
611 | #define USBCNTLR_GENRNDISEP1 0x0080 |
---|
612 | #define USBCNTLR_GENRNDISEP2 0x0084 |
---|
613 | #define USBCNTLR_GENRNDISEP3 0x0088 |
---|
614 | #define USBCNTLR_GENRNDISEP4 0x008C |
---|
615 | #define USBCNTLR_GENRNDISEP5 0x0090 |
---|
616 | #define USBCNTLR_GENRNDISEP6 0x0094 |
---|
617 | #define USBCNTLR_GENRNDISEP7 0x0098 |
---|
618 | #define USBCNTLR_GENRNDISEP8 0x009C |
---|
619 | #define USBCNTLR_GENRNDISEP9 0x00A0 |
---|
620 | #define USBCNTLR_GENRNDISEP10 0x00A4 |
---|
621 | #define USBCNTLR_GENRNDISEP11 0x00A8 |
---|
622 | #define USBCNTLR_GENRNDISEP12 0x00AC |
---|
623 | #define USBCNTLR_GENRNDISEP13 0x00B0 |
---|
624 | #define USBCNTLR_GENRNDISEP14 0x00B4 |
---|
625 | #define USBCNTLR_GENRNDISEP15 0x00B8 |
---|
626 | #define USBCNTLR_AUTOREQ 0x00D0 |
---|
627 | #define USBCNTLR_SRPFIXTIME 0x00D4 |
---|
628 | #define USBCNTLR_TDOWN 0x00D8 |
---|
629 | #define USBCNTLR_UTMI 0x00E0 |
---|
630 | #define USBCNTLR_MGCUTMILB 0x00E4 |
---|
631 | #define USBCNTLR_MODE 0x00E8 |
---|
632 | /*---------------------------------------------------------------------------*/ |
---|
633 | /* USB PHY Registers offset */ |
---|
634 | #define USBPHY_USB0_BASE_REG_OFFSET 0x1300 /* USB0 */ |
---|
635 | #define USBPHY_USB1_BASE_REG_OFFSET 0x1B00 /* USB1 */ |
---|
636 | #define USBPHY_TERMINATION_CNTL 0x0000 |
---|
637 | #define USBPHY_RX_CALIB 0x0004 |
---|
638 | #define USBPHY_DLLHS_2 0x0008 |
---|
639 | #define USBPHY_RX_TEST_2 0x000C |
---|
640 | #define USBPHY_CHRG_DET 0x0014 |
---|
641 | #define USBPHY_PWR_CNTL 0x0018 |
---|
642 | #define USBPHY_UTMI_INTERFACE_CNTL_1 0x001C |
---|
643 | #define USBPHY_UTMI_INTERFACE_CNTL_2 0x0020 |
---|
644 | #define USBPHY_BIST 0x0024 |
---|
645 | #define USBPHY_BIST_CRC 0x0028 |
---|
646 | #define USBPHY_CDR_BIST2 0x002C |
---|
647 | #define USBPHY_GPIO 0x0030 |
---|
648 | #define USBPHY_DLLHS 0x0034 |
---|
649 | #define USBPHY_USB2PHYCM_CONFIG 0x003C |
---|
650 | #define USBPHY_AD_INTERFACE_REG1 0x0044 |
---|
651 | #define USBPHY_AD_INTERFACE_REG2 0x0048 |
---|
652 | #define USBPHY_AD_INTERFACE_REG3 0x004C |
---|
653 | #define USBPHY_ANA_CONFIG2 0x0054 |
---|
654 | /*---------------------------------------------------------------------------*/ |
---|
655 | /* USB Core Registers offset */ |
---|
656 | #define USBCORE_USB0_BASE_REG_OFFSET 0x1400 |
---|
657 | #define USBCORE_USB1_BASE_REG_OFFSET 0x1C00 |
---|
658 | /*---------------------------------------------------------------------------*/ |
---|
659 | /* USB CPPI DMA Controller Registers offset */ |
---|
660 | #define USBCPPIDMACNTLR_BASE_REG_OFFSET 0x2000 |
---|
661 | #define USBCPPIDMACNTLR_DMAREVID 0x0000 |
---|
662 | #define USBCPPIDMACNTLR_TDFDQ 0x0004 |
---|
663 | #define USBCPPIDMACNTLR_DMAEMU 0x0008 |
---|
664 | #define USBCPPIDMACNTLR_TXGCR0 0x0800 |
---|
665 | #define USBCPPIDMACNTLR_RXGCR0 0x0808 |
---|
666 | #define USBCPPIDMACNTLR_RXHPCRA0 0x080C |
---|
667 | #define USBCPPIDMACNTLR_RXHPCRB0 0x0810 |
---|
668 | #define USBCPPIDMACNTLR_TXGCR1 0x0820 |
---|
669 | #define USBCPPIDMACNTLR_RXGCR1 0x0828 |
---|
670 | #define USBCPPIDMACNTLR_RXHPCRA1 0x082C |
---|
671 | #define USBCPPIDMACNTLR_RXHPCRB1 0x0830 |
---|
672 | #define USBCPPIDMACNTLR_TXGCR2 0x0840 |
---|
673 | #define USBCPPIDMACNTLR_RXGCR2 0x0848 |
---|
674 | #define USBCPPIDMACNTLR_RXHPCRA2 0x084C |
---|
675 | #define USBCPPIDMACNTLR_RXHPCRB2 0x0850 |
---|
676 | #define USBCPPIDMACNTLR_TXGCR3 0x0860 |
---|
677 | #define USBCPPIDMACNTLR_RXGCR3 0x0868 |
---|
678 | #define USBCPPIDMACNTLR_RXHPCRA3 0x086C |
---|
679 | #define USBCPPIDMACNTLR_RXHPCRB3 0x0870 |
---|
680 | #define USBCPPIDMACNTLR_TXGCR4 0x0880 |
---|
681 | #define USBCPPIDMACNTLR_RXGCR4 0x0888 |
---|
682 | #define USBCPPIDMACNTLR_RXHPCRA4 0x088C |
---|
683 | #define USBCPPIDMACNTLR_RXHPCRB4 0x0890 |
---|
684 | #define USBCPPIDMACNTLR_TXGCR5 0x08A0 |
---|
685 | #define USBCPPIDMACNTLR_RXGCR5 0x08A8 |
---|
686 | #define USBCPPIDMACNTLR_RXHPCRA5 0x08AC |
---|
687 | #define USBCPPIDMACNTLR_RXHPCRB5 0x08B0 |
---|
688 | #define USBCPPIDMACNTLR_TXGCR6 0x08C0 |
---|
689 | #define USBCPPIDMACNTLR_RXGCR6 0x08C8 |
---|
690 | #define USBCPPIDMACNTLR_RXHPCRA6 0x08CC |
---|
691 | #define USBCPPIDMACNTLR_RXHPCRB6 0x08D0 |
---|
692 | #define USBCPPIDMACNTLR_TXGCR7 0x08E0 |
---|
693 | #define USBCPPIDMACNTLR_RXGCR7 0x08E8 |
---|
694 | #define USBCPPIDMACNTLR_RXHPCRA7 0x08EC |
---|
695 | #define USBCPPIDMACNTLR_RXHPCRB7 0x08F0 |
---|
696 | #define USBCPPIDMACNTLR_TXGCR8 0x0900 |
---|
697 | #define USBCPPIDMACNTLR_RXGCR8 0x0908 |
---|
698 | #define USBCPPIDMACNTLR_RXHPCRA8 0x090C |
---|
699 | #define USBCPPIDMACNTLR_RXHPCRB8 0x0910 |
---|
700 | #define USBCPPIDMACNTLR_TXGCR9 0x0920 |
---|
701 | #define USBCPPIDMACNTLR_RXGCR9 0x0928 |
---|
702 | #define USBCPPIDMACNTLR_RXHPCRA9 0x092C |
---|
703 | #define USBCPPIDMACNTLR_RXHPCRB9 0x0930 |
---|
704 | #define USBCPPIDMACNTLR_TXGCR10 0x0940 |
---|
705 | #define USBCPPIDMACNTLR_RXGCR10 0x0948 |
---|
706 | #define USBCPPIDMACNTLR_RXHPCRA10 0x094C |
---|
707 | #define USBCPPIDMACNTLR_RXHPCRB10 0x0950 |
---|
708 | #define USBCPPIDMACNTLR_TXGCR11 0x0960 |
---|
709 | #define USBCPPIDMACNTLR_RXGCR11 0x0968 |
---|
710 | #define USBCPPIDMACNTLR_RXHPCRA11 0x096C |
---|
711 | #define USBCPPIDMACNTLR_RXHPCRB11 0x0970 |
---|
712 | #define USBCPPIDMACNTLR_TXGCR12 0x0980 |
---|
713 | #define USBCPPIDMACNTLR_RXGCR12 0x0988 |
---|
714 | #define USBCPPIDMACNTLR_RXHPCRA12 0x098C |
---|
715 | #define USBCPPIDMACNTLR_RXHPCRB12 0x0990 |
---|
716 | #define USBCPPIDMACNTLR_TXGCR13 0x09A0 |
---|
717 | #define USBCPPIDMACNTLR_RXGCR13 0x09A8 |
---|
718 | #define USBCPPIDMACNTLR_RXHPCRA13 0x09AC |
---|
719 | #define USBCPPIDMACNTLR_RXHPCRB13 0x09B0 |
---|
720 | #define USBCPPIDMACNTLR_TXGCR14 0x09C0 |
---|
721 | #define USBCPPIDMACNTLR_RXGCR14 0x09C8 |
---|
722 | #define USBCPPIDMACNTLR_RXHPCRA14 0x09CC |
---|
723 | #define USBCPPIDMACNTLR_RXHPCRB14 0x09D0 |
---|
724 | #define USBCPPIDMACNTLR_TXGCR15 0x09E0 |
---|
725 | #define USBCPPIDMACNTLR_RXGCR15 0x09E8 |
---|
726 | #define USBCPPIDMACNTLR_RXHPCRA15 0x09EC |
---|
727 | #define USBCPPIDMACNTLR_RXHPCRB15 0x09F0 |
---|
728 | #define USBCPPIDMACNTLR_TXGCR16 0x0A00 |
---|
729 | #define USBCPPIDMACNTLR_RXGCR16 0x0A08 |
---|
730 | #define USBCPPIDMACNTLR_RXHPCRA16 0x0A0C |
---|
731 | #define USBCPPIDMACNTLR_RXHPCRB16 0x0A10 |
---|
732 | #define USBCPPIDMACNTLR_TXGCR17 0x0A20 |
---|
733 | #define USBCPPIDMACNTLR_RXGCR17 0x0A28 |
---|
734 | #define USBCPPIDMACNTLR_RXHPCRA17 0x0A2C |
---|
735 | #define USBCPPIDMACNTLR_RXHPCRB17 0x0A30 |
---|
736 | #define USBCPPIDMACNTLR_TXGCR18 0x0A40 |
---|
737 | #define USBCPPIDMACNTLR_RXGCR18 0x0A48 |
---|
738 | #define USBCPPIDMACNTLR_RXHPCRA18 0x0A4C |
---|
739 | #define USBCPPIDMACNTLR_RXHPCRB18 0x0A50 |
---|
740 | #define USBCPPIDMACNTLR_TXGCR19 0x0A60 |
---|
741 | #define USBCPPIDMACNTLR_RXGCR19 0x0A68 |
---|
742 | #define USBCPPIDMACNTLR_RXHPCRA19 0x0A6C |
---|
743 | #define USBCPPIDMACNTLR_RXHPCRB19 0x0A70 |
---|
744 | #define USBCPPIDMACNTLR_TXGCR20 0x0A80 |
---|
745 | #define USBCPPIDMACNTLR_RXGCR20 0x0A88 |
---|
746 | #define USBCPPIDMACNTLR_RXHPCRA20 0x0A8C |
---|
747 | #define USBCPPIDMACNTLR_RXHPCRB20 0x0A90 |
---|
748 | #define USBCPPIDMACNTLR_TXGCR21 0x0AA0 |
---|
749 | #define USBCPPIDMACNTLR_RXGCR21 0x0AA8 |
---|
750 | #define USBCPPIDMACNTLR_RXHPCRA21 0x0AAC |
---|
751 | #define USBCPPIDMACNTLR_RXHPCRB21 0x0AB0 |
---|
752 | #define USBCPPIDMACNTLR_TXGCR22 0x0AC0 |
---|
753 | #define USBCPPIDMACNTLR_RXGCR22 0x0AC8 |
---|
754 | #define USBCPPIDMACNTLR_RXHPCRA22 0x0ACC |
---|
755 | #define USBCPPIDMACNTLR_RXHPCRB22 0x0AD0 |
---|
756 | #define USBCPPIDMACNTLR_TXGCR23 0x0AE0 |
---|
757 | #define USBCPPIDMACNTLR_RXGCR23 0x0AE8 |
---|
758 | #define USBCPPIDMACNTLR_RXHPCRA23 0x0AEC |
---|
759 | #define USBCPPIDMACNTLR_RXHPCRB23 0x0AF0 |
---|
760 | #define USBCPPIDMACNTLR_TXGCR24 0x0B00 |
---|
761 | #define USBCPPIDMACNTLR_RXGCR24 0x0B08 |
---|
762 | #define USBCPPIDMACNTLR_RXHPCRA24 0x0B0C |
---|
763 | #define USBCPPIDMACNTLR_RXHPCRB24 0x0B10 |
---|
764 | #define USBCPPIDMACNTLR_TXGCR25 0x0B20 |
---|
765 | #define USBCPPIDMACNTLR_RXGCR25 0x0B28 |
---|
766 | #define USBCPPIDMACNTLR_RXHPCRA25 0x0B2C |
---|
767 | #define USBCPPIDMACNTLR_RXHPCRB25 0x0B30 |
---|
768 | #define USBCPPIDMACNTLR_TXGCR26 0x0B40 |
---|
769 | #define USBCPPIDMACNTLR_RXGCR26 0x0B48 |
---|
770 | #define USBCPPIDMACNTLR_RXHPCRA26 0x0B4C |
---|
771 | #define USBCPPIDMACNTLR_RXHPCRB26 0x0B50 |
---|
772 | #define USBCPPIDMACNTLR_TXGCR27 0x0B60 |
---|
773 | #define USBCPPIDMACNTLR_RXGCR27 0x0B68 |
---|
774 | #define USBCPPIDMACNTLR_RXHPCRA27 0x0B6C |
---|
775 | #define USBCPPIDMACNTLR_RXHPCRB27 0x0B70 |
---|
776 | #define USBCPPIDMACNTLR_TXGCR28 0x0B80 |
---|
777 | #define USBCPPIDMACNTLR_RXGCR28 0x0B88 |
---|
778 | #define USBCPPIDMACNTLR_RXHPCRA28 0x0B8C |
---|
779 | #define USBCPPIDMACNTLR_RXHPCRB28 0x0B90 |
---|
780 | #define USBCPPIDMACNTLR_TXGCR29 0x0BA0 |
---|
781 | #define USBCPPIDMACNTLR_RXGCR29 0x0BA8 |
---|
782 | #define USBCPPIDMACNTLR_RXHPCRA29 0x0BAC |
---|
783 | #define USBCPPIDMACNTLR_RXHPCRB29 0x0BB0 |
---|
784 | /*---------------------------------------------------------------------------*/ |
---|
785 | /* USB CPPI DMA Scheduler Registers offset */ |
---|
786 | #define USBCPPIDMASCHED_BASE_REG_OFFSET 0x3000 |
---|
787 | #define USBCPPIDMASCHED_CNTL 0x0000 |
---|
788 | /*---------------------------------------------------------------------------*/ |
---|
789 | /* USB Queue Manager Registers offset */ |
---|
790 | #define USBQUEUEMNGER_BASEREG_OFFSET 0x4000 |
---|
791 | #define USBQUEUEMNGER_QMGRREVID 0x0000 |
---|
792 | #define USBQUEUEMNGER_QMGRRST 0x0008 |
---|
793 | #define USBQUEUEMNGER_FDNSCO 0x0020 |
---|
794 | #define USBQUEUEMNGER_FDNSC1 0x0024 |
---|
795 | #define USBQUEUEMNGER_FDNSC2 0x0028 |
---|
796 | #define USBQUEUEMNGER_FDNSC3 0x002C |
---|
797 | #define USBQUEUEMNGER_FDNSC4 0x0030 |
---|
798 | #define USBQUEUEMNGER_FDNSC5 0x0034 |
---|
799 | #define USBQUEUEMNGER_FDNSC6 0x0038 |
---|
800 | #define USBQUEUEMNGER_FDNSC7 0x003C |
---|
801 | #define USBQUEUEMNGER_LRAM0BASE 0x0080 |
---|
802 | #define USBQUEUEMNGER_LRAM0SIZE 0x0084 |
---|
803 | #define USBQUEUEMNGER_LRAM1BASE 0x0088 |
---|
804 | #define USBQUEUEMNGER_PEND0 0x0090 |
---|
805 | #define USBQUEUEMNGER_PEND1 0x0094 |
---|
806 | #define USBQUEUEMNGER_PEND2 0x0098 |
---|
807 | #define USBQUEUEMNGER_PEND3 0x009C |
---|
808 | #define USBQUEUEMNGER_PEND4 0x00A0 |
---|
809 | #define USBQUEUEMNGER_QMEMRBASE0 0x1000 |
---|
810 | #define USBQUEUEMNGER_QMEMCNTL0 0x1004 |
---|
811 | #define USBQUEUEMNGER_QMEMRBASE1 0x1010 |
---|
812 | #define USBQUEUEMNGER_QMEMCNTL1 0x1014 |
---|
813 | #define USBQUEUEMNGER_QMEMRBASE2 0x1020 |
---|
814 | #define USBQUEUEMNGER_QMEMCNTL2 0x1024 |
---|
815 | #define USBQUEUEMNGER_QMEMRBASE3 0x1030 |
---|
816 | #define USBQUEUEMNGER_QMEMCNTL3 0x1034 |
---|
817 | #define USBQUEUEMNGER_QMEMRBASE4 0x1040 |
---|
818 | #define USBQUEUEMNGER_QMEMCNTL4 0x1044 |
---|
819 | #define USBQUEUEMNGER_QMEMRBASE5 0x1050 |
---|
820 | #define USBQUEUEMNGER_QMEMCNTL5 0x1054 |
---|
821 | #define USBQUEUEMNGER_QMEMRBASE6 0x1060 |
---|
822 | #define USBQUEUEMNGER_QMEMCNTL6 0x1064 |
---|
823 | #define USBQUEUEMNGER_QMEMRBASE7 0x1070 |
---|
824 | #define USBQUEUEMNGER_QMEMCNTL7 0x1074 |
---|
825 | /*===========================================================================*/ |
---|
826 | |
---|
827 | |
---|
828 | /*===========================================================================*/ |
---|
829 | /* SPI */ |
---|
830 | /*===========================================================================*/ |
---|
831 | /* Revision Register */ |
---|
832 | #define MCSPI_REVISION 0x0000 |
---|
833 | /* System Configuration Register */ |
---|
834 | #define MCSPI_SYSCONFIG 0x0110 |
---|
835 | /* System Status Register */ |
---|
836 | #define MCSPI_SYSSTATUS 0x0114 |
---|
837 | /* Interrupt Status Register offset */ |
---|
838 | #define MCSPI_IRQSTATUS 0x0118 |
---|
839 | /*---------------------------------------------------------------------------*/ |
---|
840 | /* Interrupt Status Register bit defines */ |
---|
841 | #define MCSPI_IRQSTATUS_RX3_FULL BIT14 |
---|
842 | #define MCSPI_IRQSTATUS_TX3_UNDERFLOW BIT13 |
---|
843 | #define MCSPI_IRQSTATUS_TX3_EMPTY BIT12 |
---|
844 | #define MCSPI_IRQSTATUS_RX2_FULL BIT10 |
---|
845 | #define MCSPI_IRQSTATUS_TX2_UNDERFLOW BIT9 |
---|
846 | #define MCSPI_IRQSTATUS_TX2_EMPTY BIT8 |
---|
847 | #define MCSPI_IRQSTATUS_RX1_FULL BIT6 |
---|
848 | #define MCSPI_IRQSTATUS_TX1_UNDERFLOW BIT5 |
---|
849 | #define MCSPI_IRQSTATUS_TX1_EMPTY BIT4 |
---|
850 | #define MCSPI_IRQSTATUS_RX0_OVERFLOW BIT3 |
---|
851 | #define MCSPI_IRQSTATUS_RX0_FULL BIT2 |
---|
852 | #define MCSPI_IRQSTATUS_TX0_UNDERFLOW BIT1 |
---|
853 | #define MCSPI_IRQSTATUS_TX0_EMPTY BIT0 |
---|
854 | /* Interrupt Enable Register offset */ |
---|
855 | #define MCSPI_IRQENABLE 0x011C |
---|
856 | /* System Register offset */ |
---|
857 | #define MCSPI_SYST 0x0124 |
---|
858 | /* Module Control Register offset */ |
---|
859 | #define MCSPI_MODULCTRL 0x0128 |
---|
860 | /*---------------------------------------------------------------------------*/ |
---|
861 | /* Configuration Registers offset */ |
---|
862 | |
---|
863 | /* Channel 0 Configuration Register offset */ |
---|
864 | #define MCSPI_CH0CONF 0x012C |
---|
865 | /* Channel 1 Configuration Register offset */ |
---|
866 | #define MCSPI_CH1CONF 0x0140 |
---|
867 | /* Channel 2 Configuration Register offset */ |
---|
868 | #define MCSPI_CH2CONF 0x0154 |
---|
869 | /* Channel 3 Configuration Register offset */ |
---|
870 | #define MCSPI_CH3CONF 0x0168 |
---|
871 | |
---|
872 | |
---|
873 | /* Configuration Register bit defines */ |
---|
874 | |
---|
875 | /* 1 = One clock cycle granularity */ |
---|
876 | #define MCSPI_CHXCONF_CLKG BIT29 |
---|
877 | /* 1 = FIFO buffer is used to Receive data */ |
---|
878 | #define MCSPI_CHXCONF_FFER BIT28 |
---|
879 | /* 1 = FIFO buffer is used to Transmit data */ |
---|
880 | #define MCSPI_CHXCONF_FFEW BIT27 |
---|
881 | /* 0.5 clock cycles between CS toggling and first (or last) edge |
---|
882 | of SPI clock */ |
---|
883 | #define MCSPI_CHXCONF_TCS_0_5 (0x00 << 25) |
---|
884 | /* 1.5 clock cycles between CS toggling and first (or last) edge |
---|
885 | of SPI clock */ |
---|
886 | #define MCSPI_CHXCONF_TCS_1_5 (0x01 << 25) |
---|
887 | /* 2.5 clock cycles between CS toggling and first (or last) edge |
---|
888 | of SPI clock */ |
---|
889 | #define MCSPI_CHXCONF_TCS_2_5 (0x02 << 25) |
---|
890 | /* 3.5 clock cycles between CS toggling and first (or last) edge |
---|
891 | of SPI clock */ |
---|
892 | #define MCSPI_CHXCONF_TCS_3_5 (0x03 << 25) |
---|
893 | /* 1 = Start bit polarity is held to 1 during SPI transfer */ |
---|
894 | #define MCSPI_CHXCONF_SBPOL BIT24 |
---|
895 | /* 1 = Start bit added before SPI transfer |
---|
896 | 0 = default length specified by WL */ |
---|
897 | #define MCSPI_CHXCONF_SBE BIT23 |
---|
898 | /* Slave select detection enabled on CS0 */ |
---|
899 | #define MCSPI_CHXCONF_SPIENSLV_0 (0x00 << 21) |
---|
900 | /* Slave select detection enabled on CS1 */ |
---|
901 | #define MCSPI_CHXCONF_SPIENSLV_1 (0x01 << 21) |
---|
902 | /* Slave select detection enabled on CS2 */ |
---|
903 | #define MCSPI_CHXCONF_SPIENSLV_2 (0x02 << 21) |
---|
904 | /* Slave select detection enabled on CS3 */ |
---|
905 | #define MCSPI_CHXCONF_SPIENSLV_3 (0x03 << 21) |
---|
906 | /* 1 = CSx high when EPOL is 0 and low whel EPOL is 1 */ |
---|
907 | #define MCSPI_CHXCONF_FORCE BIT20 |
---|
908 | /* Turbo is activated */ |
---|
909 | #define MCSPI_CHXCONF_TURBO BIT19 |
---|
910 | /* 1 = spim_simo selected for reception |
---|
911 | 0 = spim_somi selected for reception */ |
---|
912 | #define MCSPI_CHXCONF_IS BIT18 |
---|
913 | /* 1 = no transmission on spim_simo |
---|
914 | 0 = spim_simo selected for transmission */ |
---|
915 | #define MCSPI_CHXCONF_DPE1 BIT17 |
---|
916 | /* 1 = no transmission on spim_somi |
---|
917 | 0 = spim_somi selected for transmission */ |
---|
918 | #define MCSPI_CHXCONF_DPE0 BIT16 |
---|
919 | /* 1 = DMA read request enabled */ |
---|
920 | #define MCSPI_CHXCONF_DMAR BIT15 |
---|
921 | /* 1 = DMA write request enabled */ |
---|
922 | #define MCSPI_CHXCONF_DMAW BIT14 |
---|
923 | /* Transmit and receive mode */ |
---|
924 | #define MCSPI_CHXCONF_TRM_TR (0x00 << 12) |
---|
925 | /* Receive-only mode */ |
---|
926 | #define MCSPI_CHXCONF_TRM_RO (0x01 << 12) |
---|
927 | /* Transmit-only mode */ |
---|
928 | #define MCSPI_CHXCONF_TRM_TO (0x02 << 12) |
---|
929 | /* SPI word length, 0x7 = 8-bit */ |
---|
930 | #define MCSPI_CHXCONF_WL(_x_) ((_x_ & 0x1f) << 7) |
---|
931 | /* 1 = SPIM_CSx is low during active state, |
---|
932 | 0 = high during active state */ |
---|
933 | #define MCSPI_CHxCONF_EPOL BIT6 |
---|
934 | /* Frequency divider for spim_clk */ |
---|
935 | #define MCSPI_CHXCONF_CLKD(_x_) ((_x_ & 0xf) << 2) |
---|
936 | /* 1 = spim_clk is low during active state |
---|
937 | 0 = high during active state */ |
---|
938 | #define MCSPI_CHXCONF_POL BIT1 |
---|
939 | /* 1 = data latched on even-numbered edges |
---|
940 | 0 = data latched on odd-numbered edges */ |
---|
941 | #define MCSPI_CHXCONF_PHA BIT0 |
---|
942 | /*---------------------------------------------------------------------------*/ |
---|
943 | /* Status Registers offset */ |
---|
944 | #define MCSPI_CH0STAT 0x0130 // Channel 0 Status Register |
---|
945 | #define MCSPI_CH1STAT 0x0144 // Channel 1 Status Register |
---|
946 | #define MCSPI_CH2STAT 0x0158 // Channel 2 Status Register |
---|
947 | #define MCSPI_CH3STAT 0x016C // Channel 3 Status Register |
---|
948 | /* Status Register bit defines */ |
---|
949 | #define MCSPI_CHXSAT_RXF_FULL BIT6 |
---|
950 | #define MCSPI_CHXSAT_RXF_EMPTY BIT5 |
---|
951 | #define MCSPI_CHXSAT_TXF_FULL BIT4 |
---|
952 | #define MCSPI_CHXSAT_TXF_EMPTY BIT3 |
---|
953 | #define MCSPI_CHXSAT_EOT BIT2 |
---|
954 | #define MCSPI_CHXSAT_TX0_EMPTY BIT1 |
---|
955 | #define MCSPI_CHXSAT_RX0_FULL BIT0 |
---|
956 | /*---------------------------------------------------------------------------*/ |
---|
957 | /* Control Registers offset */ |
---|
958 | #define MCSPI_CH0CTRL 0x0134 // Channel 0 Control Register offset |
---|
959 | #define MCSPI_CH1CTRL 0x0148 // Channel 1 Control Register offset |
---|
960 | #define MCSPI_CH2CTRL 0x015C // Channel 2 Control Register offset |
---|
961 | #define MCSPI_CH3CTRL 0x0170 // Channel 3 Control Register offset |
---|
962 | /*---------------------------------------------------------------------------*/ |
---|
963 | /* FIFO Buffer Registers offset */ |
---|
964 | |
---|
965 | /* Channel 0 FIFO Transmit Buffer Register offset */ |
---|
966 | #define MCSPI_TX0 0x0138 |
---|
967 | /* Channel 0 FIFO Receive Buffer Register offset */ |
---|
968 | #define MCSPI_RX0 0x013C |
---|
969 | /* Channel 1 FIFO Transmit Buffer Register offset */ |
---|
970 | #define MCSPI_TX1 0x014C |
---|
971 | /* Channel 1 FIFO Receive Buffer Register offset */ |
---|
972 | #define MCSPI_RX1 0x0150 |
---|
973 | /* Channel 2 FIFO Transmit Buffer Register offset */ |
---|
974 | #define MCSPI_TX2 0x0160 |
---|
975 | /* Channel 2 FIFO Receive Buffer Register offset */ |
---|
976 | #define MCSPI_RX2 0x0164 |
---|
977 | /* Channel 3 FIFO Transmit Buffer Register offset */ |
---|
978 | #define MCSPI_TX3 0x0174 |
---|
979 | /* Channel 3 FIFO Receive Buffer Register offset */ |
---|
980 | #define MCSPI_RX3 0x0178 |
---|
981 | /*---------------------------------------------------------------------------*/ |
---|
982 | /* Transfer Levels Register */ |
---|
983 | #define MCSPI_XFERLEVEL 0x017C |
---|
984 | /* DMA Address Aligned FIFO Transmitter Register */ |
---|
985 | #define MCSPI_DAFTX 0x0180 |
---|
986 | /* DMA Address Aligned FIFO Receiver Register */ |
---|
987 | #define MCSPI_DAFRX 0x01A0 |
---|
988 | /*===========================================================================*/ |
---|
989 | |
---|
990 | |
---|
991 | /*===========================================================================*/ |
---|
992 | /* General Purpose I/O */ |
---|
993 | /*===========================================================================*/ |
---|
994 | /* GPIO0 Registers */ |
---|
995 | #define GPIO0_BASE (L4_WKUP_BASE + 0x00207000) |
---|
996 | #define GPIO0_REG(_x_) *(vulong *)(GPIO0_BASE + _x_) |
---|
997 | /* GPIO1 Registers */ |
---|
998 | #define GPIO1_BASE (L4_PER_BASE + 0x0004C000) |
---|
999 | #define GPIO1_REG(_x_) *(vulong *)(GPIO1_BASE + _x_) |
---|
1000 | /* GPIO2 Registers */ |
---|
1001 | #define GPIO2_BASE (L4_PER_BASE + 0x001AC000) |
---|
1002 | #define GPIO2_REG(_x_) *(vulong *)(GPIO2_BASE + _x_) |
---|
1003 | /* GPIO3 Registers */ |
---|
1004 | #define GPIO3_BASE (L4_PER_BASE + 0x001AE000) |
---|
1005 | #define GPIO3_REG(_x_) *(vulong *)(GPIO3_BASE + _x_) |
---|
1006 | /*---------------------------------------------------------------------------*/ |
---|
1007 | /* GPIOx Register offsets */ |
---|
1008 | #define GPIOX_REVISION 0x0000 |
---|
1009 | #define GPIOX_SYSCONFIG 0x0010 |
---|
1010 | #define GPIOX_EOI 0x0020 |
---|
1011 | #define GPIOX_IRQSTATUS_RAW_0 0x0024 |
---|
1012 | #define GPIOX_IRQSTATUS_RAW_1 0x0028 |
---|
1013 | #define GPIOX_IRQSTATUS_0 0x002C |
---|
1014 | #define GPIOX_IRQSTATUS_1 0x0030 |
---|
1015 | #define GPIOX_IRQSTATUS_SET_0 0x0034 |
---|
1016 | #define GPIOX_IRQSTATUS_SET_1 0x0038 |
---|
1017 | #define GPIOX_IRQSTATUS_CLR_0 0x003C |
---|
1018 | #define GPIOX_IRQSTATUS_CLR_1 0x0040 |
---|
1019 | #define GPIOX_IRQWAKEN_0 0x0044 |
---|
1020 | #define GPIOX_IRQWAKEN_1 0x0048 |
---|
1021 | #define GPIOX_SYSSTATUS 0x0114 |
---|
1022 | #define GPIOX_CTRL 0x0130 |
---|
1023 | #define GPIOX_OE 0x0134 |
---|
1024 | #define GPIOX_DATAIN 0x0138 |
---|
1025 | #define GPIOX_DATAOUT 0x013C |
---|
1026 | #define GPIOX_LEVELDETECT0 0x0140 |
---|
1027 | #define GPIOX_LEVELDETECT1 0x0144 |
---|
1028 | #define GPIOX_RISINGDETECT 0x0148 |
---|
1029 | #define GPIOX_FALLINGDETECT 0x014C |
---|
1030 | #define GPIOX_DEBOUNCEENABLE 0x0150 |
---|
1031 | #define GPIOX_DEBOUNCINGTIME 0x0154 |
---|
1032 | #define GPIOX_CLEARDATAOUT 0x0190 |
---|
1033 | #define GPIOX_SETDATAOUT 0x0194 |
---|
1034 | /*===========================================================================*/ |
---|
1035 | |
---|
1036 | |
---|
1037 | /*===========================================================================*/ |
---|
1038 | /* Watchdog Timer */ |
---|
1039 | /*===========================================================================*/ |
---|
1040 | /* Watchdog Timer Registers offset*/ |
---|
1041 | #define WDT1_BASE (L4_WKUP_BASE + 0x00235000) |
---|
1042 | #define WDT1_REG(_x_) *(vulong *)(WDT1_BASE + _x_) |
---|
1043 | /*---------------------------------------------------------------------------*/ |
---|
1044 | /* WatchDog Timer Register offsets */ |
---|
1045 | |
---|
1046 | /* Watchdow Identification Register */ |
---|
1047 | #define WDT1_WIDR 0x00 |
---|
1048 | /* Watchdog System Control Register */ |
---|
1049 | #define WDT1_WDSC 0x10 |
---|
1050 | /* Watchdog Status Register */ |
---|
1051 | #define WDT1_WDST 0x14 |
---|
1052 | /* Watchdog Interrupt Status Register */ |
---|
1053 | #define WDT1_WISR 0x18 |
---|
1054 | /* Watchdog Interrupt Enable Register */ |
---|
1055 | #define WDT1_WIER 0x1C |
---|
1056 | /* Watchdog Control Register */ |
---|
1057 | #define WDT1_WCLR 0x24 |
---|
1058 | /* Watchdog Counter Register */ |
---|
1059 | #define WDT1_WCRR 0x28 |
---|
1060 | /* Watchdog Load Register */ |
---|
1061 | #define WDT1_WLDR 0x2C |
---|
1062 | /* Watchdog Trigger Register */ |
---|
1063 | #define WDT1_WTGR 0x30 |
---|
1064 | /* Watchdog Write Posting Bits Register */ |
---|
1065 | #define WDT1_WWPS 0x34 |
---|
1066 | /* Watchdog Delay Configuration Register */ |
---|
1067 | #define WDT1_WDLY 0x44 |
---|
1068 | /* Watchdog Start/Stop Register */ |
---|
1069 | #define WDT1_WSPR 0x48 |
---|
1070 | /* Watchdog Raw Interrupt Status Register */ |
---|
1071 | #define WDT1_WIRQSTATRAW 0x54 |
---|
1072 | /* Watchdog Interrupt Status Register */ |
---|
1073 | #define WDT1_WIRQSTAT 0x58 |
---|
1074 | /* Watchdog Interrupt Enable Set Register */ |
---|
1075 | #define WDT1_WIRQENSET 0x5C |
---|
1076 | /* Watchdog Interrupt Enable Clear Register */ |
---|
1077 | #define WDT1_WIRQENCLR 0x60 |
---|
1078 | /*===========================================================================*/ |
---|
1079 | |
---|
1080 | |
---|
1081 | /*===========================================================================*/ |
---|
1082 | /* MMC */ |
---|
1083 | /*===========================================================================*/ |
---|
1084 | /* MMC Registers offset */ |
---|
1085 | #define MMC1_BASE (L4_PER_BASE + 0x001D8000) |
---|
1086 | #define MMC1_REG(_x_) *(vulong *)(MMC1_BASE + _x_) |
---|
1087 | /*---------------------------------------------------------------------------*/ |
---|
1088 | /* MMC Register offsets */ |
---|
1089 | |
---|
1090 | /* System Configuration */ |
---|
1091 | #define SD_SYSCONFIG 0x0110 |
---|
1092 | /* System Status */ |
---|
1093 | #define SD_SYSSTATUS 0x0114 |
---|
1094 | /* Card Status Response Error */ |
---|
1095 | #define SD_CSRE 0x0124 |
---|
1096 | /* System Test */ |
---|
1097 | #define SD_SYSTEST 0x0128 |
---|
1098 | /* Configuration */ |
---|
1099 | #define SD_CON 0x012C |
---|
1100 | /* Power Counter */ |
---|
1101 | #define SD_PWCNT 0x0130 |
---|
1102 | /* SDMA System Address */ |
---|
1103 | #define SD_SDMASA 0x0200 |
---|
1104 | /* Transfer Length Configuration */ |
---|
1105 | #define SD_BLK 0x0204 |
---|
1106 | /* Command Argument */ |
---|
1107 | #define SD_ARG 0x0208 |
---|
1108 | /* Command and Transfer Mode */ |
---|
1109 | #define SD_CMD 0x020C |
---|
1110 | /* Command Response 0 and 1 */ |
---|
1111 | #define SD_RSP10 0x0210 |
---|
1112 | /* Command Response 2 and 3 */ |
---|
1113 | #define SD_RSP32 0x0214 |
---|
1114 | /* Command Response 4 and 5 */ |
---|
1115 | #define SD_RSP54 0x0218 |
---|
1116 | /* Command Response 6 and 7 */ |
---|
1117 | #define SD_RSP76 0x021C |
---|
1118 | /* Data */ |
---|
1119 | #define SD_DATA 0x0220 |
---|
1120 | /* Present State */ |
---|
1121 | #define SD_PSTATE 0x0224 |
---|
1122 | /* Host Control */ |
---|
1123 | #define SD_HCTL 0x0228 |
---|
1124 | /* SD System Control */ |
---|
1125 | #define SD_SYSCTL 0x022C |
---|
1126 | /* SD Interrupt Status */ |
---|
1127 | #define SD_STAT 0x0230 |
---|
1128 | /* SD Interrupt Enable */ |
---|
1129 | #define SD_IE 0x0234 |
---|
1130 | /* SD Interrupt Enable Set */ |
---|
1131 | #define SD_ISE 0x0238 |
---|
1132 | /* Auto CMD12 Error Status */ |
---|
1133 | #define SD_AC12 0x023C |
---|
1134 | /* Capabilities */ |
---|
1135 | #define SD_CAPA 0x0240 |
---|
1136 | /* Maximum Current Capabilities */ |
---|
1137 | #define SD_CUR_CAPA 0x0148 |
---|
1138 | /* Force Event */ |
---|
1139 | #define SD_FE 0x0250 |
---|
1140 | /* ADMA Error Status */ |
---|
1141 | #define SD_ADMAES 0x0254 |
---|
1142 | /* ADMA System Address Low bits */ |
---|
1143 | #define SD_ADMASAL 0x0258 |
---|
1144 | /* ADMA System Address High bits */ |
---|
1145 | #define SD_ADMASAH 0x025C |
---|
1146 | /* Versions */ |
---|
1147 | #define SD_REV 0x02FC |
---|
1148 | /*===========================================================================*/ |
---|
1149 | |
---|
1150 | #endif /* AM335X_H */ |
---|