| 1 | //========================================================================== |
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| 2 | // |
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| 3 | // smsc911x.h |
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| 4 | // |
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| 5 | // |
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| 6 | // Author(s): Jay Monkman <jtm@lopingdog.com> |
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| 7 | // Contributors: |
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| 8 | // Date: 06-07-2007 |
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| 9 | // Description: This file contains definitions for the SMSC 911x and 912x |
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| 10 | // families of ethernet controllers. |
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| 11 | // |
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| 12 | //-------------------------------------------------------------------------- |
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| 13 | |
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| 14 | // ------------------------------------------------------------------------ |
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| 15 | // cpuio.h must provide SMSC911X_BASE_ADDRESS |
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| 16 | // defines |
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| 17 | #define SMSC_REG(_x_) *(vulong *)(SMSC911X_BASE_ADDRESS + _x_) |
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| 18 | |
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| 19 | // ------------------------------------------------------------------------ |
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| 20 | // Directly visible registers. |
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| 21 | #define RX_FIFO_PORT SMSC_REG(0x00) |
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| 22 | #define TX_FIFO_PORT SMSC_REG(0x20) |
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| 23 | #define RX_FIFO_PORT_INC SMSC_REG(0x100) |
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| 24 | #define TX_FIFO_PORT_INC SMSC_REG(0x120) |
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| 25 | #define RX_STATUS_FIFO_PORT SMSC_REG(0x40) |
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| 26 | #define RX_STATUS_FIFO_PEEK SMSC_REG(0x44) |
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| 27 | #define RX_STATUS_FF (1 << 30) |
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| 28 | #define RX_STATUS_PL_MASK (0x3fff << 16) |
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| 29 | #define RX_STATUS_PL_SHIFT (16) |
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| 30 | #define RX_STATUS_ES (1 << 15) |
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| 31 | #define RX_STATUS_BF (1 << 13) |
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| 32 | #define RX_STATUS_LE (1 << 12) |
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| 33 | #define RX_STATUS_RF (1 << 11) |
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| 34 | #define RX_STATUS_MF (1 << 10) |
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| 35 | #define RX_STATUS_FTL (1 << 7) |
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| 36 | #define RX_STATUS_CS (1 << 6) |
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| 37 | #define RX_STATUS_FT (1 << 5) |
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| 38 | #define RX_STATUS_RWTO (1 << 4) |
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| 39 | #define RX_STATUS_ME (1 << 3) |
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| 40 | #define RX_STATUS_DB (1 << 2) |
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| 41 | #define RX_STATUS_CE (1 << 1) |
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| 42 | |
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| 43 | #define TX_STATUS_FIFO_PORT SMSC_REG(0x48) |
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| 44 | #define TX_STATUS_FIFO_PEEK SMSC_REG(0x4c) |
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| 45 | #define TX_STATUS_FIFO_ES (1 << 15) |
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| 46 | #define TX_STATUS_FIFO_LOC (1 << 11) |
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| 47 | #define TX_STATUS_FIFO_NC (1 << 10) |
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| 48 | #define TX_STATUS_FIFO_LC (1 << 9) |
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| 49 | #define TX_STATUS_FIFO_EC (1 << 8) |
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| 50 | #define TX_STATUS_FIFO_ED (1 << 2) |
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| 51 | #define TX_STATUS_FIFO_UE (1 << 1) |
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| 52 | #define TX_STATUS_FIFO_D (1 << 0) |
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| 53 | #define TX_STATUS_FIFO_TAG_MASK (0xffff << 16) |
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| 54 | |
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| 55 | #define ID_REV SMSC_REG(0x50) |
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| 56 | #define ID_REV_ID_MASK (0xffff << 16) |
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| 57 | #define ID_REV_CHIP_9118 (0x0115 << 16) |
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| 58 | #define ID_REV_CHIP_9211 (0x9211 << 16) |
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| 59 | #define ID_REV_CHIP_9215 (0x115A << 16) |
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| 60 | #define ID_REV_CHIP_9218 (0x118A << 16) |
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| 61 | #define ID_REV_REV_MASK (0xffff << 0) |
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| 62 | |
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| 63 | #define INT_STS SMSC_REG(0x58) |
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| 64 | #define INT_STS_SW_INT (1 << 21) |
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| 65 | #define INT_STS_TXSTOP_INT (1 << 25) |
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| 66 | #define INT_STS_RXSTOP_INT (1 << 24) |
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| 67 | #define INT_STS_RXDFH_INT (1 << 23) |
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| 68 | #define INT_STS_TIOC_INT (1 << 21) |
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| 69 | #define INT_STS_RXD_INT (1 << 20) |
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| 70 | #define INT_STS_GPT_INT (1 << 19) |
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| 71 | #define INT_STS_PHY_INT (1 << 18) |
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| 72 | #define INT_STS_PMT_INT (1 << 17) |
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| 73 | #define INT_STS_TXSO_INT (1 << 16) |
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| 74 | #define INT_STS_RWT_INT (1 << 15) |
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| 75 | #define INT_STS_RXE_INT (1 << 14) |
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| 76 | #define INT_STS_TXE_INT (1 << 13) |
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| 77 | #define INT_STS_TDFU_INT (1 << 11) |
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| 78 | #define INT_STS_TDFO_INT (1 << 10) |
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| 79 | #define INT_STS_TDFA_INT (1 << 9) |
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| 80 | #define INT_STS_TSFF_INT (1 << 8) |
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| 81 | #define INT_STS_TSFL_INT (1 << 7) |
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| 82 | #define INT_STS_RDXF_INT (1 << 6) |
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| 83 | #define INT_STS_RDFL_INT (1 << 5) |
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| 84 | #define INT_STS_RSFF_INT (1 << 4) |
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| 85 | #define INT_STS_RSFL_INT (1 << 3) |
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| 86 | #define INT_STS_GPIO2_INT (1 << 2) |
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| 87 | #define INT_STS_GPIO1_INT (1 << 1) |
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| 88 | #define INT_STS_GPIO0_INT (1 << 0) |
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| 89 | |
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| 90 | #define BYTE_TEST SMSC_REG(0x64) |
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| 91 | #define BYTE_TEST_VAL (0x87654321) |
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| 92 | |
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| 93 | #define FIFO_INT SMSC_REG(0x68) |
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| 94 | #define FIFO_INT_TDAL(x) (((x) & 0xff) << 24) |
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| 95 | #define FIFO_INT_TSL(x) (((x) & 0xff) << 16) |
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| 96 | #define FIFO_INT_RDAL(x) (((x) & 0xff) << 8) |
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| 97 | #define FIFO_INT_RSL(x) (((x) & 0xff) << 0) |
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| 98 | |
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| 99 | #define RX_CFG SMSC_REG(0x6c) |
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| 100 | #define RX_CFG_END_ALIGN4 (0 << 30) |
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| 101 | #define RX_CFG_END_ALIGN16 (1 << 30) |
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| 102 | #define RX_CFG_END_ALIGN32 (2 << 30) |
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| 103 | #define RX_CFG_FORCE_DISCARD (1 << 15) |
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| 104 | #define RX_CFG_RXDOFF(x) (((x) & 0x1f) << 8) |
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| 105 | |
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| 106 | #define TX_CFG SMSC_REG(0x70) |
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| 107 | #define TX_CFG_TXS_DUMP (1 << 15) |
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| 108 | #define TX_CFG_TXD_DUMP (1 << 14) |
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| 109 | #define TX_CFG_TXSAO (1 << 2) |
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| 110 | #define TX_CFG_TX_ON (1 << 1) |
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| 111 | #define TX_CFG_STOP_TX (1 << 0) |
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| 112 | |
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| 113 | #define HW_CFG SMSC_REG(0x74) |
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| 114 | #define HW_CFG_TTM (1 << 21) |
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| 115 | #define HW_CFG_SF (1 << 20) |
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| 116 | #define HW_CFG_TX_FIF_SZ(x) (((x) & 0xf) << 16) |
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| 117 | #define HW_CFG_TX_FIF_MASK (0xf << 16) |
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| 118 | #define HW_CFG_TR(x) (((x) & 0x3) << 12) |
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| 119 | #define HW_CFG_PHY_CLK_MASK (3 << 5) |
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| 120 | #define HW_CFG_PHY_CLK_INT (0 << 5) |
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| 121 | #define HW_CFG_PHY_CLK_EXT (1 << 5) |
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| 122 | #define HW_CFG_PHY_CLK_DIS (2 << 5) |
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| 123 | #define HW_CFG_SMI_SEL (1 << 3) |
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| 124 | #define HW_CFG_EXT_PHY_EN (1 << 2) |
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| 125 | #define HW_CFG_BITMD_32 (1 << 2) |
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| 126 | #define HW_CFG_SRST_TO (1 << 1) |
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| 127 | #define HW_CFG_SRST (1 << 0) |
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| 128 | |
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| 129 | #define RX_DP_CTL SMSC_REG(0x78) |
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| 130 | #define RX_DP_RX_FFWD (1 << 31) |
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| 131 | |
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| 132 | #define RX_FIFO_INF SMSC_REG(0x7c) |
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| 133 | #define TX_FIFO_RXSUSED_MASK (0x00ff << 16) |
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| 134 | #define TX_FIFO_RXDUSED_MASK (0xffff << 0) |
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| 135 | |
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| 136 | #define TX_FIFO_INF SMSC_REG(0x80) |
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| 137 | #define TX_FIFO_TXSUSED_MASK (0x00ff << 16) |
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| 138 | #define TX_FIFO_TDFREE_MASK (0xffff << 0) |
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| 139 | |
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| 140 | #define PMT_CTRL SMSC_REG(0x84) |
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| 141 | #define PMT_CTRL_PM_MODE_D0 (0 << 12) |
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| 142 | #define PMT_CTRL_PM_MODE_D1 (1 << 12) |
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| 143 | #define PMT_CTRL_PM_MODE_D2 (2 << 12) |
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| 144 | #define PMT_CTRL_PHY_RST (1 << 10) |
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| 145 | #define PMT_CTRL_WOL_EN (1 << 9) |
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| 146 | #define PMT_CTRL_ED_EN (1 << 8) |
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| 147 | #define PMT_CTRL_PME_TYPE (1 << 6) |
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| 148 | #define PMT_CTRL_WUPS_NONE (0 << 4) |
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| 149 | #define PMT_CTRL_WUPS_D2 (1 << 4) |
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| 150 | #define PMT_CTRL_WUPS_D1 (2 << 4) |
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| 151 | #define PMT_CTRL_WUPS_MULT (3 << 4) |
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| 152 | #define PMT_CTRL_PME_IND (1 << 3) |
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| 153 | #define PMT_CTRL_PME_POL (1 << 2) |
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| 154 | #define PMT_CTRL_PME_EN (1 << 1) |
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| 155 | #define PMT_CTRL_PME_READY (1 << 0) |
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| 156 | |
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| 157 | #define GPIO_CFG SMSC_REG(0x88) |
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| 158 | #define GPIO_CFG_LED3_EN (1 << 30) |
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| 159 | #define GPIO_CFG_LED2_EN (1 << 29) |
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| 160 | #define GPIO_CFG_LED1_EN (1 << 28) |
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| 161 | #define GPIO_CFG_GPIO_INT_POL(x) (1 << (((x) & 0x3) + 24)) |
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| 162 | #define GPIO_CFG_EEPR_EEPROM (0 << 20) |
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| 163 | #define GPIO_CFG_GPIOBUF(x) (1 << (((x) & 0x3) + 16)) |
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| 164 | #define GPIO_CFG_GPIODIR(x) (1 << (((x) & 0x3) + 8)) |
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| 165 | |
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| 166 | #define GPT_CFG SMSC_REG(0x8c) |
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| 167 | #define GPT_CFG_TIMER_EN (1 << 29) |
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| 168 | #define GPT_CFG_GPT_LOAD(x) (((x) & 0xffff) << 0) |
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| 169 | |
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| 170 | #define GPT_CNT SMSC_REG(0x90) |
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| 171 | #define GPT_CNT_MASK (0xffff << 0) |
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| 172 | |
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| 173 | #define WORD_SWAP SMSC_REG(0x98) |
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| 174 | #define WORD_SWAP_BIG (0xFFFFFFFF) |
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| 175 | |
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| 176 | #define FREE_RUN SMSC_REG(0x9c) |
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| 177 | |
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| 178 | #define RX_DROP SMSC_REG(0xa0) |
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| 179 | |
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| 180 | #define MAC_CSR_CMD SMSC_REG(0xa4) |
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| 181 | #define MAC_CSR_CMD_CSR_BUSY (0x80000000) |
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| 182 | #define MAC_CSR_CMD_RNW (0x40000000) |
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| 183 | #define MAC_RD_CMD(x) (((x) & 0xff) | (MAC_CSR_CMD_CSR_BUSY |\ |
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| 184 | MAC_CSR_CMD_RNW)) |
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| 185 | #define MAC_WR_CMD(x) (((x) & 0xff) | (MAC_CSR_CMD_CSR_BUSY)) |
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| 186 | |
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| 187 | #define MAC_CSR_DATA SMSC_REG(0xa8) |
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| 188 | |
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| 189 | #define AFC_CFG SMSC_REG(0xac) |
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| 190 | #define AFC_CFG_AFC_HI(x) (((x) & 0xff) << 16) |
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| 191 | #define AFC_CFG_AFC_LO(x) (((x) & 0xff) << 8) |
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| 192 | #define AFC_CFG_BACK_DUR(x) (((x) & 0xf) << 4) |
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| 193 | #define AFC_CFG_FCMULT (1 << 3) |
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| 194 | #define AFC_CFG_FCBRD (1 << 2) |
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| 195 | #define AFC_CFG_FCADD (1 << 1) |
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| 196 | #define AFC_CFG_FCANY (1 << 0) |
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| 197 | |
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| 198 | #define E2P_CMD SMSC_REG(0xb0) |
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| 199 | #define E2P_DATA SMSC_REG(0xb4) |
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| 200 | |
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| 201 | // ---------------------------------------------------------- |
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| 202 | // Registers available via MAC_CSR_CMD/MAC_CSR_DATA registers |
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| 203 | #define MAC_CR (0x1) |
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| 204 | #define MAC_CR_RXALL (1 << 31) |
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| 205 | #define MAC_CR_RCVOWN (1 << 23) |
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| 206 | #define MAC_CR_LOOPBK (1 << 21) |
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| 207 | #define MAC_CR_FDPX (1 << 20) |
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| 208 | #define MAC_CR_MCPAS (1 << 18) |
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| 209 | #define MAC_CR_PRMS (1 << 18) |
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| 210 | #define MAC_CR_INVFILT (1 << 17) |
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| 211 | #define MAC_CR_PASSBAD (1 << 16) |
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| 212 | #define MAC_CR_HO (1 << 15) |
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| 213 | #define MAC_CR_HPFILT (1 << 13) |
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| 214 | #define MAC_CR_LCOLL (1 << 12) |
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| 215 | #define MAC_CR_BCAST (1 << 11) |
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| 216 | #define MAC_CR_DISRTY (1 << 10) |
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| 217 | #define MAC_CR_PADSTR (1 << 8) |
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| 218 | #define MAC_CR_BOLMT10 (0 << 6) |
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| 219 | #define MAC_CR_BOLMT8 (1 << 6) |
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| 220 | #define MAC_CR_BOLMT4 (2 << 6) |
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| 221 | #define MAC_CR_BOLMT1 (3 << 6) |
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| 222 | #define MAC_CR_DFCHK (1 << 5) |
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| 223 | #define MAC_CR_TXEN (1 << 3) |
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| 224 | #define MAC_CR_RXEN (1 << 2) |
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| 225 | |
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| 226 | #define ADDRH (0x2) |
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| 227 | #define ADDRL (0x3) |
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| 228 | #define HASHH (0x4) |
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| 229 | #define HASHL (0x5) |
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| 230 | |
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| 231 | #define MII_ACC (0x6) |
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| 232 | #define MII_ACC_ADDR(x) (((x) & 0x1f) << 11) |
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| 233 | #define MII_ACC_REG(x) (((x) & 0x1f) << 6) |
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| 234 | #define MII_ACC_WR (1 << 1) |
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| 235 | #define MII_ACC_BUSY (1 << 0) |
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| 236 | |
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| 237 | #define MII_DATA (0x7) |
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| 238 | #define FLOW (0x8) |
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| 239 | #define VLAN1 (0x9) |
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| 240 | #define VLAN2 (0xa) |
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| 241 | #define WUFF (0xb) |
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| 242 | #define WUCSR (0xc) |
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| 243 | |
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| 244 | // ---------------------------------------------------------- |
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| 245 | // PHY Registers |
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| 246 | #define PHY_BCR 0 |
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| 247 | #define PHY_BCR_RESET (1 << 15) |
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| 248 | #define PHY_BCR_LOOP (1 << 14) |
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| 249 | #define PHY_BCR_SPEED (1 << 13) |
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| 250 | #define PHY_BCR_ANE (1 << 12) |
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| 251 | #define PHY_BCR_PD (1 << 11) |
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| 252 | #define PHY_BCR_RAN (1 << 9) |
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| 253 | #define PHY_BCR_FD (1 << 8) |
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| 254 | #define PHY_BCR_CT (1 << 7) |
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| 255 | |
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| 256 | #define PHY_BSR 1 |
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| 257 | #define PHY_PHY1 2 |
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| 258 | #define PHY_PHY2 3 |
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| 259 | #define PHY_ANAR 4 |
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| 260 | #define PHY_ANAR_NP (1 << 15) |
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| 261 | #define PHY_ANAR_RF (1 << 13) |
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| 262 | #define PHY_ANAR_PAUSE(x) (((x) & 0x3) << 10) |
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| 263 | #define PHY_ANAR_100T4 (1 << 9) |
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| 264 | #define PHY_ANAR_100TX_FD (1 << 8) |
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| 265 | #define PHY_ANAR_100TX (1 << 7) |
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| 266 | #define PHY_ANAR_10T_FD (1 << 6) |
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| 267 | #define PHY_ANAR_10T (1 << 5) |
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| 268 | #define PHY_ANAR_SF (0x01) |
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| 269 | |
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| 270 | |
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| 271 | #define PHY_ANLPAR 5 |
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| 272 | #define PHY_ANER 6 |
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| 273 | #define PHY_MCSR 17 |
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| 274 | #define PHY_SMR 18 |
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| 275 | #define PHY_SCSI 27 |
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| 276 | #define PHY_ISR 29 |
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| 277 | #define PHY_IMR 30 |
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| 278 | #define PHY_PSCSR 31 |
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| 279 | |
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| 280 | |
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| 281 | // ---------------------------------------------------------- |
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| 282 | // TX and RX command definitions |
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| 283 | #define TX_CMD_IC (1 << 31) |
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| 284 | #define TX_CMD_BEA(x) (((x) & 0x3) << 24) |
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| 285 | #define TX_CMD_DS(x) (((x) & 0x1f) << 16) |
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| 286 | #define TX_CMD_FS (1 << 13) |
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| 287 | #define TX_CMD_LS (1 << 12) |
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| 288 | #define TX_CMD_BS(x) (((x) & 0x7ff) << 0) |
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| 289 | #define TX_CMD_TAG(x) (((x) & 0xffff) << 16) |
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| 290 | #define TX_CMD_CRCDIS (1 << 13) |
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| 291 | #define TX_CMD_PKTLEN(x) (((x) & 0x7ff) << 0) |
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| 292 | |
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| 293 | |
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| 294 | |
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| 295 | void smsc911x_reset(void); |
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| 296 | int smsc911x_rx(uchar *); |
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| 297 | int smsc911x_tx(uchar *, ulong); |
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| 298 | int smsc911x_init(void); |
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| 299 | void smsc911x_enable_promiscuous_reception(void); |
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| 300 | void smsc911x_disable_promiscuous_reception(void); |
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| 301 | void smsc911x_enable_multicast_reception(void); |
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| 302 | void smsc911x_disable_multicast_reception(void); |
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| 303 | void smsc911x_enable_broadcast_reception(void); |
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| 304 | void smsc911x_disable_broadcast_reception(void); |
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