source: umon/main/cpu/arm/arm.h @ 6e6815e

Last change on this file since 6e6815e was 6e6815e, checked in by Ben Gras <beng@…>, on Jun 20, 2016 at 3:24:20 PM

ARM: save and print exception context

Debugging aid. Prints nice exception context info like:

R0 = 0x00000000 R8 = 0x402fe8b0
R1 = 0x402ffd80 R9 = 0x40309b15
R2 = 0x00000800 R10 = 0x00000000
R3 = 0x402ffd40 R11 = 0x00000000
R4 = 0x402ffd40 R12 = 0x402fdd38
R5 = 0x402ffd80 SP = 0x40309694
R6 = 0x00000003 LR = 0x402fa348
R7 = 0x00000800 PC = 0x402f8614
VEC = 0x00000003

Data structures, definitions and code taken from RTEMS.

  • Property mode set to 100644
File size: 4.9 KB
Line 
1/**************************************************************************
2 *
3 * Copyright (c) 2013 Alcatel-Lucent
4 *
5 * Alcatel Lucent licenses this file to You under the Apache License,
6 * Version 2.0 (the "License"); you may not use this file except in
7 * compliance with the License.  A copy of the License is contained the
8 * file LICENSE at the top level of this repository.
9 * You may also obtain a copy of the License at:
10 *
11 *      http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 **************************************************************************
20 *
21 * arm.h
22 *
23 * PSR Bits
24 *
25 * Original author:     Ed Sutter (ed.sutter@alcatel-lucent.com)
26 *
27 */
28#define PSR_THUMB_STATE         0x00000020
29#define PSR_IMASK_IRQ           0x00000080
30#define PSR_IMASK_FRQ           0x00000040
31#define PSR_CONDITION_NEGATIVE  0x80000000
32#define PSR_CONDITION_ZERO      0x40000000
33#define PSR_CONDITION_CARRY     0x20000000
34#define PSR_CONDITION_OVERFLOW  0x10000000
35#define PSR_MODE_MASK           0x0000001f
36
37/* Mode bits within PSR:
38 */
39#define ABORT_MODE          0x00000017
40#define FASTINTRQST_MODE    0x00000011
41#define INTRQST_MODE        0x00000012
42#define SUPERVISOR_MODE     0x00000013
43#define SYSTEM_MODE         0x0000001f
44#define UNDEFINED_MODE      0x0000001b
45#define USER_MODE           0x00000010
46
47/* Exception types:
48 */
49#define EXCTYPE_UNDEF       1
50#define EXCTYPE_ABORTP      2
51#define EXCTYPE_ABORTD      3
52#define EXCTYPE_IRQ         4
53#define EXCTYPE_FIRQ        5
54#define EXCTYPE_SWI         6
55#define EXCTYPE_NOTASSGN    7
56
57/* Link register adjustments for each exception:
58 * These adjustments are used by the exception handler to establish the
59 * address at which the exception occurred.
60 */
61#define LRADJ_UNDEF         4
62#define LRADJ_ABORTP        4
63#define LRADJ_ABORTD        8
64#define LRADJ_IRQ           4
65#define LRADJ_FIRQ          4
66#define LRADJ_SWI           4
67
68/* Vector numbers used by assign_handler and the mon_assignhandler()
69 * API function...
70 */
71#define VEC_RST              0
72#define VEC_UND              1
73#define VEC_SWI              2
74#define VEC_ABP              3
75#define VEC_ABD              4
76#define VEC_IRQ              5
77#define VEC_RESERVED         6
78#define VEC_FIQ              7
79
80/* Taken from RTEMS score/cpu.h */
81#define ARM_EXCEPTION_FRAME_SIZE 80
82#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52
83#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72
84
85#define ARM_PSR_N (1 << 31)
86#define ARM_PSR_Z (1 << 30)
87#define ARM_PSR_C (1 << 29)
88#define ARM_PSR_V (1 << 28)
89#define ARM_PSR_Q (1 << 27)
90#define ARM_PSR_J (1 << 24)
91#define ARM_PSR_GE_SHIFT 16
92#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
93#define ARM_PSR_E (1 << 9)
94#define ARM_PSR_A (1 << 8)
95#define ARM_PSR_I (1 << 7)
96#define ARM_PSR_F (1 << 6)
97#define ARM_PSR_T (1 << 5)
98#define ARM_PSR_M_SHIFT 0
99#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
100#define ARM_PSR_M_USR 0x10
101#define ARM_PSR_M_FIQ 0x11
102#define ARM_PSR_M_IRQ 0x12
103#define ARM_PSR_M_SVC 0x13
104#define ARM_PSR_M_ABT 0x17
105#define ARM_PSR_M_UND 0x1b
106#define ARM_PSR_M_SYS 0x1f
107
108#ifndef _ASSEMBLY_
109
110#include "stddefs.h"
111
112/* Exception context.
113 * These data structures gratefully taken from the RTEMS
114 * source code cpukit/score/cpu/arm/rtems/score/cpu.h
115 */
116
117typedef struct {
118  uint32_t register_fpexc;
119  uint32_t register_fpscr;
120  uint64_t register_d0;
121  uint64_t register_d1;
122  uint64_t register_d2;
123  uint64_t register_d3;
124  uint64_t register_d4;
125  uint64_t register_d5;
126  uint64_t register_d6;
127  uint64_t register_d7;
128  uint64_t register_d8;
129  uint64_t register_d9;
130  uint64_t register_d10;
131  uint64_t register_d11;
132  uint64_t register_d12;
133  uint64_t register_d13;
134  uint64_t register_d14;
135  uint64_t register_d15;
136  uint64_t register_d16;
137  uint64_t register_d17;
138  uint64_t register_d18;
139  uint64_t register_d19;
140  uint64_t register_d20;
141  uint64_t register_d21;
142  uint64_t register_d22;
143  uint64_t register_d23;
144  uint64_t register_d24;
145  uint64_t register_d25;
146  uint64_t register_d26;
147  uint64_t register_d27;
148  uint64_t register_d28;
149  uint64_t register_d29;
150  uint64_t register_d30;
151  uint64_t register_d31;
152} ARM_VFP_context;
153
154typedef struct {
155  uint32_t register_r0;
156  uint32_t register_r1;
157  uint32_t register_r2;
158  uint32_t register_r3;
159  uint32_t register_r4;
160  uint32_t register_r5;
161  uint32_t register_r6;
162  uint32_t register_r7;
163  uint32_t register_r8;
164  uint32_t register_r9;
165  uint32_t register_r10;
166  uint32_t register_r11;
167  uint32_t register_r12;
168  uint32_t register_sp;
169  void *register_lr;
170  void *register_pc;
171  uint32_t register_cpsr;
172  int vector;
173  const ARM_VFP_context *vfp_context;
174  uint32_t reserved_for_stack_alignment;
175} CPU_Exception_frame;
176
177#endif
Note: See TracBrowser for help on using the repository browser.