source: rtems/testsuites/sptests/spcache01/spcache01.scn @ 7e5c9b89

4.115
Last change on this file since 7e5c9b89 was 7e5c9b89, checked in by Sebastian Huber <sebastian.huber@…>, on 11/25/14 at 13:58:13

rtems: Move rtems_cache_aligned_malloc()

Make sure also the size is cache aligned since otherwise we may have
some overlap with the next allocation block. A cache invalidate on this
area would be fatal.

  • Property mode set to 100644
File size: 1.7 KB
RevLine 
[3378be95]1*** TEST SPCACHE 1 ***
2data cache flush and invalidate test
3data cache operations by line passed the test
[31494ab2]4data cache operations by line passed the test (copy-back cache detected)
[3378be95]5data cache line size 32 bytes
[e1d7bf0]6data cache size 262144 bytes
7data cache level 1 size 32768 bytes
8data cache level 2 size 262144 bytes
[3378be95]9load 4096 bytes with flush entire data
10  duration with normal cache 12660 ns
11  duration with warm cache 2580 ns
12  duration with flushed cache 2580 ns
13load 4096 bytes with flush multiple data
14  duration with normal cache 2600 ns
15  duration with warm cache 2580 ns
16  duration with flushed cache 11400 ns
17load 4096 bytes with invalidate multiple data
18  duration with normal cache 2580 ns
19  duration with warm cache 2580 ns
20  duration with invalidated cache 11620 ns
21store 4096 bytes with flush entire data
22  duration with normal cache 2600 ns
23  duration with warm cache 2580 ns
24  duration with flushed cache 2580 ns
25store 4096 bytes with flush multiple data
26  duration with normal cache 2580 ns
27  duration with warm cache 2580 ns
28  duration with flushed cache 3000 ns
29store 4096 bytes with invalidate multiple data
30  duration with normal cache 2580 ns
31  duration with warm cache 2580 ns
32  duration with invalidated cache 2640 ns
33instruction cache line size 32 bytes
[e1d7bf0]34instruction cache size 262144 bytes
35instruction cache level 1 size 32768 bytes
36instruction cache level 2 size 262144 bytes
[3378be95]37invalidate entire instruction
38  duration with normal cache 5780 ns
39  duration with warm cache 640 ns
40  duration with invalidated cache 640 ns
41invalidate multiple instruction
42  duration with normal cache 680 ns
43  duration with warm cache 640 ns
44  duration with invalidated cache 2600 ns
[7e5c9b89]45test rtems_cache_aligned_malloc()
[3378be95]46*** END OF TEST SPCACHE 1 ***
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