1 | /* |
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2 | * Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #ifdef HAVE_CONFIG_H |
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16 | #include "config.h" |
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17 | #endif |
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18 | |
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19 | #include <stdio.h> |
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20 | #include <stdlib.h> |
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21 | #include <inttypes.h> |
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22 | |
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23 | #include <rtems.h> |
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24 | #include <rtems/counter.h> |
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25 | #include <rtems/score/sysstate.h> |
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26 | |
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27 | #define TESTS_USE_PRINTF |
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28 | #include "tmacros.h" |
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29 | |
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30 | const char rtems_test_name[] = "SPCACHE 1"; |
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31 | |
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32 | #ifdef __or1k__ |
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33 | #define I() __asm__ volatile ("l.nop") |
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34 | #else |
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35 | #define I() __asm__ volatile ("nop") |
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36 | #endif |
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37 | |
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38 | #define I8() I(); I(); I(); I(); I(); I(); I(); I() |
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39 | |
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40 | #define I64() I8(); I8(); I8(); I8(); I8(); I8(); I8(); I8() |
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41 | |
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42 | #define I512() I64(); I64(); I64(); I64(); I64(); I64(); I64(); I64() |
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43 | |
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44 | CPU_STRUCTURE_ALIGNMENT static int data[1024]; |
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45 | |
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46 | static void test_data_flush_and_invalidate(void) |
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47 | { |
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48 | if (rtems_cache_get_data_line_size() > 0) { |
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49 | rtems_interrupt_lock lock; |
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50 | rtems_interrupt_lock_context lock_context; |
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51 | volatile int *vdata = &data[0]; |
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52 | int n = 32; |
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53 | int i; |
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54 | size_t data_size = n * sizeof(data[0]); |
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55 | bool write_through; |
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56 | |
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57 | printf("data cache flush and invalidate test\n"); |
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58 | |
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59 | rtems_interrupt_lock_initialize(&lock, "test"); |
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60 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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61 | |
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62 | for (i = 0; i < n; ++i) { |
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63 | vdata[i] = i; |
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64 | } |
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65 | |
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66 | rtems_cache_flush_multiple_data_lines(&data[0], data_size); |
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67 | |
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68 | for (i = 0; i < n; ++i) { |
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69 | rtems_test_assert(vdata[i] == i); |
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70 | } |
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71 | |
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72 | for (i = 0; i < n; ++i) { |
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73 | vdata[i] = ~i; |
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74 | } |
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75 | |
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76 | rtems_cache_invalidate_multiple_data_lines(&data[0], data_size); |
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77 | |
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78 | write_through = vdata[0] == ~0; |
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79 | if (write_through) { |
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80 | for (i = 0; i < n; ++i) { |
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81 | rtems_test_assert(vdata[i] == ~i); |
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82 | } |
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83 | } else { |
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84 | for (i = 0; i < n; ++i) { |
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85 | rtems_test_assert(vdata[i] == i); |
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86 | } |
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87 | } |
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88 | |
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89 | for (i = 0; i < n; ++i) { |
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90 | vdata[i] = ~i; |
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91 | } |
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92 | |
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93 | rtems_cache_flush_multiple_data_lines(&data[0], data_size); |
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94 | rtems_cache_invalidate_multiple_data_lines(&data[0], data_size); |
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95 | |
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96 | for (i = 0; i < n; ++i) { |
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97 | rtems_test_assert(vdata[i] == ~i); |
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98 | } |
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99 | |
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100 | rtems_interrupt_lock_release(&lock, &lock_context); |
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101 | rtems_interrupt_lock_destroy(&lock); |
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102 | |
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103 | printf( |
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104 | "data cache operations by line passed the test (%s cache detected)\n", |
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105 | write_through ? "write-through" : "copy-back" |
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106 | ); |
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107 | } else { |
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108 | printf( |
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109 | "skip data cache flush and invalidate test" |
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110 | " due to cache line size of zero\n" |
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111 | ); |
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112 | } |
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113 | |
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114 | /* Make sure these are nops */ |
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115 | rtems_cache_flush_multiple_data_lines(NULL, 0); |
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116 | rtems_cache_invalidate_multiple_data_lines(NULL, 0); |
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117 | } |
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118 | |
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119 | static uint64_t do_some_work(void) |
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120 | { |
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121 | rtems_counter_ticks a; |
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122 | rtems_counter_ticks b; |
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123 | rtems_counter_ticks d; |
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124 | |
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125 | /* This gives 1024 nop instructions */ |
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126 | a = rtems_counter_read(); |
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127 | I512(); |
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128 | I512(); |
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129 | b = rtems_counter_read(); |
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130 | |
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131 | d = rtems_counter_difference(b, a); |
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132 | |
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133 | return rtems_counter_ticks_to_nanoseconds(d); |
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134 | } |
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135 | |
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136 | static uint64_t load(void) |
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137 | { |
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138 | rtems_counter_ticks a; |
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139 | rtems_counter_ticks b; |
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140 | rtems_counter_ticks d; |
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141 | size_t i; |
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142 | volatile int *vdata = &data[0]; |
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143 | |
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144 | a = rtems_counter_read(); |
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145 | for (i = 0; i < RTEMS_ARRAY_SIZE(data); ++i) { |
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146 | vdata[i]; |
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147 | } |
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148 | b = rtems_counter_read(); |
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149 | |
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150 | d = rtems_counter_difference(b, a); |
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151 | |
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152 | return rtems_counter_ticks_to_nanoseconds(d); |
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153 | } |
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154 | |
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155 | static uint64_t store(void) |
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156 | { |
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157 | rtems_counter_ticks a; |
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158 | rtems_counter_ticks b; |
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159 | rtems_counter_ticks d; |
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160 | size_t i; |
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161 | volatile int *vdata = &data[0]; |
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162 | |
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163 | a = rtems_counter_read(); |
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164 | for (i = 0; i < RTEMS_ARRAY_SIZE(data); ++i) { |
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165 | vdata[i] = 0; |
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166 | } |
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167 | b = rtems_counter_read(); |
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168 | |
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169 | d = rtems_counter_difference(b, a); |
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170 | |
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171 | return rtems_counter_ticks_to_nanoseconds(d); |
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172 | } |
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173 | |
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174 | static void test_timing(void) |
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175 | { |
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176 | rtems_interrupt_lock lock; |
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177 | rtems_interrupt_lock_context lock_context; |
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178 | size_t data_size = sizeof(data); |
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179 | uint64_t d[3]; |
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180 | uint32_t cache_level; |
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181 | size_t cache_size; |
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182 | |
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183 | rtems_interrupt_lock_initialize(&lock, "test"); |
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184 | |
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185 | printf( |
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186 | "data cache line size %zi bytes\n" |
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187 | "data cache size %zi bytes\n", |
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188 | rtems_cache_get_data_line_size(), |
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189 | rtems_cache_get_data_cache_size(0) |
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190 | ); |
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191 | |
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192 | cache_level = 1; |
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193 | cache_size = rtems_cache_get_data_cache_size(cache_level); |
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194 | while (cache_size > 0) { |
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195 | printf( |
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196 | "data cache level %" PRIu32 " size %zi bytes\n", |
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197 | cache_level, |
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198 | cache_size |
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199 | ); |
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200 | ++cache_level; |
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201 | cache_size = rtems_cache_get_data_cache_size(cache_level); |
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202 | } |
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203 | |
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204 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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205 | |
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206 | d[0] = load(); |
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207 | d[1] = load(); |
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208 | rtems_cache_flush_entire_data(); |
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209 | d[2] = load(); |
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210 | |
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211 | rtems_interrupt_lock_release(&lock, &lock_context); |
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212 | |
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213 | printf( |
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214 | "load %zi bytes with flush entire data\n" |
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215 | " duration with normal cache %" PRIu64 " ns\n" |
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216 | " duration with warm cache %" PRIu64 " ns\n" |
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217 | " duration with flushed cache %" PRIu64 " ns\n", |
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218 | data_size, |
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219 | d[0], |
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220 | d[1], |
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221 | d[2] |
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222 | ); |
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223 | |
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224 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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225 | |
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226 | d[0] = load(); |
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227 | d[1] = load(); |
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228 | rtems_cache_flush_multiple_data_lines(&data[0], sizeof(data)); |
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229 | d[2] = load(); |
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230 | |
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231 | rtems_interrupt_lock_release(&lock, &lock_context); |
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232 | |
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233 | printf( |
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234 | "load %zi bytes with flush multiple data\n" |
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235 | " duration with normal cache %" PRIu64 " ns\n" |
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236 | " duration with warm cache %" PRIu64 " ns\n" |
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237 | " duration with flushed cache %" PRIu64 " ns\n", |
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238 | data_size, |
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239 | d[0], |
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240 | d[1], |
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241 | d[2] |
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242 | ); |
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243 | |
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244 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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245 | |
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246 | d[0] = load(); |
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247 | d[1] = load(); |
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248 | rtems_cache_invalidate_multiple_data_lines(&data[0], sizeof(data)); |
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249 | d[2] = load(); |
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250 | |
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251 | rtems_interrupt_lock_release(&lock, &lock_context); |
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252 | |
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253 | printf( |
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254 | "load %zi bytes with invalidate multiple data\n" |
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255 | " duration with normal cache %" PRIu64 " ns\n" |
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256 | " duration with warm cache %" PRIu64 " ns\n" |
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257 | " duration with invalidated cache %" PRIu64 " ns\n", |
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258 | data_size, |
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259 | d[0], |
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260 | d[1], |
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261 | d[2] |
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262 | ); |
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263 | |
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264 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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265 | |
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266 | d[0] = store(); |
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267 | d[1] = store(); |
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268 | rtems_cache_flush_entire_data(); |
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269 | d[2] = store(); |
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270 | |
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271 | rtems_interrupt_lock_release(&lock, &lock_context); |
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272 | |
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273 | printf( |
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274 | "store %zi bytes with flush entire data\n" |
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275 | " duration with normal cache %" PRIu64 " ns\n" |
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276 | " duration with warm cache %" PRIu64 " ns\n" |
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277 | " duration with flushed cache %" PRIu64 " ns\n", |
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278 | data_size, |
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279 | d[0], |
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280 | d[1], |
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281 | d[2] |
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282 | ); |
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283 | |
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284 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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285 | |
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286 | d[0] = store(); |
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287 | d[1] = store(); |
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288 | rtems_cache_flush_multiple_data_lines(&data[0], sizeof(data)); |
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289 | d[2] = store(); |
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290 | |
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291 | rtems_interrupt_lock_release(&lock, &lock_context); |
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292 | |
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293 | printf( |
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294 | "store %zi bytes with flush multiple data\n" |
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295 | " duration with normal cache %" PRIu64 " ns\n" |
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296 | " duration with warm cache %" PRIu64 " ns\n" |
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297 | " duration with flushed cache %" PRIu64 " ns\n", |
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298 | data_size, |
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299 | d[0], |
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300 | d[1], |
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301 | d[2] |
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302 | ); |
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303 | |
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304 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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305 | |
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306 | d[0] = store(); |
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307 | d[1] = store(); |
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308 | rtems_cache_invalidate_multiple_data_lines(&data[0], sizeof(data)); |
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309 | d[2] = store(); |
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310 | |
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311 | rtems_interrupt_lock_release(&lock, &lock_context); |
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312 | |
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313 | printf( |
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314 | "store %zi bytes with invalidate multiple data\n" |
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315 | " duration with normal cache %" PRIu64 " ns\n" |
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316 | " duration with warm cache %" PRIu64 " ns\n" |
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317 | " duration with invalidated cache %" PRIu64 " ns\n", |
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318 | data_size, |
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319 | d[0], |
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320 | d[1], |
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321 | d[2] |
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322 | ); |
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323 | |
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324 | printf( |
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325 | "instruction cache line size %zi bytes\n" |
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326 | "instruction cache size %zi bytes\n", |
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327 | rtems_cache_get_instruction_line_size(), |
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328 | rtems_cache_get_instruction_cache_size(0) |
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329 | ); |
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330 | |
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331 | cache_level = 1; |
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332 | cache_size = rtems_cache_get_instruction_cache_size(cache_level); |
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333 | while (cache_size > 0) { |
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334 | printf( |
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335 | "instruction cache level %" PRIu32 " size %zi bytes\n", |
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336 | cache_level, |
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337 | cache_size |
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338 | ); |
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339 | ++cache_level; |
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340 | cache_size = rtems_cache_get_instruction_cache_size(cache_level); |
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341 | } |
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342 | |
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343 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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344 | |
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345 | d[0] = do_some_work(); |
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346 | d[1] = do_some_work(); |
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347 | rtems_cache_invalidate_entire_instruction(); |
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348 | d[2] = do_some_work(); |
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349 | |
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350 | rtems_interrupt_lock_release(&lock, &lock_context); |
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351 | |
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352 | printf( |
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353 | "invalidate entire instruction\n" |
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354 | " duration with normal cache %" PRIu64 " ns\n" |
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355 | " duration with warm cache %" PRIu64 " ns\n" |
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356 | " duration with invalidated cache %" PRIu64 " ns\n", |
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357 | d[0], |
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358 | d[1], |
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359 | d[2] |
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360 | ); |
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361 | |
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362 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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363 | |
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364 | d[0] = do_some_work(); |
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365 | d[1] = do_some_work(); |
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366 | rtems_cache_invalidate_multiple_instruction_lines(do_some_work, 4096); |
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367 | d[2] = do_some_work(); |
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368 | |
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369 | rtems_interrupt_lock_release(&lock, &lock_context); |
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370 | |
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371 | printf( |
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372 | "invalidate multiple instruction\n" |
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373 | " duration with normal cache %" PRIu64 " ns\n" |
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374 | " duration with warm cache %" PRIu64 " ns\n" |
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375 | " duration with invalidated cache %" PRIu64 " ns\n", |
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376 | d[0], |
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377 | d[1], |
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378 | d[2] |
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379 | ); |
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380 | |
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381 | rtems_interrupt_lock_destroy(&lock); |
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382 | } |
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383 | |
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384 | static void test_cache_aligned_alloc(void) |
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385 | { |
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386 | void *p0; |
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387 | void *p1; |
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388 | size_t cls; |
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389 | |
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390 | printf("test rtems_cache_aligned_malloc()\n"); |
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391 | |
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392 | p0 = rtems_cache_aligned_malloc(1); |
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393 | p1 = rtems_cache_aligned_malloc(1); |
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394 | |
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395 | rtems_test_assert(p0 != NULL); |
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396 | rtems_test_assert(p1 != NULL); |
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397 | |
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398 | cls = rtems_cache_get_data_line_size(); |
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399 | if (cls > 0) { |
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400 | size_t m = cls - 1; |
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401 | uintptr_t a0 = (uintptr_t) p0; |
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402 | uintptr_t a1 = (uintptr_t) p1; |
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403 | |
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404 | rtems_test_assert(a1 - a0 > cls); |
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405 | rtems_test_assert((a0 & m) == 0); |
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406 | rtems_test_assert((a1 & m) == 0); |
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407 | } |
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408 | |
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409 | free(p0); |
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410 | free(p1); |
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411 | } |
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412 | |
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413 | #define AREA_SIZE 256 |
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414 | |
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415 | static char cache_coherent_area_0[AREA_SIZE]; |
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416 | |
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417 | static char cache_coherent_area_1[AREA_SIZE]; |
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418 | |
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419 | static char cache_coherent_area_2[AREA_SIZE]; |
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420 | |
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421 | static void add_area(void *begin) |
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422 | { |
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423 | rtems_cache_coherent_add_area(NULL, 0); |
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424 | rtems_cache_coherent_add_area(begin, AREA_SIZE); |
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425 | } |
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426 | |
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427 | static void test_cache_coherent_alloc(void) |
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428 | { |
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429 | void *p0; |
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430 | void *p1; |
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431 | System_state_Codes previous_state; |
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432 | |
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433 | printf("test cache coherent allocation\n"); |
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434 | |
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435 | p0 = rtems_cache_coherent_allocate(1, 0, 0); |
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436 | rtems_test_assert(p0 != NULL); |
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437 | |
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438 | rtems_cache_coherent_free(p0); |
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439 | |
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440 | p0 = rtems_cache_coherent_allocate(1, 0, 0); |
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441 | rtems_test_assert(p0 != NULL); |
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442 | |
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443 | add_area(&cache_coherent_area_0[0]); |
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444 | add_area(&cache_coherent_area_1[0]); |
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445 | |
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446 | previous_state = _System_state_Get(); |
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447 | _System_state_Set(previous_state + 1); |
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448 | add_area(&cache_coherent_area_2[0]); |
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449 | _System_state_Set(previous_state); |
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450 | |
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451 | p1 = rtems_cache_coherent_allocate(1, 0, 0); |
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452 | rtems_test_assert(p1 != NULL); |
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453 | |
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454 | rtems_cache_coherent_free(p0); |
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455 | rtems_cache_coherent_free(p1); |
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456 | } |
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457 | |
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458 | static void Init(rtems_task_argument arg) |
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459 | { |
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460 | TEST_BEGIN(); |
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461 | |
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462 | test_data_flush_and_invalidate(); |
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463 | test_timing(); |
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464 | test_cache_aligned_alloc(); |
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465 | test_cache_coherent_alloc(); |
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466 | |
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467 | TEST_END(); |
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468 | |
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469 | rtems_test_exit(0); |
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470 | } |
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471 | |
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472 | #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER |
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473 | #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER |
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474 | |
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475 | #define CONFIGURE_MAXIMUM_TASKS 1 |
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476 | |
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477 | #define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION |
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478 | |
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479 | #define CONFIGURE_RTEMS_INIT_TASKS_TABLE |
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480 | |
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481 | #define CONFIGURE_INIT |
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482 | |
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483 | #include <rtems/confdefs.h> |
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