1 | /* |
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2 | * Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #ifdef HAVE_CONFIG_H |
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16 | #include "config.h" |
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17 | #endif |
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18 | |
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19 | #include <rtems/score/smpimpl.h> |
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20 | #include <rtems/score/smpbarrier.h> |
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21 | #include <rtems/counter.h> |
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22 | #include <rtems.h> |
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23 | |
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24 | #include <stdio.h> |
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25 | |
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26 | #include "tmacros.h" |
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27 | |
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28 | const char rtems_test_name[] = "SMPIPI 1"; |
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29 | |
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30 | #define CPU_COUNT 32 |
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31 | |
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32 | typedef struct { |
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33 | uint32_t value; |
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34 | uint32_t cache_line_separation[31]; |
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35 | } test_counter; |
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36 | |
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37 | typedef struct { |
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38 | test_counter counters[CPU_COUNT]; |
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39 | uint32_t copy_counters[CPU_COUNT]; |
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40 | SMP_barrier_Control barrier; |
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41 | SMP_barrier_State main_barrier_state; |
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42 | SMP_barrier_State worker_barrier_state; |
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43 | } test_context; |
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44 | |
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45 | static test_context test_instance = { |
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46 | .barrier = SMP_BARRIER_CONTROL_INITIALIZER, |
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47 | .main_barrier_state = SMP_BARRIER_STATE_INITIALIZER, |
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48 | .worker_barrier_state = SMP_BARRIER_STATE_INITIALIZER |
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49 | }; |
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50 | |
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51 | static void barrier( |
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52 | test_context *ctx, |
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53 | SMP_barrier_State *state |
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54 | ) |
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55 | { |
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56 | _SMP_barrier_Wait(&ctx->barrier, state, 2); |
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57 | } |
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58 | |
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59 | static void barrier_handler(Per_CPU_Control *cpu_self) |
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60 | { |
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61 | test_context *ctx = &test_instance; |
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62 | uint32_t cpu_index_self = _Per_CPU_Get_index(cpu_self); |
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63 | SMP_barrier_State *bs = &ctx->worker_barrier_state; |
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64 | |
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65 | ++ctx->counters[cpu_index_self].value; |
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66 | |
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67 | /* (A) */ |
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68 | barrier(ctx, bs); |
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69 | |
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70 | /* (B) */ |
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71 | barrier(ctx, bs); |
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72 | |
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73 | /* (C) */ |
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74 | barrier(ctx, bs); |
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75 | } |
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76 | |
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77 | static void test_send_message_while_processing_a_message( |
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78 | test_context *ctx |
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79 | ) |
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80 | { |
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81 | uint32_t cpu_count = rtems_get_processor_count(); |
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82 | uint32_t cpu_index_self = rtems_get_current_processor(); |
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83 | uint32_t cpu_index; |
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84 | SMP_barrier_State *bs = &ctx->main_barrier_state; |
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85 | |
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86 | _SMP_Set_test_message_handler(barrier_handler); |
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87 | |
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88 | for (cpu_index = 0; cpu_index < cpu_count; ++cpu_index) { |
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89 | if (cpu_index != cpu_index_self) { |
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90 | _SMP_Send_message(cpu_index, SMP_MESSAGE_TEST); |
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91 | |
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92 | /* (A) */ |
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93 | barrier(ctx, bs); |
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94 | |
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95 | rtems_test_assert(ctx->counters[cpu_index].value == 1); |
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96 | _SMP_Send_message(cpu_index, SMP_MESSAGE_TEST); |
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97 | |
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98 | /* (B) */ |
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99 | barrier(ctx, bs); |
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100 | |
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101 | rtems_test_assert(ctx->counters[cpu_index].value == 1); |
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102 | |
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103 | /* (C) */ |
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104 | barrier(ctx, bs); |
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105 | |
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106 | /* (A) */ |
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107 | barrier(ctx, bs); |
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108 | |
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109 | rtems_test_assert(ctx->counters[cpu_index].value == 2); |
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110 | |
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111 | /* (B) */ |
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112 | barrier(ctx, bs); |
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113 | |
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114 | /* (C) */ |
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115 | barrier(ctx, bs); |
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116 | |
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117 | ctx->counters[cpu_index].value = 0; |
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118 | } |
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119 | } |
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120 | } |
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121 | |
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122 | static void counter_handler(Per_CPU_Control *cpu_self) |
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123 | { |
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124 | test_context *ctx = &test_instance; |
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125 | uint32_t cpu_index_self = _Per_CPU_Get_index(cpu_self); |
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126 | |
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127 | ++ctx->counters[cpu_index_self].value; |
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128 | } |
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129 | |
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130 | static void test_send_message_flood( |
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131 | test_context *ctx |
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132 | ) |
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133 | { |
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134 | uint32_t cpu_count = rtems_get_processor_count(); |
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135 | uint32_t cpu_index_self = rtems_get_current_processor(); |
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136 | uint32_t cpu_index; |
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137 | |
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138 | _SMP_Set_test_message_handler(counter_handler); |
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139 | |
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140 | for (cpu_index = 0; cpu_index < cpu_count; ++cpu_index) { |
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141 | uint32_t i; |
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142 | |
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143 | /* Wait 1us so that all outstanding messages have been processed */ |
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144 | rtems_counter_delay_nanoseconds(1000000); |
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145 | |
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146 | for (i = 0; i < cpu_count; ++i) { |
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147 | if (i != cpu_index) { |
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148 | ctx->copy_counters[i] = ctx->counters[i].value; |
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149 | } |
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150 | } |
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151 | |
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152 | for (i = 0; i < 100000; ++i) { |
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153 | _SMP_Send_message(cpu_index, SMP_MESSAGE_TEST); |
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154 | } |
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155 | |
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156 | for (i = 0; i < cpu_count; ++i) { |
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157 | if (i != cpu_index) { |
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158 | rtems_test_assert(ctx->copy_counters[i] == ctx->counters[i].value); |
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159 | } |
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160 | } |
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161 | } |
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162 | |
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163 | for (cpu_index = 0; cpu_index < cpu_count; ++cpu_index) { |
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164 | printf( |
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165 | "inter-processor interrupts for processor %" |
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166 | PRIu32 "%s: %" PRIu32 "\n", |
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167 | cpu_index, |
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168 | cpu_index == cpu_index_self ? " (main)" : "", |
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169 | ctx->counters[cpu_index].value |
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170 | ); |
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171 | } |
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172 | } |
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173 | |
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174 | static void test(void) |
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175 | { |
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176 | test_context *ctx = &test_instance; |
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177 | |
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178 | test_send_message_while_processing_a_message(ctx); |
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179 | test_send_message_flood(ctx); |
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180 | } |
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181 | |
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182 | static void Init(rtems_task_argument arg) |
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183 | { |
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184 | TEST_BEGIN(); |
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185 | |
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186 | test(); |
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187 | |
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188 | TEST_END(); |
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189 | rtems_test_exit(0); |
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190 | } |
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191 | |
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192 | #define CONFIGURE_APPLICATION_DOES_NOT_NEED_CLOCK_DRIVER |
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193 | #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER |
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194 | |
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195 | #define CONFIGURE_SMP_APPLICATION |
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196 | |
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197 | #define CONFIGURE_SMP_MAXIMUM_PROCESSORS CPU_COUNT |
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198 | |
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199 | #define CONFIGURE_MAXIMUM_TASKS 1 |
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200 | |
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201 | #define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION |
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202 | |
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203 | #define CONFIGURE_RTEMS_INIT_TASKS_TABLE |
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204 | |
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205 | #define CONFIGURE_INIT |
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206 | |
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207 | #include <rtems/confdefs.h> |
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