1 | /* |
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2 | * Copyright (c) 2012 Deng Hengyi. |
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3 | * |
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4 | * This test case is to test atomic sub operation. |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | * |
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10 | */ |
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11 | |
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12 | #ifdef HAVE_CONFIG_H |
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13 | #include "config.h" |
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14 | #endif |
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15 | |
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16 | #include "system.h" |
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17 | |
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18 | #include <stdlib.h> |
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19 | #include <rtems/rtems/atomic.h> |
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20 | |
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21 | #define TEST_REPEAT 1000 |
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22 | |
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23 | #define ATOMIC_FETCH_SUB_NO_BARRIER(NAME, TYPE, R_TYPE, cpuid, mem_bar)\ |
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24 | { \ |
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25 | Atomic_##TYPE t; \ |
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26 | R_TYPE a; \ |
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27 | R_TYPE b; \ |
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28 | R_TYPE c; \ |
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29 | unsigned int i; \ |
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30 | for (i = 0; i < TEST_REPEAT; i++){ \ |
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31 | a = (R_TYPE)(rand() % ((R_TYPE)-1 / 2)); \ |
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32 | b = (R_TYPE)(rand() % ((R_TYPE)-1 / 2)); \ |
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33 | _Atomic_Store_##NAME(&t, a, ATOMIC_ORDER_RELEASE); \ |
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34 | _Atomic_Fetch_sub_##NAME(&t, b, mem_bar); \ |
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35 | c = _Atomic_Load_##NAME(&t, ATOMIC_ORDER_ACQUIRE); \ |
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36 | rtems_test_assert(c == (R_TYPE)(a - b)); \ |
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37 | } \ |
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38 | locked_printf("\nCPU%d Atomic_Fetch_sub_" #NAME ": SUCCESS\n", cpuid); \ |
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39 | } |
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40 | |
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41 | rtems_task Test_task( |
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42 | rtems_task_argument argument |
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43 | ) |
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44 | { |
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45 | uint32_t cpu_num; |
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46 | char name[5]; |
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47 | char *p; |
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48 | |
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49 | /* Get the task name */ |
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50 | p = rtems_object_get_name( RTEMS_SELF, 5, name ); |
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51 | rtems_test_assert( p != NULL ); |
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52 | |
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53 | /* Get the CPU Number */ |
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54 | cpu_num = rtems_smp_get_current_processor(); |
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55 | |
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56 | /* Print that the task is up and running. */ |
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57 | /* test relaxed barrier */ |
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58 | ATOMIC_FETCH_SUB_NO_BARRIER(uint, Uint, uint_fast32_t, cpu_num, ATOMIC_ORDER_RELAXED); |
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59 | |
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60 | ATOMIC_FETCH_SUB_NO_BARRIER(ptr, Pointer, uintptr_t, cpu_num, ATOMIC_ORDER_RELAXED); |
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61 | |
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62 | /* test acquire barrier */ |
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63 | ATOMIC_FETCH_SUB_NO_BARRIER(uint, Uint, uint_fast32_t, cpu_num, ATOMIC_ORDER_ACQUIRE); |
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64 | |
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65 | ATOMIC_FETCH_SUB_NO_BARRIER(ptr, Pointer, uintptr_t, cpu_num, ATOMIC_ORDER_ACQUIRE); |
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66 | |
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67 | /* test release barrier */ |
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68 | ATOMIC_FETCH_SUB_NO_BARRIER(uint, Uint, uint_fast32_t, cpu_num, ATOMIC_ORDER_RELEASE); |
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69 | |
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70 | ATOMIC_FETCH_SUB_NO_BARRIER(ptr, Pointer, uintptr_t, cpu_num, ATOMIC_ORDER_RELEASE); |
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71 | |
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72 | // ATOMIC_FETCH_SUB_NO_BARRIER(64, cpu_num); |
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73 | |
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74 | /* Set the flag that the task is up and running */ |
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75 | TaskRan[cpu_num] = true; |
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76 | |
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77 | /* Drop into a loop which will keep this task on |
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78 | * running on the cpu. |
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79 | */ |
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80 | while(1); |
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81 | } |
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