source: rtems/testsuites/libtests/spi01/init.c @ c4b8b147

5
Last change on this file since c4b8b147 was c4b8b147, checked in by Sebastian Huber <sebastian.huber@…>, on 11/03/17 at 07:35:38

tests: Use simple console driver

Update #3170.
Update #3199.

  • Property mode set to 100644
File size: 6.4 KB
Line 
1/*
2 * Copyright (c) 2016 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifdef HAVE_CONFIG_H
16  #include "config.h"
17#endif
18
19#include <dev/spi/spi.h>
20
21#include <sys/ioctl.h>
22#include <sys/stat.h>
23#include <errno.h>
24#include <fcntl.h>
25#include <math.h>
26#include <stdlib.h>
27#include <string.h>
28#include <unistd.h>
29
30#include <rtems/libcsupport.h>
31
32#include "tmacros.h"
33
34static uint8_t mode_8 = 0xA5;
35static uint32_t mode_32 = 0x5A5A5A5A;
36static uint32_t speed = 12345678;
37static uint8_t bits_per_word = 12;
38static uint8_t lsb_first = 1;
39
40const char rtems_test_name[] = "SPI 1";
41
42static const char bus_path[] = "/dev/spi-0";
43
44typedef struct test_device test_device;
45
46struct test_device {
47  int (*transfer)(
48    spi_bus *bus,
49    const spi_ioc_transfer *msgs,
50    uint32_t msg_count,
51    test_device *dev
52  );
53};
54
55typedef struct {
56  test_device base;
57  char buf[3];
58} test_device_simple_read_write;
59
60typedef struct {
61  spi_bus base;
62  unsigned long clock;
63  test_device *device;
64  uint32_t msg_count;
65  uint32_t max_speed_hz;
66  test_device_simple_read_write simple_read_write;
67} test_bus;
68
69static int test_simple_read_write_transfer(
70  spi_bus *bus,
71  const spi_ioc_transfer *msgs,
72  uint32_t msg_count,
73  test_device *base
74)
75{
76  (void)bus;
77
78  test_device_simple_read_write *dev = (test_device_simple_read_write *) base;
79
80  if (msg_count == 1 && msgs[0].len == sizeof(dev->buf)) {
81    if (msgs[0].rx_buf == 0){
82        memcpy(&dev->buf[0], msgs[0].tx_buf, sizeof(dev->buf));
83    } else if (msgs[0].tx_buf == 0){
84        memcpy(msgs[0].rx_buf, &dev->buf[0], sizeof(dev->buf));
85    } else {
86        return -EIO;
87    }
88  } else {
89    return -EIO;
90  }
91  return 0;
92}
93
94static int test_transfer(
95  spi_bus *base,
96  const spi_ioc_transfer *msgs,
97  uint32_t msg_count
98)
99{
100  test_bus *bus = (test_bus *) base;
101  test_device *dev;
102
103  dev = bus->device;
104  bus->msg_count = msg_count;
105
106  return (*dev->transfer)(&bus->base, msgs, msg_count, dev);
107}
108
109static int test_setup(spi_bus *base)
110{
111  test_bus *bus = (test_bus *) base;
112
113  if ((base->speed_hz > bus->max_speed_hz) ||
114    ((base->bits_per_word < 8) || (base->bits_per_word > 16))) {
115    return 1;
116  }
117
118  return 0;
119}
120
121static void test_destroy(spi_bus *base)
122{
123  spi_bus_destroy_and_free(base);
124}
125
126static void test_simple_read_write(test_bus *bus, int fd)
127{
128  static const char zero[] = { 0, 0, 0 };
129  static const char abc[] = { 'a', 'b', 'c' };
130
131  int rv;
132  char buf[3];
133  ssize_t n;
134
135  errno = 0;
136  rv = ioctl(fd, 0xb00b);
137  rtems_test_assert(rv == -1);
138  rtems_test_assert(errno == EINVAL);
139
140  errno = 0;
141  n = write(fd, &buf[0], 1000);
142  rtems_test_assert(n == -1);
143  rtems_test_assert(errno == EIO);
144
145  errno = 0;
146  n = read(fd, &buf[0], 1000);
147  rtems_test_assert(n == -1);
148  rtems_test_assert(errno == EIO);
149
150  rtems_test_assert(
151    memcmp(&bus->simple_read_write.buf[0], &zero[0], sizeof(buf)) == 0
152  );
153
154  n = write(fd, &abc[0], sizeof(buf));
155  rtems_test_assert(n == (ssize_t) sizeof(buf));
156
157  rtems_test_assert(
158    memcmp(&bus->simple_read_write.buf[0], &abc[0], sizeof(buf)) == 0
159  );
160
161  n = read(fd, &buf[0], sizeof(buf));
162  rtems_test_assert(n == (ssize_t) sizeof(buf));
163
164  rtems_test_assert(memcmp(&buf[0], &abc[0], sizeof(buf)) == 0);
165}
166
167static void test(void)
168{
169  rtems_resource_snapshot snapshot;
170  test_bus *bus;
171  int rv;
172  int fd;
173  uint8_t read_mode_8;
174  uint32_t read_mode_32;
175  uint32_t read_speed;
176  uint8_t read_bits_per_word;
177  uint8_t read_lsb_first;
178  spi_ioc_transfer msg;
179
180  rtems_resource_snapshot_take(&snapshot);
181
182  bus = (test_bus *) spi_bus_alloc_and_init(sizeof(*bus));
183  rtems_test_assert(bus != NULL);
184
185  bus->base.transfer = test_transfer;
186  bus->base.destroy = test_destroy;
187  bus->base.setup = test_setup;
188
189  bus->simple_read_write.base.transfer = test_simple_read_write_transfer;
190  bus->device = &bus->simple_read_write.base;
191
192  bus->max_speed_hz = 50000000;
193
194  rv = spi_bus_register(&bus->base, &bus_path[0]);
195  rtems_test_assert(rv == 0);
196
197  fd = open(&bus_path[0], O_RDWR);
198  rtems_test_assert(fd >= 0);
199
200  rv = ioctl(fd, SPI_BUS_OBTAIN);
201  rtems_test_assert(rv == 0);
202
203  rv = ioctl(fd, SPI_BUS_RELEASE);
204  rtems_test_assert(rv == 0);
205
206  rv = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
207  rtems_test_assert(rv == 0);
208  rv = ioctl(fd, SPI_IOC_RD_MAX_SPEED_HZ, &read_speed);
209  rtems_test_assert(rv == 0);
210  rtems_test_assert(read_speed == speed);
211
212  speed = 60000000;
213  rv = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
214  rtems_test_assert(rv == -1);
215
216  rv = ioctl(fd, SPI_IOC_WR_LSB_FIRST, &lsb_first);
217  rtems_test_assert(rv == 0);
218  rv = ioctl(fd, SPI_IOC_RD_LSB_FIRST, &read_lsb_first);
219  rtems_test_assert(rv == 0);
220  rtems_test_assert(read_lsb_first == lsb_first);
221
222  rv = ioctl(fd, SPI_IOC_WR_MODE, &mode_8);
223  rtems_test_assert(rv == 0);
224  rv = ioctl(fd, SPI_IOC_RD_MODE, &read_mode_8);
225  rtems_test_assert(rv == 0);
226  rtems_test_assert(read_mode_8 == mode_8);
227
228  rv = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits_per_word);
229  rtems_test_assert(rv == 0);
230  rv = ioctl(fd, SPI_IOC_RD_BITS_PER_WORD, &read_bits_per_word);
231  rtems_test_assert(rv == 0);
232  rtems_test_assert(read_bits_per_word == bits_per_word);
233
234  bits_per_word = 7;
235  rv = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits_per_word);
236  rtems_test_assert(rv == -1);
237
238  rv = ioctl(fd, SPI_IOC_WR_MODE32, &mode_32);
239  rtems_test_assert(rv == 0);
240  rv = ioctl(fd, SPI_IOC_RD_MODE32, &read_mode_32);
241  rtems_test_assert(rv == 0);
242  rtems_test_assert(read_mode_32 == mode_32);
243
244  bus->msg_count = 1;
245  ioctl(fd, SPI_IOC_MESSAGE(8192), &msg);
246  rtems_test_assert(bus->msg_count == 0);
247
248  test_simple_read_write(bus, fd);
249
250  rv = close(fd);
251  rtems_test_assert(rv == 0);
252
253  rv = unlink(&bus_path[0]);
254  rtems_test_assert(rv == 0);
255
256  rtems_test_assert(rtems_resource_snapshot_check(&snapshot));
257}
258
259static void Init(rtems_task_argument arg)
260{
261  (void)arg;
262
263  TEST_BEGIN();
264
265  test();
266
267  TEST_END();
268  rtems_test_exit(0);
269}
270
271#define CONFIGURE_MICROSECONDS_PER_TICK 2000
272
273#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
274#define CONFIGURE_APPLICATION_NEEDS_SIMPLE_CONSOLE_DRIVER
275
276#define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 7
277
278#define CONFIGURE_MAXIMUM_TASKS 1
279
280#define CONFIGURE_MAXIMUM_SEMAPHORES 1
281
282#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION
283
284#define CONFIGURE_RTEMS_INIT_TASKS_TABLE
285
286#define CONFIGURE_INIT
287
288#include <rtems/confdefs.h>
Note: See TracBrowser for help on using the repository browser.