| 1 | build-type: config-file |
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| 2 | content: | |
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| 3 | MEMORY { |
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| 4 | NULL : ORIGIN = 0x00000000, LENGTH = ${STM32H7_MEMORY_NULL_SIZE:#010x} |
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| 5 | ITCM : ORIGIN = ${STM32H7_MEMORY_NULL_SIZE:#010x}, LENGTH = ${STM32H7_MEMORY_ITCM_SIZE:#010x} |
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| 6 | FLASH : ORIGIN = 0x08000000, LENGTH = ${STM32H7_MEMORY_FLASH_SIZE:#010x} |
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| 7 | DTCM : ORIGIN = 0x20000000, LENGTH = ${STM32H7_MEMORY_DTCM_SIZE:#010x} |
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| 8 | SRAM_AXI : ORIGIN = 0x24000000, LENGTH = ${STM32H7_MEMORY_SRAM_AXI_SIZE:#010x} |
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| 9 | SRAM_1 : ORIGIN = 0x30000000, LENGTH = ${STM32H7_MEMORY_SRAM_1_SIZE:#010x} |
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| 10 | SRAM_2 : ORIGIN = 0x30020000, LENGTH = ${STM32H7_MEMORY_SRAM_2_SIZE:#010x} |
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| 11 | SRAM_3 : ORIGIN = 0x30040000, LENGTH = ${STM32H7_MEMORY_SRAM_3_SIZE:#010x} |
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| 12 | SRAM_4 : ORIGIN = 0x38000000, LENGTH = ${STM32H7_MEMORY_SRAM_4_SIZE:#010x} |
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| 13 | SRAM_BACKUP : ORIGIN = 0x38800000, LENGTH = ${STM32H7_MEMORY_SRAM_BACKUP_SIZE:#010x} |
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| 14 | PERIPHERAL : ORIGIN = 0x40000000, LENGTH = ${STM32H7_MEMORY_PERIPHERAL_SIZE:#010x} |
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| 15 | NOR : ORIGIN = 0x60000000, LENGTH = ${STM32H7_MEMORY_NOR_SIZE:#010x} |
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| 16 | SDRAM_1 : ORIGIN = 0x70000000, LENGTH = ${STM32H7_MEMORY_SDRAM_1_SIZE:#010x} |
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| 17 | NAND : ORIGIN = 0x80000000, LENGTH = ${STM32H7_MEMORY_NAND_SIZE:#010x} |
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| 18 | QUADSPI : ORIGIN = 0x90000000, LENGTH = ${STM32H7_MEMORY_QUADSPI_SIZE:#010x} |
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| 19 | SDRAM_2 : ORIGIN = 0xd0000000, LENGTH = ${STM32H7_MEMORY_SDRAM_2_SIZE:#010x} |
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| 20 | } |
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| 21 | |
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| 22 | stm32h7_memory_null_begin = ORIGIN (NULL); |
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| 23 | stm32h7_memory_null_end = ORIGIN (NULL) + LENGTH (NULL); |
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| 24 | stm32h7_memory_null_size = LENGTH (NULL); |
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| 25 | |
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| 26 | stm32h7_memory_itcm_begin = ORIGIN (ITCM); |
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| 27 | stm32h7_memory_itcm_end = ORIGIN (ITCM) + LENGTH (ITCM); |
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| 28 | stm32h7_memory_itcm_size = LENGTH (ITCM); |
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| 29 | |
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| 30 | stm32h7_memory_flash_begin = ORIGIN (FLASH); |
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| 31 | stm32h7_memory_flash_end = ORIGIN (FLASH) + LENGTH (FLASH); |
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| 32 | stm32h7_memory_flash_size = LENGTH (FLASH); |
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| 33 | |
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| 34 | stm32h7_memory_dtcm_begin = ORIGIN (DTCM); |
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| 35 | stm32h7_memory_dtcm_end = ORIGIN (DTCM) + LENGTH (DTCM); |
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| 36 | stm32h7_memory_dtcm_size = LENGTH (DTCM); |
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| 37 | |
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| 38 | stm32h7_memory_sram_axi_begin = ORIGIN (SRAM_AXI); |
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| 39 | stm32h7_memory_sram_axi_end = ORIGIN (SRAM_AXI) + LENGTH (SRAM_AXI); |
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| 40 | stm32h7_memory_sram_axi_size = LENGTH (SRAM_AXI); |
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| 41 | |
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| 42 | stm32h7_memory_sram_1_begin = ORIGIN (SRAM_1); |
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| 43 | stm32h7_memory_sram_1_end = ORIGIN (SRAM_1) + LENGTH (SRAM_1); |
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| 44 | stm32h7_memory_sram_1_size = LENGTH (SRAM_1); |
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| 45 | |
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| 46 | stm32h7_memory_sram_2_begin = ORIGIN (SRAM_2); |
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| 47 | stm32h7_memory_sram_2_end = ORIGIN (SRAM_2) + LENGTH (SRAM_2); |
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| 48 | stm32h7_memory_sram_2_size = LENGTH (SRAM_2); |
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| 49 | |
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| 50 | stm32h7_memory_sram_3_begin = ORIGIN (SRAM_3); |
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| 51 | stm32h7_memory_sram_3_end = ORIGIN (SRAM_3) + LENGTH (SRAM_3); |
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| 52 | stm32h7_memory_sram_3_size = LENGTH (SRAM_3); |
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| 53 | |
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| 54 | stm32h7_memory_sram_4_begin = ORIGIN (SRAM_4); |
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| 55 | stm32h7_memory_sram_4_end = ORIGIN (SRAM_4) + LENGTH (SRAM_4); |
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| 56 | stm32h7_memory_sram_4_size = LENGTH (SRAM_4); |
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| 57 | |
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| 58 | stm32h7_memory_sram_backup_begin = ORIGIN (SRAM_BACKUP); |
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| 59 | stm32h7_memory_sram_backup_end = ORIGIN (SRAM_BACKUP) + LENGTH (SRAM_BACKUP); |
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| 60 | stm32h7_memory_sram_backup_size = LENGTH (SRAM_BACKUP); |
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| 61 | |
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| 62 | stm32h7_memory_peripheral_begin = ORIGIN (PERIPHERAL); |
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| 63 | stm32h7_memory_peripheral_end = ORIGIN (PERIPHERAL) + LENGTH (PERIPHERAL); |
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| 64 | stm32h7_memory_peripheral_size = LENGTH (PERIPHERAL); |
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| 65 | |
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| 66 | stm32h7_memory_nor_begin = ORIGIN (NOR); |
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| 67 | stm32h7_memory_nor_end = ORIGIN (NOR) + LENGTH (NOR); |
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| 68 | stm32h7_memory_nor_size = LENGTH (NOR); |
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| 69 | |
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| 70 | stm32h7_memory_sdram_1_begin = ORIGIN (SDRAM_1); |
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| 71 | stm32h7_memory_sdram_1_end = ORIGIN (SDRAM_1) + LENGTH (SDRAM_1); |
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| 72 | stm32h7_memory_sdram_1_size = LENGTH (SDRAM_1); |
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| 73 | |
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| 74 | stm32h7_memory_nand_begin = ORIGIN (NAND); |
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| 75 | stm32h7_memory_nand_end = ORIGIN (NAND) + LENGTH (NAND); |
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| 76 | stm32h7_memory_nand_size = LENGTH (NAND); |
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| 77 | |
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| 78 | stm32h7_memory_quadspi_begin = ORIGIN (QUADSPI); |
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| 79 | stm32h7_memory_quadspi_end = ORIGIN (QUADSPI) + LENGTH (QUADSPI); |
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| 80 | stm32h7_memory_quadspi_size = LENGTH (QUADSPI); |
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| 81 | |
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| 82 | stm32h7_memory_sdram_2_begin = ORIGIN (SDRAM_2); |
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| 83 | stm32h7_memory_sdram_2_end = ORIGIN (SDRAM_2) + LENGTH (SDRAM_2); |
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| 84 | stm32h7_memory_sdram_2_size = LENGTH (SDRAM_2); |
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| 85 | enabled-by: true |
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| 86 | install-path: ${BSP_LIBDIR} |
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| 87 | links: [] |
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| 88 | target: linkcmds.memory |
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| 89 | type: build |
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| 90 | SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause |
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| 91 | copyrights: |
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| 92 | - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) |
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