source: rtems/spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml @ d0eaf3ec

Last change on this file since d0eaf3ec was 5fe49a08, checked in by Kinsey Moore <kinsey.moore@…>, on 05/18/21 at 19:51:46

bsps/aarch64: Add MMU driver to relax alignment

Currently, the AArch64 BSPs have a hard time running on real hardware
without building the toolchain and the bsps with -mstrict-align in
multiple places. Configuring the MMU on these chips allows for unaligned
memory accesses for non-device memory which avoids requiring strict
alignment in the toolchain and in the BSPs themselves.

In writing this driver, it was found that the synchronous exception
handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to
avoid thread stack misalignments in RTEMS_DEBUG mode. This is now
avoided by exactly preserving thread mode stack and flags and the new
implementation is compatible with the draft information provided on the
mailing list covering the Exception Management API.
  • Property mode set to 100644
File size: 3.7 KB
Line 
1SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
2build-type: config-file
3content: |
4  /* SPDX-License-Identifier: BSD-2-Clause */
5
6  /*
7   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
8   * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
9   *
10   * Redistribution and use in source and binary forms, with or without
11   * modification, are permitted provided that the following conditions
12   * are met:
13   * 1. Redistributions of source code must retain the above copyright
14   *    notice, this list of conditions and the following disclaimer.
15   * 2. Redistributions in binary form must reproduce the above copyright
16   *    notice, this list of conditions and the following disclaimer in the
17   *    documentation and/or other materials provided with the distribution.
18   *
19   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28   * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29   * POSSIBILITY OF SUCH DAMAGE.
30   */
31
32  MEMORY {
33    RAM       : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
34    NOCACHE   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
35    RAM_MMU   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
36  }
37
38  REGION_ALIAS ("REGION_START",          RAM);
39  REGION_ALIAS ("REGION_VECTOR",         RAM);
40  REGION_ALIAS ("REGION_TEXT",           RAM);
41  REGION_ALIAS ("REGION_TEXT_LOAD",      RAM);
42  REGION_ALIAS ("REGION_RODATA",         RAM);
43  REGION_ALIAS ("REGION_RODATA_LOAD",    RAM);
44  REGION_ALIAS ("REGION_DATA",           RAM);
45  REGION_ALIAS ("REGION_DATA_LOAD",      RAM);
46  REGION_ALIAS ("REGION_FAST_TEXT",      RAM);
47  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
48  REGION_ALIAS ("REGION_FAST_DATA",      RAM);
49  REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
50  REGION_ALIAS ("REGION_BSS",            RAM);
51  REGION_ALIAS ("REGION_WORK",           RAM);
52  REGION_ALIAS ("REGION_STACK",          RAM);
53  REGION_ALIAS ("REGION_NOCACHE",        NOCACHE);
54  REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
55
56  bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? bsp_stack_exception_size : 1024;
57
58  bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
59
60  bsp_vector_table_in_start_section = 1;
61
62  bsp_translation_table_base = ORIGIN (RAM_MMU);
63  bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);
64
65  OUTPUT_FORMAT ("elf32-littleaarch64")
66  OUTPUT_ARCH (aarch64:ilp32)
67
68  INCLUDE linkcmds.base
69copyrights:
70- Copyright (C) 2020 On-Line Applications Research (OAR)
71enabled-by: true
72install-path: ${BSP_LIBDIR}
73links: []
74target: linkcmds
75type: build
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