1 | @c |
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2 | @c COPYRIGHT (c) 2014. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | |
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7 | @chapter Symmetric Multiprocessing Services |
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8 | |
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9 | @section Introduction |
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10 | |
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11 | This chapter describes the services related to Symmetric Multiprocessing |
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12 | provided by RTEMS. |
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13 | |
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14 | The application level services currently provided are: |
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15 | |
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16 | @itemize @bullet |
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17 | @item @code{rtems_get_processor_count} - Get processor count |
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18 | @item @code{rtems_get_current_processor} - Get current processor index |
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19 | @item @code{rtems_scheduler_ident} - Get ID of a scheduler |
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20 | @item @code{rtems_scheduler_get_processor_set} - Get processor set of a scheduler |
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21 | @item @code{rtems_task_get_scheduler} - Get scheduler of a task |
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22 | @item @code{rtems_task_set_scheduler} - Set scheduler of a task |
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23 | @item @code{rtems_task_get_affinity} - Get task processor affinity |
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24 | @item @code{rtems_task_set_affinity} - Set task processor affinity |
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25 | @end itemize |
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26 | |
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27 | @c |
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28 | @c |
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29 | @c |
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30 | @section Background |
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31 | |
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32 | @subsection Uniprocessor versus SMP Parallelism |
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33 | |
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34 | Uniprocessor systems have long been used in embedded systems. In this hardware |
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35 | model, there are some system execution characteristics which have long been |
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36 | taken for granted: |
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37 | |
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38 | @itemize @bullet |
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39 | @item one task executes at a time |
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40 | @item hardware events result in interrupts |
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41 | @end itemize |
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42 | |
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43 | There is no true parallelism. Even when interrupts appear to occur |
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44 | at the same time, they are processed in largely a serial fashion. |
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45 | This is true even when the interupt service routines are allowed to |
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46 | nest. From a tasking viewpoint, it is the responsibility of the real-time |
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47 | operatimg system to simulate parallelism by switching between tasks. |
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48 | These task switches occur in response to hardware interrupt events and explicit |
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49 | application events such as blocking for a resource or delaying. |
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50 | |
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51 | With symmetric multiprocessing, the presence of multiple processors |
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52 | allows for true concurrency and provides for cost-effective performance |
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53 | improvements. Uniprocessors tend to increase performance by increasing |
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54 | clock speed and complexity. This tends to lead to hot, power hungry |
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55 | microprocessors which are poorly suited for many embedded applications. |
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56 | |
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57 | The true concurrency is in sharp contrast to the single task and |
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58 | interrupt model of uniprocessor systems. This results in a fundamental |
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59 | change to uniprocessor system characteristics listed above. Developers |
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60 | are faced with a different set of characteristics which, in turn, break |
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61 | some existing assumptions and result in new challenges. In an SMP system |
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62 | with N processors, these are the new execution characteristics. |
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63 | |
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64 | @itemize @bullet |
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65 | @item N tasks execute in parallel |
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66 | @item hardware events result in interrupts |
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67 | @end itemize |
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68 | |
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69 | There is true parallelism with a task executing on each processor and |
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70 | the possibility of interrupts occurring on each processor. Thus in contrast |
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71 | to their being one task and one interrupt to consider on a uniprocessor, |
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72 | there are N tasks and potentially N simultaneous interrupts to consider |
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73 | on an SMP system. |
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74 | |
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75 | This increase in hardware complexity and presence of true parallelism |
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76 | results in the application developer needing to be even more cautious |
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77 | about mutual exclusion and shared data access than in a uniprocessor |
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78 | embedded system. Race conditions that never or rarely happened when an |
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79 | application executed on a uniprocessor system, become much more likely |
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80 | due to multiple threads executing in parallel. On a uniprocessor system, |
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81 | these race conditions would only happen when a task switch occurred at |
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82 | just the wrong moment. Now there are N-1 tasks executing in parallel |
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83 | all the time and this results in many more opportunities for small |
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84 | windows in critical sections to be hit. |
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85 | |
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86 | @subsection Task Affinity |
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87 | |
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88 | @cindex task affinity |
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89 | @cindex thread affinity |
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90 | |
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91 | RTEMS provides services to manipulate the affinity of a task. Affinity |
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92 | is used to specify the subset of processors in an SMP system on which |
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93 | a particular task can execute. |
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94 | |
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95 | By default, tasks have an affinity which allows them to execute on any |
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96 | available processor. |
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97 | |
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98 | Task affinity is a possible feature to be supported by SMP-aware |
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99 | schedulers. However, only a subset of the available schedulers support |
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100 | affinity. Although the behavior is scheduler specific, if the scheduler |
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101 | does not support affinity, it is likely to ignore all attempts to set |
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102 | affinity. |
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103 | |
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104 | @subsection Task Migration |
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105 | |
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106 | @cindex task migration |
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107 | @cindex thread migration |
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108 | |
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109 | With more than one processor in the system tasks can migrate from one processor |
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110 | to another. There are three reasons why tasks migrate in RTEMS. |
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111 | |
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112 | @itemize @bullet |
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113 | @item The scheduler changes explicitly via @code{rtems_task_set_scheduler()} or |
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114 | similar directives. |
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115 | @item The task resumes execution after a blocking operation. On a priority |
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116 | based scheduler it will evict the lowest priority task currently assigned to a |
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117 | processor in the processor set managed by the scheduler instance. |
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118 | @item The task moves temporarily to another scheduler instance due to locking |
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119 | protocols like @cite{Migratory Priority Inheritance} or the |
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120 | @cite{Multiprocessor Resource Sharing Protocol}. |
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121 | @end itemize |
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122 | |
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123 | Task migration should be avoided so that the working set of a task can stay on |
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124 | the most local cache level. |
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125 | |
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126 | The current implementation of task migration in RTEMS has some implications |
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127 | with respect to the interrupt latency. It is crucial to preserve the system |
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128 | invariant that a task can execute on at most one processor in the system at a |
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129 | time. This is accomplished with a boolean indicator in the task context. The |
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130 | processor architecture specific low-level task context switch code will mark |
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131 | that a task context is no longer executing and waits that the heir context |
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132 | stopped execution before it restores the heir context and resumes execution of |
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133 | the heir task. So there is one point in time in which a processor is without a |
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134 | task. This is essential to avoid cyclic dependencies in case multiple tasks |
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135 | migrate at once. Otherwise some supervising entity is necessary to prevent |
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136 | life-locks. Such a global supervisor would lead to scalability problems so |
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137 | this approach is not used. Currently the thread dispatch is performed with |
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138 | interrupts disabled. So in case the heir task is currently executing on |
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139 | another processor then this prolongs the time of disabled interrupts since one |
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140 | processor has to wait for another processor to make progress. |
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141 | |
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142 | It is difficult to avoid this issue with the interrupt latency since interrupts |
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143 | normally store the context of the interrupted task on its stack. In case a |
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144 | task is marked as not executing we must not use its task stack to store such an |
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145 | interrupt context. We cannot use the heir stack before it stopped execution on |
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146 | another processor. So if we enable interrupts during this transition we have |
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147 | to provide an alternative task independent stack for this time frame. This |
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148 | issue needs further investigation. |
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149 | |
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150 | @subsection Critical Section Techniques and SMP |
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151 | |
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152 | As discussed earlier, SMP systems have opportunities for true parallelism |
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153 | which was not possible on uniprocessor systems. Consequently, multiple |
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154 | techniques that provided adequate critical sections on uniprocessor |
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155 | systems are unsafe on SMP systems. In this section, some of these |
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156 | unsafe techniques will be discussed. |
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157 | |
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158 | In general, applications must use proper operating system provided mutual |
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159 | exclusion mechanisms to ensure correct behavior. This primarily means |
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160 | the use of binary semaphores or mutexes to implement critical sections. |
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161 | |
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162 | @subsubsection Disable Interrupts |
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163 | |
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164 | Again on a uniprocessor system, there is only a single processor which |
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165 | logically executes a single task and takes interrupts. On an SMP system, |
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166 | each processor may take an interrupt. When the application disables |
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167 | interrupts, it generally does so by altering a processor register to |
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168 | mask interrupts and later to re-enable them. On a uniprocessor system, |
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169 | changing this in the single processor is sufficient. However, on an SMP |
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170 | system, this register in @strong{ALL} processors must be changed. There |
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171 | are no comparable capabilities in an SMP system to disable all interrupts |
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172 | across all processors. |
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173 | |
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174 | @subsubsection Highest Priority Task Assumption |
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175 | |
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176 | On a uniprocessor system, it is safe to assume that when the highest |
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177 | priority task in an application executes, it will execute without being |
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178 | preempted until it voluntarily blocks. Interrupts may occur while it is |
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179 | executing, but there will be no context switch to another task unless |
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180 | the highest priority task voluntarily initiates it. |
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181 | |
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182 | Given the assumption that no other tasks will have their execution |
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183 | interleaved with the highest priority task, it is possible for this |
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184 | task to be constructed such that it does not need to acquire a binary |
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185 | semaphore or mutex for protected access to shared data. |
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186 | |
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187 | In an SMP system, it cannot be assumed there will never be a single task |
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188 | executing. It should be assumed that every processor is executing another |
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189 | application task. Further, those tasks will be ones which would not have |
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190 | been executed in a uniprocessor configuration and should be assumed to |
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191 | have data synchronization conflicts with what was formerly the highest |
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192 | priority task which executed without conflict. |
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193 | |
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194 | @subsubsection Disable Preemption |
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195 | |
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196 | On a uniprocessor system, disabling preemption in a task is very similar |
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197 | to making the highest priority task assumption. While preemption is |
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198 | disabled, no task context switches will occur unless the task initiates |
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199 | them voluntarily. And, just as with the highest priority task assumption, |
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200 | there are N-1 processors also running tasks. Thus the assumption that no |
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201 | other tasks will run while the task has preemption disabled is violated. |
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202 | |
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203 | @subsection Task Unique Data and SMP |
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204 | |
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205 | Per task variables are a service commonly provided by real-time operating |
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206 | systems for application use. They work by allowing the application |
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207 | to specify a location in memory (typically a @code{void *}) which is |
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208 | logically added to the context of a task. On each task switch, the |
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209 | location in memory is stored and each task can have a unique value in |
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210 | the same memory location. This memory location is directly accessed as a |
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211 | variable in a program. |
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212 | |
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213 | This works well in a uniprocessor environment because there is one task |
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214 | executing and one memory location containing a task-specific value. But |
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215 | it is fundamentally broken on an SMP system because there are always N |
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216 | tasks executing. With only one location in memory, N-1 tasks will not |
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217 | have the correct value. |
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218 | |
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219 | This paradigm for providing task unique data values is fundamentally |
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220 | broken on SMP systems. |
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221 | |
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222 | @subsubsection Classic API Per Task Variables |
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223 | |
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224 | The Classic API provides three directives to support per task variables. These are: |
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225 | |
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226 | @itemize @bullet |
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227 | @item @code{@value{DIRPREFIX}task_variable_add} - Associate per task variable |
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228 | @item @code{@value{DIRPREFIX}task_variable_get} - Obtain value of a a per task variable |
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229 | @item @code{@value{DIRPREFIX}task_variable_delete} - Remove per task variable |
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230 | @end itemize |
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231 | |
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232 | As task variables are unsafe for use on SMP systems, the use of these |
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233 | services should be eliminated in all software that is to be used in |
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234 | an SMP environment. It is recommended that the application developer |
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235 | consider the use of POSIX Keys or Thread Local Storage (TLS). POSIX Keys |
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236 | are not enabled in all RTEMS configurations. |
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237 | |
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238 | @b{STATUS}: As of March 2014, some support services in the |
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239 | @code{rtems/cpukit} use per task variables. When these uses are |
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240 | eliminated, the per task variable directives will be disabled when |
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241 | building RTEMS in SMP configuration. |
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242 | |
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243 | @c |
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244 | @c |
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245 | @c |
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246 | @section Operations |
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247 | |
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248 | @subsection Setting Affinity to a Single Processor |
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249 | |
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250 | On some embedded applications targeting SMP systems, it may be beneficial to |
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251 | lock individual tasks to specific processors. In this way, one can designate a |
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252 | processor for I/O tasks, another for computation, etc.. The following |
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253 | illustrates the code sequence necessary to assign a task an affinity for |
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254 | processor with index @code{processor_index}. |
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255 | |
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256 | @example |
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257 | @group |
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258 | #include <rtems.h> |
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259 | #include <assert.h> |
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260 | |
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261 | void pin_to_processor(rtems_id task_id, int processor_index) |
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262 | @{ |
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263 | rtems_status_code sc; |
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264 | cpu_set_t cpuset; |
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265 | |
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266 | CPU_ZERO(&cpuset); |
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267 | CPU_SET(processor_index, &cpuset); |
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268 | |
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269 | sc = rtems_task_set_affinity(task_id, sizeof(cpuset), &cpuset); |
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270 | assert(sc == RTEMS_SUCCESSFUL); |
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271 | @} |
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272 | @end group |
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273 | @end example |
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274 | |
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275 | It is important to note that the @code{cpuset} is not validated until the |
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276 | @code{@value{DIRPREFIX}task_set_affinity} call is made. At that point, |
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277 | it is validated against the current system configuration. |
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278 | |
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279 | @c |
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280 | @c |
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281 | @c |
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282 | @section Directives |
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283 | |
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284 | This section details the symmetric multiprocessing services. A subsection |
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285 | is dedicated to each of these services and describes the calling sequence, |
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286 | related constants, usage, and status codes. |
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287 | |
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288 | @c |
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289 | @c rtems_get_processor_count |
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290 | @c |
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291 | @page |
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292 | @subsection GET_PROCESSOR_COUNT - Get processor count |
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293 | |
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294 | @subheading CALLING SEQUENCE: |
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295 | |
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296 | @ifset is-C |
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297 | @example |
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298 | uint32_t rtems_get_processor_count(void); |
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299 | @end example |
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300 | @end ifset |
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301 | |
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302 | @ifset is-Ada |
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303 | @end ifset |
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304 | |
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305 | @subheading DIRECTIVE STATUS CODES: |
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306 | |
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307 | The count of processors in the system. |
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308 | |
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309 | @subheading DESCRIPTION: |
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310 | |
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311 | On uni-processor configurations a value of one will be returned. |
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312 | |
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313 | On SMP configurations this returns the value of a global variable set during |
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314 | system initialization to indicate the count of utilized processors. The |
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315 | processor count depends on the physically or virtually available processors and |
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316 | application configuration. The value will always be less than or equal to the |
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317 | maximum count of application configured processors. |
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318 | |
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319 | @subheading NOTES: |
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320 | |
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321 | None. |
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322 | |
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323 | @c |
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324 | @c rtems_get_current_processor |
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325 | @c |
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326 | @page |
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327 | @subsection GET_CURRENT_PROCESSOR - Get current processor index |
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328 | |
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329 | @subheading CALLING SEQUENCE: |
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330 | |
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331 | @ifset is-C |
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332 | @example |
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333 | uint32_t rtems_get_current_processor(void); |
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334 | @end example |
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335 | @end ifset |
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336 | |
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337 | @ifset is-Ada |
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338 | @end ifset |
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339 | |
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340 | @subheading DIRECTIVE STATUS CODES: |
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341 | |
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342 | The index of the current processor. |
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343 | |
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344 | @subheading DESCRIPTION: |
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345 | |
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346 | On uni-processor configurations a value of zero will be returned. |
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347 | |
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348 | On SMP configurations an architecture specific method is used to obtain the |
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349 | index of the current processor in the system. The set of processor indices is |
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350 | the range of integers starting with zero up to the processor count minus one. |
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351 | |
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352 | Outside of sections with disabled thread dispatching the current processor |
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353 | index may change after every instruction since the thread may migrate from one |
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354 | processor to another. Sections with disabled interrupts are sections with |
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355 | thread dispatching disabled. |
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356 | |
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357 | @subheading NOTES: |
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358 | |
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359 | None. |
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360 | |
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361 | @c |
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362 | @c rtems_scheduler_ident |
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363 | @c |
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364 | @page |
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365 | @subsection SCHEDULER_IDENT - Get ID of a scheduler |
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366 | |
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367 | @subheading CALLING SEQUENCE: |
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368 | |
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369 | @ifset is-C |
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370 | @example |
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371 | rtems_status_code rtems_scheduler_ident( |
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372 | rtems_name name, |
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373 | rtems_id *id |
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374 | ); |
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375 | @end example |
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376 | @end ifset |
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377 | |
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378 | @ifset is-Ada |
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379 | @end ifset |
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380 | |
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381 | @subheading DIRECTIVE STATUS CODES: |
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382 | |
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383 | @code{@value{RPREFIX}SUCCESSFUL} - successful operation@* |
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384 | @code{@value{RPREFIX}INVALID_ADDRESS} - @code{id} is NULL@* |
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385 | @code{@value{RPREFIX}INVALID_NAME} - invalid scheduler name@* |
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386 | @code{@value{RPREFIX}UNSATISFIED} - - a scheduler with this name exists, but |
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387 | the processor set of this scheduler is empty |
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388 | |
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389 | @subheading DESCRIPTION: |
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390 | |
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391 | Identifies a scheduler by its name. The scheduler name is determined by the |
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392 | scheduler configuration. @xref{Configuring a System Configuring |
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393 | Clustered/Partitioned Schedulers}. |
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394 | |
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395 | @subheading NOTES: |
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396 | |
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397 | None. |
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398 | |
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399 | @c |
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400 | @c rtems_scheduler_get_processor_set |
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401 | @c |
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402 | @page |
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403 | @subsection SCHEDULER_GET_PROCESSOR_SET - Get processor set of a scheduler |
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404 | |
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405 | @subheading CALLING SEQUENCE: |
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406 | |
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407 | @ifset is-C |
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408 | @example |
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409 | rtems_status_code rtems_scheduler_get_processor_set( |
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410 | rtems_id scheduler_id, |
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411 | size_t cpusetsize, |
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412 | cpu_set_t *cpuset |
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413 | ); |
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414 | @end example |
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415 | @end ifset |
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416 | |
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417 | @ifset is-Ada |
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418 | @end ifset |
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419 | |
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420 | @subheading DIRECTIVE STATUS CODES: |
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421 | |
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422 | @code{@value{RPREFIX}SUCCESSFUL} - successful operation@* |
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423 | @code{@value{RPREFIX}INVALID_ADDRESS} - @code{cpuset} is NULL@* |
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424 | @code{@value{RPREFIX}INVALID_ID} - invalid scheduler id@* |
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425 | @code{@value{RPREFIX}INVALID_NUMBER} - the affinity set buffer is too small for |
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426 | set of processors owned by the scheduler |
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427 | |
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428 | @subheading DESCRIPTION: |
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429 | |
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430 | Returns the processor set owned by the scheduler in @code{cpuset}. A set bit |
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431 | in the processor set means that this processor is owned by the scheduler and a |
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432 | cleared bit means the opposite. |
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433 | |
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434 | @subheading NOTES: |
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435 | |
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436 | None. |
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437 | |
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438 | @c |
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439 | @c rtems_task_get_scheduler |
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440 | @c |
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441 | @page |
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442 | @subsection TASK_GET_SCHEDULER - Get scheduler of a task |
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443 | |
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444 | @subheading CALLING SEQUENCE: |
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445 | |
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446 | @ifset is-C |
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447 | @example |
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448 | rtems_status_code rtems_task_get_scheduler( |
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449 | rtems_id id, |
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450 | rtems_id *scheduler_id |
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451 | ); |
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452 | @end example |
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453 | @end ifset |
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454 | |
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455 | @ifset is-Ada |
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456 | @end ifset |
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457 | |
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458 | @subheading DIRECTIVE STATUS CODES: |
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459 | |
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460 | @code{@value{RPREFIX}SUCCESSFUL} - successful operation@* |
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461 | @code{@value{RPREFIX}INVALID_ADDRESS} - @code{scheduler_id} is NULL@* |
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462 | @code{@value{RPREFIX}INVALID_ID} - invalid task id |
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463 | |
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464 | @subheading DESCRIPTION: |
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465 | |
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466 | Returns the scheduler identifier of a task in @code{scheduler_id}. |
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467 | |
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468 | @subheading NOTES: |
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469 | |
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470 | None. |
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471 | |
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472 | @c |
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473 | @c rtems_task_set_scheduler |
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474 | @c |
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475 | @page |
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476 | @subsection TASK_SET_SCHEDULER - Set scheduler of a task |
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477 | |
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478 | @subheading CALLING SEQUENCE: |
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479 | |
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480 | @ifset is-C |
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481 | @example |
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482 | rtems_status_code rtems_task_set_scheduler( |
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483 | rtems_id id, |
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484 | rtems_id scheduler_id |
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485 | ); |
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486 | @end example |
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487 | @end ifset |
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488 | |
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489 | @ifset is-Ada |
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490 | @end ifset |
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491 | |
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492 | @subheading DIRECTIVE STATUS CODES: |
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493 | |
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494 | @code{@value{RPREFIX}SUCCESSFUL} - successful operation@* |
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495 | @code{@value{RPREFIX}INVALID_ID} - invalid task or scheduler id@* |
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496 | @code{@value{RPREFIX}INCORRECT_STATE} - the task is in the wrong state to |
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497 | perform a scheduler change |
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498 | |
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499 | @subheading DESCRIPTION: |
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500 | |
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501 | Sets the scheduler of a task specified by @code{scheduler_id}. The scheduler |
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502 | of a task is initialized to the scheduler of the task that created it. |
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503 | |
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504 | @subheading NOTES: |
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505 | |
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506 | None. |
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507 | |
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508 | @subheading EXAMPLE: |
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509 | |
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510 | @example |
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511 | @group |
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512 | #include <rtems.h> |
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513 | #include <assert.h> |
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514 | |
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515 | void task(rtems_task_argument arg); |
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516 | |
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517 | void example(void) |
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518 | @{ |
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519 | rtems_status_code sc; |
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520 | rtems_id task_id; |
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521 | rtems_id scheduler_id; |
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522 | rtems_name scheduler_name; |
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523 | |
---|
524 | scheduler_name = rtems_build_name('W', 'O', 'R', 'K'); |
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525 | |
---|
526 | sc = rtems_scheduler_ident(scheduler_name, &scheduler_id); |
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527 | assert(sc == RTEMS_SUCCESSFUL); |
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528 | |
---|
529 | sc = rtems_task_create( |
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530 | rtems_build_name('T', 'A', 'S', 'K'), |
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531 | 1, |
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532 | RTEMS_MINIMUM_STACK_SIZE, |
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533 | RTEMS_DEFAULT_MODES, |
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534 | RTEMS_DEFAULT_ATTRIBUTES, |
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535 | &task_id |
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536 | ); |
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537 | assert(sc == RTEMS_SUCCESSFUL); |
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538 | |
---|
539 | sc = rtems_task_set_scheduler(task_id, scheduler_id); |
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540 | assert(sc == RTEMS_SUCCESSFUL); |
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541 | |
---|
542 | sc = rtems_task_start(task_id, task, 0); |
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543 | assert(sc == RTEMS_SUCCESSFUL); |
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544 | @} |
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545 | @end group |
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546 | @end example |
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547 | |
---|
548 | @c |
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549 | @c rtems_task_get_affinity |
---|
550 | @c |
---|
551 | @page |
---|
552 | @subsection TASK_GET_AFFINITY - Get task processor affinity |
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553 | |
---|
554 | @subheading CALLING SEQUENCE: |
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555 | |
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556 | @ifset is-C |
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557 | @example |
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558 | rtems_status_code rtems_task_get_affinity( |
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559 | rtems_id id, |
---|
560 | size_t cpusetsize, |
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561 | cpu_set_t *cpuset |
---|
562 | ); |
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563 | @end example |
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564 | @end ifset |
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565 | |
---|
566 | @ifset is-Ada |
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567 | @end ifset |
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568 | |
---|
569 | @subheading DIRECTIVE STATUS CODES: |
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570 | |
---|
571 | @code{@value{RPREFIX}SUCCESSFUL} - successful operation@* |
---|
572 | @code{@value{RPREFIX}INVALID_ADDRESS} - @code{cpuset} is NULL@* |
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573 | @code{@value{RPREFIX}INVALID_ID} - invalid task id@* |
---|
574 | @code{@value{RPREFIX}INVALID_NUMBER} - the affinity set buffer is too small for |
---|
575 | the current processor affinity set of the task |
---|
576 | |
---|
577 | @subheading DESCRIPTION: |
---|
578 | |
---|
579 | Returns the current processor affinity set of the task in @code{cpuset}. A set |
---|
580 | bit in the affinity set means that the task can execute on this processor and a |
---|
581 | cleared bit means the opposite. |
---|
582 | |
---|
583 | @subheading NOTES: |
---|
584 | |
---|
585 | None. |
---|
586 | |
---|
587 | @c |
---|
588 | @c rtems_task_set_affinity |
---|
589 | @c |
---|
590 | @page |
---|
591 | @subsection TASK_SET_AFFINITY - Set task processor affinity |
---|
592 | |
---|
593 | @subheading CALLING SEQUENCE: |
---|
594 | |
---|
595 | @ifset is-C |
---|
596 | @example |
---|
597 | rtems_status_code rtems_task_set_affinity( |
---|
598 | rtems_id id, |
---|
599 | size_t cpusetsize, |
---|
600 | const cpu_set_t *cpuset |
---|
601 | ); |
---|
602 | @end example |
---|
603 | @end ifset |
---|
604 | |
---|
605 | @ifset is-Ada |
---|
606 | @end ifset |
---|
607 | |
---|
608 | @subheading DIRECTIVE STATUS CODES: |
---|
609 | |
---|
610 | @code{@value{RPREFIX}SUCCESSFUL} - successful operation@* |
---|
611 | @code{@value{RPREFIX}INVALID_ADDRESS} - @code{cpuset} is NULL@* |
---|
612 | @code{@value{RPREFIX}INVALID_ID} - invalid task id@* |
---|
613 | @code{@value{RPREFIX}INVALID_NUMBER} - invalid processor affinity set |
---|
614 | |
---|
615 | @subheading DESCRIPTION: |
---|
616 | |
---|
617 | Sets the processor affinity set for the task specified by @code{cpuset}. A set |
---|
618 | bit in the affinity set means that the task can execute on this processor and a |
---|
619 | cleared bit means the opposite. |
---|
620 | |
---|
621 | @subheading NOTES: |
---|
622 | |
---|
623 | None. |
---|