source: rtems/doc/user/intr.t @ dc2b337

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1@c
2@c  COPYRIGHT (c) 1988-1998.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@chapter Interrupt Manager
10
11@section Introduction
12
13Any real-time executive must provide a mechanism for
14quick response to externally generated interrupts to satisfy the
15critical time constraints of the application.  The interrupt
16manager provides this mechanism for RTEMS.  This manager permits
17quick interrupt response times by providing the critical ability
18to alter task execution which allows a task to be preempted upon
19exit from an ISR.  The interrupt manager includes the following
20directive:
21
22@itemize @bullet
23@item @code{@value{DIRPREFIX}interrupt_catch} - Establish an ISR
24@item @code{@value{DIRPREFIX}interrupt_disable} - Disable Interrupts
25@item @code{@value{DIRPREFIX}interrupt_enable} - Enable Interrupts
26@item @code{@value{DIRPREFIX}interrupt_flash} - Flash Interrupt
27@item @code{@value{DIRPREFIX}interrupt_is_in_progress} - Is an ISR in Progress
28@end itemize
29
30@section Background
31
32@subsection Processing an Interrupt
33
34@cindex interrupt processing
35
36The interrupt manager allows the application to
37connect a function to a hardware interrupt vector.  When an
38interrupt occurs, the processor will automatically vector to
39RTEMS.  RTEMS saves and restores all registers which are not
40preserved by the normal @value{LANGUAGE} calling convention
41for the target
42processor and invokes the user's ISR.  The user's ISR is
43responsible for processing the interrupt, clearing the interrupt
44if necessary, and device specific manipulation.
45
46The @code{@value{DIRPREFIX}interrupt_catch}
47directive connects a procedure to
48an interrupt vector.  The interrupt service routine is assumed
49to abide by these conventions and have a prototype similar to
50the following:
51
52@ifset is-C
53@example
54rtems_isr user_isr(
55  rtems_vector_number vector
56);
57@end example
58@end ifset
59
60@ifset is-Ada
61@example
62procedure User_ISR (
63  vector : in     RTEMS.Vector_Number
64);
65@end example
66@end ifset
67
68The vector number argument is provided by RTEMS to
69allow the application to identify the interrupt source.  This
70could be used to allow a single routine to service interrupts
71from multiple instances of the same device.  For example, a
72single routine could service interrupts from multiple serial
73ports and use the vector number to identify which port requires
74servicing.
75
76To minimize the masking of lower or equal priority
77level interrupts, the ISR should perform the minimum actions
78required to service the interrupt.  Other non-essential actions
79should be handled by application tasks.  Once the user's ISR has
80completed, it returns control to the RTEMS interrupt manager
81which will perform task dispatching and restore the registers
82saved before the ISR was invoked.
83
84The RTEMS interrupt manager guarantees that proper
85task scheduling and dispatching are performed at the conclusion
86of an ISR.  A system call made by the ISR may have readied a
87task of higher priority than the interrupted task.  Therefore,
88when the ISR completes, the postponed dispatch processing must
89be performed.  No dispatch processing is performed as part of
90directives which have been invoked by an ISR.
91
92Applications must adhere to the following rule if
93proper task scheduling and dispatching is to be performed:
94
95@itemize @b{ }
96
97@item @b{The interrupt manager must be used for all ISRs which
98may be interrupted by the highest priority ISR which invokes an
99RTEMS directive.}
100
101@end itemize
102
103Consider a processor which allows a numerically low
104interrupt level to interrupt a numerically greater interrupt
105level.  In this example, if an RTEMS directive is used in a
106level 4 ISR, then all ISRs which execute at levels 0 through 4
107must use the interrupt manager.
108
109Interrupts are nested whenever an interrupt occurs
110during the execution of another ISR.  RTEMS supports efficient
111interrupt nesting by allowing the nested ISRs to terminate
112without performing any dispatch processing.  Only when the
113outermost ISR terminates will the postponed dispatching occur.
114
115@subsection RTEMS Interrupt Levels
116
117@cindex interrupt levels
118
119Many processors support multiple interrupt levels or
120priorities.  The exact number of interrupt levels is processor
121dependent.  RTEMS internally supports 256 interrupt levels which
122are mapped to the processor's interrupt levels.  For specific
123information on the mapping between RTEMS and the target
124processor's interrupt levels, refer to the Interrupt Processing
125chapter of the Applications Supplement document for a specific
126target processor.
127
128@subsection Disabling of Interrupts by RTEMS
129
130@cindex disabling interrupts
131
132During the execution of directive calls, critical
133sections of code may be executed.  When these sections are
134encountered, RTEMS disables all maskable interrupts before the
135execution of the section and restores them to the previous level
136upon completion of the section.  RTEMS has been optimized to
137insure that interrupts are disabled for a minimum length of
138time.  The maximum length of time interrupts are disabled by
139RTEMS is processor dependent and is detailed in the Timing
140Specification chapter of the Applications Supplement document
141for a specific target processor.
142
143Non-maskable interrupts (NMI) cannot be disabled, and
144ISRs which execute at this level MUST NEVER issue RTEMS system
145calls.  If a directive is invoked, unpredictable results may
146occur due to the inability of RTEMS to protect its critical
147sections.  However, ISRs that make no system calls may safely
148execute as non-maskable interrupts.
149
150@section Operations
151
152@subsection Establishing an ISR
153
154The @code{@value{DIRPREFIX}interrupt_catch}
155directive establishes an ISR for
156the system.  The address of the ISR and its associated CPU
157vector number are specified to this directive.  This directive
158installs the RTEMS interrupt wrapper in the processor's
159Interrupt Vector Table and the address of the user's ISR in the
160RTEMS' Vector Table.  This directive returns the previous
161contents of the specified vector in the RTEMS' Vector Table.
162
163@subsection Directives Allowed from an ISR
164
165Using the interrupt manager insures that RTEMS knows
166when a directive is being called from an ISR.  The ISR may then
167use system calls to synchronize itself with an application task.
168The synchronization may involve messages, events or signals
169being passed by the ISR to the desired task.  Directives invoked
170by an ISR must operate only on objects which reside on the local
171node.  The following is a list of RTEMS system calls that may be
172made from an ISR:
173
174@itemize @bullet
175@item Task Management
176
177@itemize -
178@item task_get_note, task_set_note, task_suspend, task_resume
179@end itemize
180
181@item Clock Management
182
183@itemize -
184@item clock_get, clock_tick
185@end itemize
186
187@item Message, Event, and Signal Management
188
189@itemize -
190@item message_queue_send, message_queue_urgent
191@item event_send
192@item signal_send
193@end itemize
194
195@item Semaphore Management
196
197@itemize -
198@item semaphore_release
199@end itemize
200
201@item Dual-Ported Memory Management
202
203@itemize -
204@item port_external_to_internal, port_internal_to_external
205@end itemize
206
207@item IO Management
208
209@itemize -
210@item io_initialize, io_open, io_close, io_read, io_write, io_control
211@end itemize
212
213@item Fatal Error Management
214
215@itemize -
216@item fatal_error_occurred
217@end itemize
218
219@item Multiprocessing
220
221@itemize -
222@item multiprocessing_announce
223@end itemize
224@end itemize
225
226@section Directives
227
228This section details the interrupt manager's
229directives.  A subsection is dedicated to each of this manager's
230directives and describes the calling sequence, related
231constants, usage, and status codes.
232
233@c
234@c
235@c
236@page
237@subsection INTERRUPT_CATCH - Establish an ISR
238
239@cindex establish an ISR
240@cindex install an ISR
241
242@subheading CALLING SEQUENCE:
243
244@ifset is-C
245@findex rtems_interrupt_catch
246@example
247rtems_status_code rtems_interrupt_catch(
248  rtems_isr_entry      new_isr_handler,
249  rtems_vector_number  vector,
250  rtems_isr_entry     *old_isr_handler
251);
252@end example
253@end ifset
254
255@ifset is-Ada
256@example
257procedure Interrupt_Catch (
258   New_ISR_handler : in     RTEMS.Address;
259   Vector          : in     RTEMS.Vector_Number;
260   Old_ISR_Handler :    out RTEMS.Address;
261   Result          :    out RTEMS.Status_Codes
262);
263@end example
264@end ifset
265
266@subheading DIRECTIVE STATUS CODES:
267@code{@value{RPREFIX}SUCCESSFUL} - ISR established successfully@*
268@code{@value{RPREFIX}INVALID_NUMBER} - illegal vector number@*
269@code{@value{RPREFIX}INVALID_ADDRESS} - illegal ISR entry point or invalid old_isr_handler
270
271@subheading DESCRIPTION:
272
273This directive establishes an interrupt service
274routine (ISR) for the specified interrupt vector number.  The
275@code{new_isr_handler} parameter specifies the entry point of the ISR.
276The entry point of the previous ISR for the specified vector is
277returned in @code{old_isr_handler}.
278
279To release an interrupt vector, pass the old handler's address obtained
280when the vector was first capture.
281
282@ifset is-C
283Passing a NULL pointer as the @code{old_handler} address and this parameter
284will be ignored.
285@end ifset
286
287@subheading NOTES:
288
289This directive will not cause the calling task to be preempted.
290
291@c
292@c
293@c
294@page
295@subsection INTERRUPT_DISABLE - Disable Interrupts
296
297@cindex disable interrupts
298
299@subheading CALLING SEQUENCE:
300
301@ifset is-C
302@findex rtems_interrupt_disable
303@example
304void rtems_interrupt_disable(
305  rtems_interrupt_level  level
306);
307
308/* this is implemented as a macro and sets level as a side-effect */
309@end example
310@end ifset
311
312@ifset is-Ada
313@example
314function Interrupt_Disable
315return RTEMS.ISR_Level;
316@end example
317@end ifset
318
319@subheading DIRECTIVE STATUS CODES:
320
321NONE
322
323@subheading DESCRIPTION:
324
325This directive disables all maskable interrupts and returns
326the previous @code{level}.  A later invocation of the
327@code{@value{DIRPREFIX}interrupt_enable} directive should be used to
328restore the interrupt level.
329
330@subheading NOTES:
331
332This directive will not cause the calling task to be preempted.
333
334@ifset is-C
335@b{This directive is implemented as a macro which modifies the @code{level}
336parameter.}
337@end ifset
338
339@c
340@c
341@c
342@page
343@subsection INTERRUPT_ENABLE - Enable Interrupts
344
345@cindex enable interrupts
346
347@subheading CALLING SEQUENCE:
348
349@ifset is-C
350@findex rtems_interrupt_enable
351@example
352void rtems_interrupt_enable(
353  rtems_interrupt_level  level
354);
355@end example
356@end ifset
357
358@ifset is-Ada
359@example
360procedure Interrupt_Enable (
361   Level : in     RTEMS.ISR_Level
362);
363@end example
364@end ifset
365
366@subheading DIRECTIVE STATUS CODES:
367
368NONE
369
370@subheading DESCRIPTION:
371
372This directive enables maskable interrupts to the @code{level}
373which was returned by a previous call to
374@code{@value{DIRPREFIX}interrupt_disable}.
375Immediately prior to invoking this directive, maskable interrupts should
376be disabled by a call to @code{@value{DIRPREFIX}interrupt_disable}
377and will be enabled when this directive returns to the caller.
378
379@subheading NOTES:
380
381This directive will not cause the calling task to be preempted.
382
383
384@c
385@c
386@c
387@page
388@subsection INTERRUPT_FLASH - Flash Interrupts
389
390@cindex flash interrupts
391
392@subheading CALLING SEQUENCE:
393
394@ifset is-C
395@findex rtems_interrupt_flash
396@example
397void rtems_interrupt_flash(
398  rtems_interrupt_level level
399);
400@end example
401@end ifset
402
403@ifset is-Ada
404@example
405procedure Interrupt_Flash (
406   Level : in     RTEMS.ISR_Level
407);
408@end example
409@end ifset
410
411@subheading DIRECTIVE STATUS CODES:
412
413NONE
414
415@subheading DESCRIPTION:
416
417This directive temporarily enables maskable interrupts to the @code{level}
418which was returned by a previous call to
419@code{@value{DIRPREFIX}interrupt_disable}. 
420Immediately prior to invoking this directive, maskable interrupts should
421be disabled by a call to @code{@value{DIRPREFIX}interrupt_disable}
422and will be redisabled when this directive returns to the caller.
423
424@subheading NOTES:
425
426This directive will not cause the calling task to be preempted.
427
428@c
429@c
430@c
431@page
432@subsection INTERRUPT_IS_IN_PROGRESS - Is an ISR in Progress
433
434@cindex is interrupt in progress
435
436@subheading CALLING SEQUENCE:
437
438@ifset is-C
439@findex rtems_interrupt_is_in_progress
440@example
441rtems_boolean rtems_interrupt_is_in_progress( void );
442@end example
443@end ifset
444
445@ifset is-Ada
446@example
447function Interrupt_Is_In_Progress
448return RTEMS.Boolean;
449@end example
450@end ifset
451
452@subheading DIRECTIVE STATUS CODES:
453
454NONE
455
456@subheading DESCRIPTION:
457
458This directive returns @code{TRUE} if the processor is currently
459servicing an interrupt and @code{FALSE} otherwise.  A return value
460of @code{TRUE} indicates that the caller is an interrupt service
461routine, @b{NOT} a task.  The directives available to an interrupt
462service routine are restricted.
463
464@subheading NOTES:
465
466This directive will not cause the calling task to be preempted.
467
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